Intersil Corporation HI20203 Datasheet
August 1997
HI20203
8-Bit, 160 MSPS,
Ultra High-Speed D/A Converter
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 160MHz
• 8-Bit (HI20203) Resolution
• Differential Linearity Error . . . . . . . . . . . . . . . . 0.5 LSB
• Low Glitch Noise
• Analog Multiplying Function
• Low Power Consumption . . . . . . . . . . . . . . . . . .420mW
• Evaluation Board Available
• Direct Replacement for the Sony CX20201-3, CX20202-3
Applications
• Wireless Communications
• Signal Reconstruction
• Direct Digital Synthesis
• High Definition Video Systems
• Digital Measurement Systems
• Radar
Description
The HI20203 is an 8-bit, 160MHz ultra high speed D/A converter. The converter is based on an R2R switched current
source architecture that includes an input data register with
a complement feature and is Emitter Coupled Logic (ECL)
compatible.
The HI20203 is an 8-bit accurate D/A with a linearity error of
0.5 LSB.
For 10-bit resolution, please refer to the HI20201 data sheet.
Ordering Information
PART
NUMBER
HI20203JCB -20 to 75 28 Ld SOIC M28.3A-S
HI20203JCP -20 to 75 28 Ld PDIP E28.6A-S
TEMP.
RANGE (oC) PACKAGE PKG. NO.
Pinout
(MSB) D7
D6
D5
D4
D3
D2
D1
D0
NC
NC
NC
NC
CLK
CLK
(PDIP, SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
HI20203
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
SS
V
REF
AV
EE
NC
NC
NC
NC
NC
I
OUT
NC
AV
SS
DV
SS
COMPL
DV
EE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
10-1
File Number
4096.1
Typical Application Circuit
HI20203
HI20203
DIGITAL
DAT A
(ECL)
CLK
-1.3V
131Ω
-5.2V
Functional Block Diagram
D7
D6
D5
D4
D3
D2
D1
D0
82Ω
82Ω
131Ω
D7 (MSB) (1)
D6 (2)
D5 (3)
D4 (4)
D3 (5)
D2 (6)
D1 (7)
D0 (8)
(9)
(10)
(11)
(12)
(18, 19, 21-25) NC
CLK (13)
CLK (14)
(28) AV
SS
(27) V
REF
(26) AV
EE
(20) I
OUT
(17) DV
SS
(16) COMPL
(15) DV
EE
1.5kΩ
1kΩ
2kΩ
0.047µF
75Ω COAX CABLE
D/A OUT
1.0µF
3.6kΩ
.
~2.7V
TL431CP
-5.2V
1.0µF
0.047µF
-5.2V
(LSB) D0
(MSB) D7
AV
EEAVSS
D1
D2
D3
D4
D5
D6
COMPL
CLK
CLK
DVEEDV
INPUT
BUFFER
CLOCK
BUFFER
SS
UPPER
4-BIT
ENCODER
8-BIT
REGISTER
CURRENT
15
SWITCHED
CURRENT
4 LSBs
CELLS
15
CELLS
R2R
NETWORK
BIAS CURRENT
GENERATOR
I
OUT
V
REF
10-2
HI20203
Absolute Maximum Ratings T
Digital Supply Voltage DVEE to DVSS. . . . . . . . . . . . . . . . . . . -7.0V
Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . -7.0V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to DVEE V
Reference Input Voltage. . . . . . . . . . . . . . . . . . . . . . +0.3 to AVEE V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
=25oC Thermal Information
A
Thermal Resistance (Typical, Note 5) θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage
AVEE,DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to -5.45V
AVEE - DVEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to +0.05V
Digital Input Voltage
VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to -0.7V
VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9V to -1.6V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AV
= -5.2V, DVEE = -5.2V, AGND = 0V, DGND = 0V, RL = ∞, V
EE
PARAMETER TEST CONDITION
SYSTEM PERFORMANCE
Reference Input Voltage, V
. . . . . . . . VEE + 0.5V to VEE + 1.4V
REE
Load Resistance, RL. . . . . . . . . . . . . . . . . . . . . . . . . . . . Above 75Ω
Output Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 1.2V
O(FS)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC
= -1V, TA = 25oC
OUT
HI20203JCB/JCP
UNITSMIN TYP MAX
Resolution 8 - - Bits
Integral Linearity Error, INL fS = 160MHz (End Point) - - ±0.5 LSB
Differential Linearity Error, DNL fS = 160MHz - - ±0.50 LSB
Offset Error, V
OS
(Note 3) - 1.8 - LSB
(Adjustable to Zero)
Full Scale Error, FSE
(Note 3) - - ±26 LSB
(Adjustable to Zero)
Full Scale Output Current, I
FS
- - 20 mA
DYNAMIC CHARACTERISTICS
Throughput Rate See Figure 11 160 - - MHz
Glitch Energy, GE R
= 75Ω - 15 - pV/s
OUT
REFERENCE INPUT
Voltage Reference Input Range With respect to AV
Reference Input Current V
Voltage Reference to Output Small
= -4.58V -0.1 -0.4 -3.0 µA
REF
-3dB point 1V
P-P
EE
Input - 14.0 - MHz
+0.5 - +1.4 V
Signal Bandwidth
Output Rise Time, t
Output Fall Time, t
r
f
R
= 75Ω - 1.5 - ns
LOAD
R
= 75Ω - 1.5 - ns
LOAD
DIGITAL INPUTS
Input Logic High Voltage, V
Input Logic Low Voltage, V
IH
IL
(Note 2) -1.0 -0.89 V
(Note 2) -1.75 -1.6 V
10-3
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