Intersil Corporation HI20201 Datasheet

August 1997

HI20201

10-Bit, 160 MSPS,

Ultra High Speed D/A Converter

Features

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 160MHz

• Resolution (HI20201) . . . . . . . . . . . . . . . . . . . . . . . 10-Bit

• Differential Linearity Error . . . . . . . . . . . . . . . . 0.5 LSB

• Low Glitch Noise

• Analog Multiplying Function

• Low Power Consumption . . . . . . . . . . . . . . . . . .420mW

• Evaluation Board Available

• Direct Replacement for Sony CX20201-1, CX20202-1

Applications

• Wireless Communications

• Signal Reconstruction

• Direct Digital Synthesis

• High Definition Video Systems

• Digital Measurement Systems

• Radar

Description

The HI20201 is a 160MHz ultra high speed D/A converter. The
converter is based on an R/2R switched current source archi­tecture that includes an input data register with a complement
feature and is Emitter Coupled Logic (ECL) compatible.

The HI20201 is available in acommercial temperature range
and offered in a 28 lead plastic SOIC (300 mil) and a 28 lead
plastic DIP package.

Ordering Information

PART

NUMBER

HI20201JCB -20 to 75 28 Ld SOIC M28.3A-S
HI20201JCP -20 to 75 28 Ld PDIP E28.6A-S
HI20201-EV 25 Evaluation Kit

TEMP.

RANGE (oC) PACKAGE PKG. NO.

Pinout

(MSB) D9

D8
D7
D6
D5
D4
D3
D2
D1

(LSB) D0

NC

NC
CLK
CLK

(PDIP, SOIC)

1
2
3
4
5
6
7
8

9
10
11
12
13
14

HI20201

TOP VIEW

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AV

SS

V

REF

AV

EE

NC
NC
NC
NC
NC
I

OUT

NC
AV

SS

DV

SS

COMPL
DV

EE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

10-1197

File Number 3581.5

Typical Application Circuit

HI20201

HI20201

DIGITAL

DAT A
(ECL)

CLK

-1.3V

131Ω

-5.2V

Functional Block Diagram

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

82Ω

82Ω

131Ω

D9 (MSB) (1)
D8 (2)
D7 (3)
D6 (4)
D5 (5)
D4 (6)
D3 (7)
D2 (8)
D1 (9)
D0 (LSB) (10)
(11)
(12)

(18, 19, 21-25) NC

CLK (13)
CLK (14)

(28) AV

SS

(27) V

REF

(26) AV

EE

(20) I

OUT

(17) DV

SS

(16) COMPL

(15) DV

EE

1.5kΩ
1kΩ

2kΩ

0.047µF

75Ω COAX CABLE

D/A OUT

1.0µF

3.6kΩ

.

~2.7V

TL431CP

-5.2V

1.0µF

0.047µF

-5.2V

(LSB) D0

D1

D2

D3

D4

D5

D6

D7

D8

(MSB) D9

COMPL

CLK

CLK

INPUT

BUFFER

CLOCK

BUFFER

UPPER

4-BIT

ENCODER

15

15

15

15

8-BIT

REGISTER

CURRENT

15

15

15

15

SWITCHED
CURRENT

6 LSBs
CELLS

15

CELLS

R/2R

NET/WORK

BIAS CURRENT

GENERATOR

I

OUT

V

REF

10-1198

HI20201

Absolute Maximum Ratings Thermal Information

Digital Supply Voltage DVEE to DVSS. . . . . . . . . . . . . . . . . . . -7.0V

Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . -7.0V

Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to DVEE V

Reference Input Voltage. . . . . . . . . . . . . . . . . . . . . . +0.3 to AVEE V

Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA

Recommended Operating Conditions

Supply Voltage

AVEE,DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to -5.45V

AVEE - DVEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to +0.05V

Digital Input Voltage

VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to -0.7V

VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9V to -1.6V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Reference Input Voltage, V

. . . . . . . . VEE + 0.5V to VEE + 1.4V

REF

Load Resistance, RL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≥75Ω

Output Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 1.2V

OUT

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC

Electrical Specifications T

= 25oC, AVEE = DVEE = -5.2V, AGND = DGND = 0V, RL = ∞, V

A

OUT

= -1V

HI20201JCB/JCP

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX

SYSTEM PERFORMANCE

Resolution 10 - - Bits
Integral Linearity Error, INL f
Differential Linearity Error, DNL f
Offset Error, V

(Adjustable to Zero) (Note 3) - 7 - LSB

OS

= 160MHz (End Point) - - ±1.0 LSB

S

= 160MHz - - ±0.50 LSB

S

Full Scale Error, FSE (Adjustable to Zero) (Note 3) - - ±102 LSB
Full Scale Output Current, I

FS

- - 20 mA

DYNAMIC CHARACTERISTICS

Throughput Rate See Figure 11 160 - - MHz
Glitch Energy, GE R

= 75Ω - 15 - pV/s

OUT

REFERENCE INPUT

Voltage Reference Input Range With Respect to AV
Reference Input Current V
Voltage Reference to Output Small

= -4.58V -0.1 -0.4 -3.0 µA

REF

-3dB point 1V

Input - 14.0 - MHz

P-P

EE

+0.5 - +1.4 V

Signal Bandwidth
Output Rise Time, t
Output Fall Time, t

r

f

R

= 75Ω - 1.5 - ns

LOAD

R

= 75Ω - 1.5 - ns

LOAD

DIGITAL INPUTS

Input Logic High Voltage, V
Input Logic Low Voltage, V
Input Logic Current, I

, I

IL

IH

IH

IL

(Note 2) -1.0 -0.89 V
(Note 2) -1.75 -1.6 V
VIH = -0.89V, VIL = -1.75V (Note 2) 0.1 1.5 6.0 µA

(For D9 thru D6, COMPL)
Input Logic Current, I

, IIH (For D5 thru D0) VIH = -0.89V, VIL = -1.75V (Note 2) 0.1 0.75 3.0 µA

IL

TIMING CHARACTERISTICS

Data Setup Time, t
Data Hold Time, t

SU

HLD

Propagation Delay Time, t
Settling Time, t

(to1/2 LSB) See Figure 11 - 5.2 - ns

SET

PD

See Figure 11 5 - - ns
See Figure 11 1 - - ns
See Figure 11 - 3.8 - ns

10-1199

HI20201

Electrical Specifications T

= 25oC, AVEE = DVEE = -5.2V, AGND = DGND = 0V, RL = ∞, V

A

= -1V (Continued)

OUT

HI20201JCB/JCP

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX

POWER SUPPLY CHARACTERISITICS

I

EE

-60 -75 -90 mA

Power Dissipation 75Ω load - 420 470 mW

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. Excludes error due to reference drift.

4. Electrical specifications guaranteed only under the stated operating conditions.

Timing Diagram

CLK

CLK

DAT A

0V

D/A OUT

-1V

t

SU

N

t

HD

N + 1

t

D

90%

50%

10%

t

r

N

t

D

N + 1

t

f

FIGURE 1. LADDER SETTLING TIME FULL POWER BANDWIDTH (LS)

Pin Descriptions

28 PIN SOIC PIN NAME PIN DESCRIPTION

1-10 D0 (LSB)-D9 (MSB) Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 9, the Most Significant Bit.

11, 12, 19, 21- 25 NC No Connect, not used.

13

CLK

14 CLK Positive Differential Clock Input
15 DV

EE

16 COMPL Data Complement Pin. When set to a (ECL) logic High the input data is complemented in the

17 DV
18 AV
20 I
26 AV
27 V
28 AV

SS

SS

OUT

EE

REF

SS

Negative Differential Clock Input.

Digital (ECL) Power Supply -4.75V to -7V.

input buffer. When cleared to a (ECL) logic Low the input data is not complemented.
Digital Ground.
Analog Ground.
Current Output Pin.
Analog Supply -4.75V to -7V.
Input Reference Voltage used to set the output full scale range.
Analog Ground.

10-1200