Intersil Corporation HI1396Y Datasheet

SEMICONDUCTOR

HI1396Y

April 1995

Features

• Differential Linearity Error . . . . ±0.5 LSB (Typ) or Less

• Integral Linearity Error. . . . . . . . ±0.5 LSB (Typ) or Less

• Built-In Integral Linearity Compensation Circuit

• Ultra High Speed Operation with Maximum
Conversion Rate of 125 MSPS (Min)

• Low Input Capacitance . . . . . . . . . . . . . . . . . 18pF (Typ)

• Wide Analog Input Bandwidth 200MHz (Min. for Full­Scale Input)

• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . .-5.2V

• Low Power Consumption . . . . . . . . . . . . . 870mW (Typ)

• Low Error Rate

• Operable at 50% Clock Duty Cycle

• Capable of Driving 50Ω Loads

Applications

• Video Digitizing • Communication Systems

• HDTV (High Definition TV) • Radar Systems

• Direct RF Down-Conversion • Digital Oscilloscopes

8-Bit, 125 MSPS Flash A/D Converter

Description

The HI1396Y is an 8-bit ultra high speed flash analog-to-dig­ital converter IC capable of digitizing analog signals at the
maximum rate of 125MSPS. The digital I/O levels of the con­verter are compatible with ECL 100K/10KH/10K.

The HI1396Y is available for Commercial and Industrial
applications and is supplied in die form.

Ordering Information

PART

NUMBER TEMPERATURE PACKAGE

HI1396Y +25oC Die

• All performance parameters are for packaged
devices when supplied by Harris.

Die Metallization Layer

PIN PIN

66 1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright

© Harris Corporation 1995

1

File Number

3954

Functional Block Diagram

V

R1

RT

R/2

R

R

R

HI1396Y

MINV

COMPARATOR

1

D7 (MSB)

2

D6

63

R

V

IN

R2

V

RM

V

IN

64

R

65

R

126

R

127

R

128

R

129

R

191

R

192

R

193

ENCODE

LOGIC

OUTPUT

D5

D4

D3

D2

D1

D0 (LSB)

V

RB

CLK
CLK

R3

R

254

R

255

R/2

CLOCK
DRIVER

LINV

2

Specifications HI1396Y

Absolute Maximum Ratings T

Supply Voltage (AV

Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V

Reference Input Voltage

VRT, VRB, VRM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V

|VRT-VRB|. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5V

, DVEE). . . . . . . . . . . . . . . . . . . . . . . . . . . .-7V

EE

= +25oC

A

VRM Pin Input Current (I

) . . . . . . . . . . . . . . . . . . .-3mA to +3mA

VRM

Digital Output Current (ID0 to ID7) . . . . . . . . . . . . . . .-30mA to 0mA

Storage Temperature Range (T

) . . . . . . . . . . . .-65oC to +150oC

STG

Maximum Junction Temperature

HI1396YJP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC

Digital Input Voltage

CLK, CLK, MINV, LINV. . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V

|CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions (Note 1)

Supply Voltage

, DVEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V

AV

EE

AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V

AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V

Reference Input Voltage

VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V

VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V

Electrical Specifications T

= +25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V

A

PARAMETER TEST CONDITIONS MIN MAX UNIT

Differential Linearity Error (DNL) -0.5 0.5 LSB

Integral Linearity Error (INL) -0.5 0.5 LSB

Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB to V

Pulse Width of Clock

TPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.0ns Min.

TPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.0ns Min.

RT

Resolution 8 - Bits

Input Bias Current, L

Analog Input Resistance, R

Resister-String Current, I

Reference Voltage, V

Digital Input Current HI, I

Digital Input Current LO, I

CLK Open Voltage, V

Leakage (1) D0 to D7, V

IN

IN

REF

RM

IH

IL

OPN

LEAK

Leakage (2) D0 to D7,
VIN, LINV, MINV, CLK, CLK, I

Digital Output Voltage HI, V

OH

Digital Output Voltage LO, V

Supply Current, I

EE

LEAK

OL

VIN = -1.0V 0 300 µA

VIN = -1.0V 60 500 kΩ

-22 -16 mA

-1.02 -0.98 V

Hi = -0.8V 0 50 µA

Lo = -1.6V -50 50 µA

CLK = Open -1.4 -1.2 V

I = -10µA -0.8 -0.4 V

V = 0.3V -1.0 1.0 µA

220Ω to -5.2V -1.095 -0.6 V

220Ω to -5.2V -2 -1.64 V

-220 -105 mA

3