Intersil Corporation HI1386 Datasheet
HI1386
August 1997
Features
• Differential Linearity Error ±0.5 LSB or Less
• Integral Linearity Error ±0.5 LSB or Less
• Built-In Integral Linearity Compensation Circuit
• High-Speed Operation with Maximum Conversion
Rate (Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MSPS
• Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . .17pF
• Wide Analog Input Bandwidth
(Min for Full Scale Input). . . . . . . . . . . . . . . . . . 150MHz
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . -5.2V
• Low Power Consumption (Typ) . . . . . . . . . . . . .580mW
• Low Error Rate
• Operable at 50% Clock Duty Cycle
• Capable of Driving 50Ω Loads
• Direct Replacement for CXA1386
Applications
• Video Digitizing
• RGB Graphics Processing
• HDTV (High Definition TV)
• Radar Systems
• Communication Systems
• Direct RF Down-Conversion
• Digital Oscilloscopes
8-Bit, 75 MSPS, Flash A/D Converter
Description
The HI1386 is an 8-bit, high-speed flash analog-to-digital
converter IC capable of digitizing analog signals at a
maximum rate of 75 MSPS. The digital I/O levels of this A/D
converter are compatible with ECL 100K/10KH/10K.
The HI1386 is available in the commercial and industrial
temperature range and is supplied in 28 lead plastic DIP and
44 lead ceramic LCC packages.
Ordering Information
PART
NUMBER
HI1386JCP -20 to 75 28 Ld PDIP E28.6A-S
HI1386AIL -20 to 100 44 Ld CLCC J44.B
TEMP.
RANGE (oC) PACKAGE PKG. NO.
Pinouts
HI1386 (PDIP)
TOP VIEW
1
LINV
2
DV
EE
3
DGND
D1
D2
D3
D4
D5
D6
DGND
DV
EE
MINV
4
5
6
7
8
9
10
11
12
13
14
| Copyright © Intersil Corporation 1999
(LSB) D0
(MSB) D7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
EE
V
RT
AV
EE
AGND
V
IN
AGND
V
RM
AGND
V
IN
AGND
AV
EE
V
RB
CLK
CLK
4-1148
NC
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
DGND2
NC
10
11
12
13
14
15
16
17
HI1386 (CLCC)
TOP VIEW
EE
LINV
DV
DGND2
DGND1
NC
46 3
EE
DV
DGND1
MINV
7
8
9
25
NC
CLK
1
NC
CLK
AV
EE
NC
NC
NC
EE
RT
V
AVEEAV
4041424344
39
NC
38
NC
AGND
37
V
36
IN
AGND
35
V
34
RM
AGND
33
V
32
IN
AGND
31
NC
30
NC
29
2827262524232221201918
EE
EE
RB
V
AV
AV
File Number 3583.4
Functional Block Diagram
V
R1
RT
R/2
R
R
R
HI1386
MINV
COMPARATOR
1
D7 (MSB)
2
D6
63
R
V
IN
R2
V
RM
V
IN
64
R
65
R
126
R
127
R
128
R
129
R
191
R
192
R
193
ENCODE
LOGIC
OUTPUT
D5
D4
D3
D2
D1
D0 (LSB)
V
RB
CLK
CLK
R3
R
254
R
255
R/2
CLOCK
DRIVER
LINV
4-1149
Pin Descriptions
HI1386
PIN NUMBER
ST ANDARD
VOLTAGE
19, 21,
23, 25
31, 33,
35, 37
SYMBOL I/O
AGND - 0V Analog GND. Used as GND for
LEVEL EQUIVALENT CIRCUIT DESCRIPTIONDIP LCC
input buffers and latches of
comparators. Isolated from DGND ,
DGND1, and DGND2.
18, 26,2827, 28,
40, 41,
44
AV
EE
- -5.2V Analog VEE -5.2V (Typ). Internally
connected to DVEE (Resistance:
4Ω to 6Ω). Bypass with 0.1µF to
AGND.
16 23 CLK I ECL CLK Input.
DGND, DGND1
15 22 CLK Input Complementary to CLK.
When open pulled down to -1.3V.
R
Device is operable without CLK
input, but use of complementary
inputs of CLK and CLK is
recommended to obtain stable
high speed operation.
CLK
CLK
R
R
R
DV
EE
RR
3, 12 - DGND - 0V Digital GND (used for internal
circuits and output transistors).
- 5, 19 DGND1 - 0V Digital GND (used for internal
circuits and output transistors).
- 6, 16 DGND2 - 0V Digital GND (used for output
buffers).
2, 13 4, 20 DV
EE
- -5.2V Digital VEE. Internally connected
to AVEE (resistance: 4Ω to 6Ω).
Bypass with 0.1µF to DGND
4 8 D0 O ECL LSB of Data Outputs. External
DGND
pull-down resistor is required.
59D1 Data Outputs. External pull-down
610D2
D1
resistors are required.
711D3
812D4
913D5
10 14 D6
DV
11 15 D7 MSB of Data Outputs. External
EE
pull-down resistor is required.
4-1150
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