Intersil Corporation HI1171 Datasheet
HI1171
August 1997
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40MHz
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit
• Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.25 LSB
• Low Glitch Noise
• Single Supply Operation. . . . . . . . . . . . . . . . . . . . . .+5V
• Low Power Consumption (Max) . . . . . . . . . . . . . .80mW
• Evaluation Board Available (HI1171-EV)
• Direct Replacement for the Sony CXD1171
Applications
• Wireless Telecommunications
• Signal Reconstruction
• Direct Digital Synthesis
• Imaging
• Presentation and Broadcast Video
• Graphics Displays
• Signal Generators
8-Bit, 40 MSPS, High Speed D/A Converter
Description
The HI1171 is an 8-bit, 40MHz, high speed D/A converter.
The converter incorporates an 8-bit input data register with
blanking capability, and current outputs. The HI1171 features low glitch outputs. The architecture is a current cell
arrangement to provide low linearity errors.
The HI1171 is available in an Industrial temperature range
and is offered in a 24 lead (200 mil) SOIC plastic package.
For dual version, please refer to the HI1177 Data Sheet.
For triple version, please refer to the HI1178 Data Sheet.
Ordering Information
PART
NUMBER
HI1171JCB -40 to 85 24 Ld SOIC M24.2-S
HI1171-EV 25 Evaluation Board
TEMP. RANGE
(oC) PACKAGE PKG. NO.
Pinout
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
BLNK
DV
V
CLK
SS
Typical Application Circuit
HI1171
(SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
B
12
24
DV
DD
23
DV
DD
22
AV
DD
21
I
OUT2
20
I
OUT1
19
AV
DD
18
AV
DD
17
VG
16
V
REF
15
I
REF
14
AV
SS
13
DV
SS
0.1µF
0.1µF
D7
D6
D5
D4
D3
D2
D1
D0
+5V
DV
(23, 24)
DD
D7 (MSB)(8)
D6 (7)
D5 (6)
D4 (5)
D3 (4)
D2 (3)
D1 (2)
D0 (LSB) (1)
CLK (12)
VB (11)
BLNK (9)
DVSS (10, 13)
HI1171
(18, 19, 22) AV
(17) V
(16) V
(20) I
(15) I
(21) I
(14) AV
DD
REF
OUT1
REF
OUT2
SS
+5V
0.1µF
0.1µF
G
1kΩ
D/A
OUT
200Ω
3.3kΩ
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
1
File Number 3662.2
Functional Block Diagram
(LSB) D0
D1
D2
HI1171
D3
D4
D5
D6
(MSB) D7
BLNK
VB
CLK
DECODER
DECODER
CLOCK
GENERATOR
8-BIT
LATCH
6 MSBs
CURRENT
CELLS
CURRENT CELLS
(FOR FULL SCALE)
BIAS VOLTAGE
GENERATOR
2 LSBs
CURRENT
CELLS
I
OUT2
I
OUT1
VG
V
-
+
I
REF
REF
2
HI1171
Absolute Maximum Ratings Thermal Information
Digital Supply Voltage DVDD to DVSS. . . . . . . . . . . . . . . . . . .+7.0V
Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . .+7.0V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maxim um Ratings” ma y cause permanent damage to the device . This is a stress only rating and oper ation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Maximum Junction Temperature, Plastic Package . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Electrical Specifications AV
= +4.75V to +5.25V, DVDD = +4.75 to +5.25V, V
DD
= +2.0V, fS = 40MHz,
REF
CLK Pulse Width = 12.5ns, TA = 25oC (Note 4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
SYSTEM PERFORMANCE
Resolution, n - 8 - Bits
Integral Linearity Error, INL fS = 40MHz (End Point) -0.5 - 1.3 LSB
Differential Linearity Error, DNL fS = 40MHz - - ±0.25 LSB
Offset Error, V
OS
(Note 2) - - 1 mV
Full Scale Error, FSE (Adjustable to Zero) (Note 2) - - ±13 LSB
Full Scale Output Current, I
Full Scale Output Voltage, V
Output Voltage Range, V
FSR
FS
FS
-1015mA
1.9 2.0 2.1 V
0.5 2.0 2.1 V
DYNAMIC CHARACTERISTICS
Throughput Rate See Figure 7 40.0 - - MHz
Glitch Energy, GE R
= 75Ω - 30 - pV-s
OUT
Differential Gain, ∆AV (Note 3) - 1.2 - %
Differential Phase, ∆φ (Note 3) - 0.5 - Degree
REFERENCE INPUT
Voltage Reference Input Range 0.5 - 2.0 V
Reference Input Resistance (Note 3) 1.0 - - MΩ
DIGITAL INPUTS
Input Logic High Voltage, V
Input Logic Low Voltage, V
Input Logic Current, IIL, I
IH
Digital Input Capacitance, C
IH
IL
IN
(Note 3) 3.0 - - V
(Note 3) - - 1.5 V
(Note 3) - - ±5.0 µA
(Note 3) - 5.0 - pF
TIMING CHARACTERISTICS
Data Setup Time, t
Data Hold Time, t
SU
HLD
See Figure 1 5 - - ns
See Figure 1 10 - - ns
3
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