Intersil Corporation HFA3925 Datasheet

HFA3925

Data Sheet July 1998 File Number

2.4GHz - 2.5GHz 250mW Power Amplifier

™

The Intersil 2.4GHz PRISM™ chip set
is a highly integrated five-chip solution
for RF modems employing Direct
Sequence Spread Spectrum (DSSS)
signaling. The HFA3925 2.4GHz-

2.5GHz, 250mW power amplifier is one of the five chips in

the PRISM™ chip set (see the Typical Application Diagram).
The Intersil HFA3925 is an integrated power amplifier with

transmit/receive switch in a low cost SSOP 28 plastic
package. The power amplifier delivers +27dB of gain with
high efficiency and can be operated with voltages as low as

2.7V. The power amplifier switch is fully monolithic and can
be controlled with CMOS logic levels.

The HFA3925 is ideally suited for QPSK, BPSK or other
linearly modulated systems in the 2.4GHz Industrial,
Scientific, and Medical (ISM) frequency band. It can also be
used in GFSK systems where levels of +25dBm are
required. Typical applications include Wireless Local Area
Network (WLAN) and wireless portable data collection.

REMEMBER: Always apply Negative power to the VG
pins before applying the PositiveV
so may result in the destruction of the HFA3925 Power
Amplifier.

bias. Failure to do

DD

4132.4

Features

• Highly Integrated Power Amplifier with T/R Switch

• Operates Over 2.7V to 6V Supply Voltage

• High Linear Output Power (P

: +24dBm)

1dB

• Individual Gate Control for Each Amplifier Stage

• Low Cost SSOP-28 Plastic Package

Applications

• Systems Targeting IEEE 802.11 Standard

• TDD Quadrature-Modulated Communication Systems

• Wireless Local Area Networks

• PCMCIA Wireless Transceivers

• ISM Systems

• TDMA Packet Protocol Radios

• PCS/Wireless PBX

Ordering Information

TEMP.

PART NUMBER

RANGE (oC) PACKAGE

HFA3925IA -40 to 85 28 Ld SSOP M28.15
HFA3925IA96 -40 to 85 Tape and Reel

PKG.

NO.

Pinout

GND
GND
GND
GND
GND
GND
GND

RX OUT

V

G2

GND

V

DD1

GND
GND

V

G1

1
2
3
4
5
6
7
8

9
10
11
12
13
14

HFA3925

(SSOP)

TOP VIEW

2-179

28

GND
V

27

T/R CNTRL

26
25

RF OUT

24

GND
V

23

GND

22
21

GND

20

GND

19

GND

18

V
V

17

GND

16
15

RF IN

Functional Block Diagram

V

(+)

DDX

TR

DD

DD3

RF IN

STAGE 1 STAGE 2 STAGE 3

DD2
G3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

VGX(-)

STAGE BIAS CONTROL

T/R CNTRL

| Copyright © Intersil Corporation 1999

RX OUT

RF_OUT

TO

ANTENNA

Typical Application Diagram

HFA3925

HFA3724

(FILE# 4067)

HF A3424 (NOTE)

(FILE# 4131)

HF A3624

UP/DOWN

CONVERTER

(FILE# 4066)

RFPA

HF A3925

VCO

VCO

(FILE# 4132)

DUAL SYNTHESIZER

HFA3524

(FILE# 4062)

TYPICAL TRANSCEIVER APPLICATION USING THE HFA3925

NOTE: Required for systems targeting 802.11 specifications.

For additional information on the PRISM™ chip set, call
[phone] to access Intersil AnswerFAXsystem.When
prompted, key in the four-digit document number (File #) of
the datasheets you wish to receive.

÷2

0o/90

QUAD IF MODULATOR

The four-digit file numbers are shown in the Typical
Application Diagram, and correspond to the appropriate
circuit

TUNE/SELECT

I

M

o

U
X

Q

HSP3824

(FILE# 4064)

RXI

RXQ

RSSI

M
U
X

A/D

DE-

SPREAD

A/D

CCA

A/D

TXI

SPREAD

TXQ

DSSS BASEBAND PROCESSOR

PRISM™ CHIP SET FILE #4063

DPSK

DEMOD

802.11

MAC-PHY

INTERFACE

DPSK

MOD.

DATA TO MACCTRL

2-180

HFA3925

Absolute Maximum Ratings Thermal Information

Maximum Input Power (Note 2) . . . . . . . . . . . . . . . . . . . . . . +23dBm

Operating Voltages (Notes 2, 3). . . . . . . . . . . .VDD = 8V, VGG = -8V

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Electrical Specifications T

POWER AMPLIFIER

Linear Gain 27 28 32 dB
VSWR In/Out - 1.75:1 ­Input Return Loss - -11.3 - dB
Output Return Loss - -11.3 - dB
Output Power at P
Second Harmonic at P
Third Harmonic at P

IDD at P1dB (VDD1 + VDD2 + VDD3)

NOTES:

2. Ambient temperature (TA) = 25oC.

3. |VDD| + |VGG| not to exceed 12V.

1dB

1dB

1dB

= 25oC, Z0 = 50Ω, VDD = +5V, PIN = -30dBm, f = 2.45GHz, Unless Otherwise Specified

A

PARAMETER MIN TYP MAX UNITS

22.5 24.5 - dBm

- -20 0 dBc

- -30 -10 dBc

- 270 375 mA

Pin Description

PINS SYMBOL DESCRIPTION

1
2 GND DC and RF Ground.
3 GND DC and RF Ground.
4 GND DC and RF Ground.
5 GND DC and RF Ground.
6 GND DC and RF Ground.
7 GND DC and RF Ground.
8 RX OUT Output of T/R Switch for receive mode.
9VG2Negative bias control for the second PA stage, adjusted to set V

10 GND DC and RF Ground.
11 V
12 GND DC and RF Ground.
13 GND DC and RF Ground.
14 V

15 RF IN RF Input of the Power Amplifier.
16 GND DC and RF Ground.

GND

DD1

G1

DC and RF Ground.

cally 53mA. Typical voltage at pin = -0.75V. Input impedance: > 1MΩ.

Positive bias for the first stage of the PA, 2.7V to 6V.

Negative bias control for the first PA stage, adjusted to set V
20mA. Typical voltage at pin = -0.75V. Input impedance: > 1MΩ.

DD2

quiescent bias current, which is typically

DD1

quiescent bias current, which is typi-

2-181