Intersil Corporation HFA3860 Datasheet

HFA3860

Data Sheet July 1998 File Number

11 Mbps Direct Sequence Spread Spectrum Baseband Processor

™

The Intersil HFA3860 Direct Sequence (DSSS) baseband processor is part of the PRISM 2.4GHz radio chipset, and contains all the functions necessary for a full or half duplex packet baseband

transceiver for applications requiring 11 Mbps performance. The HF A3860has on-board A/Ds for analog I and Q inputs, for

which the HFA3726IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability are availab le , along with M-Ary Bi-Orthogonal Keying to provide a variety of data rates. Built-in flexibility allows the HFA3860 to be configured through a general purpose control bus, for a range of applications. A Receive Signal Strength Indicator (RSSI) monitoring function with on-board 6-bit A/D provides Clear Channel Assessment (CCA)to avoiddata collisions and optimizenetwork throughput. The HF A3860 is housed in a thin plastic quad flat pac kage (TQFP) suitable for PCMCIA board applications.

Ordering Information

TEMP.

PART NO.

RANGE (oC) PKG. TYPE PKG. NO.

HFA3860IV -40 to 85 48 Ld TQFP Q48.7x7 HFA3860IV96 -40 to 85 Tape and Reel

Simpliﬁed Block Diagram

3-BIT

A/D

DEMOD.

4347

Features

• Complete DSSS Baseband Processor

• Processing Gain. . . . . . . . . . . . . . . . . . . . . . . . . . ≥10.4dB

• Programmable Data Rate. . . . . . . .1, 2, 5.5, and 11 Mbps

• Ultra Small Package. . . . . . . . . . . . . . . . . . . . 7 x 7 x 1mm

• Single Supply Operation (44MHz Max) . . . . . 2.7V to 3.6V

• Modulation Methods. . . . . . .DBPSK, DQPSK, and MBOK

• Supports Full or Half Duplex Operations

• On-Chip A/D Converters for I/Q Data (3-Bit, 22 MSPS) and RSSI (6-Bit)

• Similar Pinout to HFA3824

Applications

• Systems Targeting IEEE 802.11 WLAN Standard

• Point-to-Point Links

• DSSS PCMCIA Wireless Transceiver

• Spread Spectrum WLAN RF Modems

• TDMA Packet Protocol Radios

• Part 15 Compliant Radio Links

• Portable Bar Code Scanners/POS Terminal

• Portable PDA/Notebook Computer

• Wireless Digital Audio

• Wireless Digital Video

• PCN/Wireless PBX

Pinout

HFA3860 (TQFP)

OUT

TEST7

TEST6

TEST5

TEST4

GND

TEST3

TEST2

TEST1

TEST0

RSSI

OUT

3-BIT

A/D

6-BIT

A/D

CCA

SPREADER DE-SPREADER

ST_CK

TX_PE

PRO-

CESSOR

INTER-

FACE

MOD.

DATA TO NETWORK

PROCESSOR

CTRL

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

TXD TXCLK X_RDY

GND

DDA

GND

http://www.intersil.com or 407-727-9207

1 2

3 4 5 6

7 8 9 10 11

13 14 15 16

RSSI

DDA

REFN

GND

REFP

373839404142434445464748

36 35 34 33 32 31 30 29 28 27 26 25

2423222120191817

SDI

GND

SCLK

RXCL RXD MD_R RX_PE CCA GND MCLK V

RESET ANTSE ANTSE SD

HFA3860

Table of Contents

PAGE

Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Typical Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Control Port (4 Wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

TX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

RX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

I/Q A/D Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

A/D Calibration Circuit and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

RSSI A/D Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Test Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Transmitter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Header/Packet Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Scrambler and Data Encoder Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Spread Spectrum Modulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Clear Channel Assessment (CCA) and Energy Detect (ED) Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Demodulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Acquisition Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PN Correlators Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Demodulation and Tracking Description (DBPSK and DQPSK Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Data Decoder and Descrambler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Data Demodulation and Tracking Description (BMBOK and QMBOK Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Demodulator Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

A Default Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Typical Application Diagram

For additional information on the PRISM™ chip set, call (407) 724-7800 to access Intersil’ AnswerFAXsystem. When prompted, key in the four-digit document number (File #) of the data sheets you wish to receive.

The four-digit ﬁle numbers are shown in the Typical Application Diagram, and correspond to the appropriate circuit.

HFA3860

HF A3424 (NOTE)

(FILE# 4131)

HF A3624

UP/DOWN

CONVERTER

(FILE# 4066)

RFPA

HF A3925

(FILE# 4132)

HFA3524

TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3860

NOTE: Required for systems targeting 802.11 speciﬁcations.

VCO

DUAL SYNTHESIZER

(FILE# 4062)

÷2

0o/90

QUAD IF MODULATOR

HFA3726

(FILE# 4067)

HF A3860

(FILE# 4347)

RXI

RXQ

RSSI

M U X

A/D

DE-

SPREAD

A/D

CCA

A/D

TXI

SPREAD

TXQ

DSSS BASEBAND PROCESSOR

DEMOD

802.11

MAC-PHY

INTERFACE

MOD.

DATA TO MACCTRL

Pin Descriptions

NAME PIN TYPE I/O DESCRIPTION

DDA

(Analog)

(Digital)

GND

(Analog)

GND

(Digital)

REFN

REFP

ANTSEL 26 O The antenna select signal changes state as the receiver switches from antenna to antenna during the

ANTSEL 27 O The antenna select signal changes state as the receiver switches from antenna to antenna during the

RSSI 14 I Receive Signal Strength Indicator Analog input.

10, 18, 20 Power DC power supply 2.7V - 3.6V (Not Hardwired Together On Chip).

7, 21, 29, 42 Power DC power supply 2.7 - 3.6V

11, 15, 19 Ground DC power supply 2.7 - 3.6V, ground (Not Hardwired Together On Chip).

6, 22, 31, 41 Ground DC power supply 2.7 - 3.6V, ground.

17 I “Negative” voltage reference for A/D’s (I and Q) [Relative to V

REFP

16 I “Positive” voltage reference for A/D’s (I, Q and RSSI) 12 I Analog input to the internal 3-bit A/D of the In-phase received data. 13 I Analog input to the internal 3-bit A/D of the Quadrature received data.

acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 27) for differential drive of antenna switches.

acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 26) for differential drive of antenna switches.

]

HFA3860

Pin Descriptions

NAME PIN TYPE I/O DESCRIPTION

TX_PE 2 I When active, the transmitter is conﬁgured to be operational, otherwise the transmitter is in standby

TXD 3 I TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network

TXCLK 4 O TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to

TX_RDY 5 O TX_RDY is an output to the external network processor indicating that Preamble and Header

CCA 32 O Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The

RXD 35 O RXD is an output to the external network processor transferring demodulated Header information and

RXCLK 36 O RXCLK is the bit clock output. This clock is used to transfer Header information and payload data

MD_RDY 34 O MD_RDY is an output signal to the network processor, indicating header data and a data packet are

RX_PE 33 I When active, the receiver is conﬁgured to be operational, otherwise the receiver is in standby mode.

SD 25 I/O SD is a serial bi-directional data bus which is used to transfer address and data to/from the internal

SCLK 24 I SCLK is the clock for the SD serial bus.The data on SD is clocked at the rising edge. SCLK is an input

SDI 23 I This pin is not used in the 4 wire interface described in this data sheet. It should not be left ﬂoating.

R/W8 IR/W is an input to the HFA3860 used to change the direction of the SD bus when reading or writing

CS 9 I CS is a Chip select for the device to activate the serial control port.The CS doesn’t impact any of the

TEST 7:0 37, 38, 39,

40, 43, 44,

45, 46

(Continued)

mode. TX_PE is an input from the external Media Access Controller (MAC) or network processor to the HFA3860. The rising edge of TX_PE will start the internal transmit state machine and the falling edge will initiate shut down of the state machine. TX_PE envelopes the transmit data exceptforthe last bit. The transmitter will continue to run for 3 symbols after TX_PE goes inactive to allow the PAto shut down gracefully.

processor to the HFA3860. The data is received serially with the LSB ﬁrst. The data is clocked in the HFA3860 at the rising edge of TXCLK.

the HFA3860, synchronously. Transmit data on the TXD bus is clocked into the HFA3860 on the rising edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the clock will be dependent upon the data rate that is programmed in the signalling ﬁeld of the header.

information has been generated and that the HFA3860 is ready to receive the data packet from the network processor over the TXD serial bus. The TX_RDY returns to the inactive state when the last chip of the last symbol has been output.

CCA algorithm makes its decision as a function of RSSI, Energy Detect (ED), and Carrier Sense (CRS). The CCA algorithm and its features are described elsewhere in the data sheet. Logic 0 = Channel is clear to transmit. Logic 1 = Channel is NOT clear to transmit (busy). This polarity is programmable and can be inverted.

data in a serial format. The data is sent serially with the LSB ﬁrst. The data is frame aligned with MD_RDY.

through the RXD serial bus to the network processor. This clock reﬂects the bit rate in use. RXCLK is held to a logic “0” state during the CRC16 reception. RXCLK becomes active after the SFD has been detected. Data should be sampled on the rising edge. This polarity is programmable and can be inverted.

ready to be transferred to the processor. MD_RDY is an active high signal and it envelopes the data transfer over the RXD serial bus. MD_RDY goes active when the SFD is detected and returns to its inactive state when RX_PE goes inactive or an error is detected in the header.

This is an active high input signal. In standby, RX_PE inactive, all A/D converters are disabled.

registers. The bit ordering of an 8-bit word is MSB ﬁrst. The ﬁrst 8 bits during transfers indicate the register address immediately followedby 8 more bits representing the data that needs to be written or read at that register.

clock and it is asynchronous to the internal master clock (MCLK)The maximum rate of this clock is 11MHz or one half the master clock frequency, whichever is lower.

data on the SD bus. R/W also enables the serial shift register used in a read cycle. R/W must be set up prior to the rising edge of SCLK. A high level indicates read while a low level is a write.

other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low signal. When inactive SD, SCLK, and R/W become “don’t care” signals.

O This is a data port that can be programmed to bring out internal signals or data for monitoring. These

bits are primarily reserved by the manufacturer for testing. A further description of the test port is given at the appropriate section of this data sheet.

HFA3860

Pin Descriptions

NAME PIN TYPE I/O DESCRIPTION

TEST_CK 1 O This is the clock that is used in conjunction with the data that is being output from the test bus (TEST

RESET 28 I Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the

MCLK 30 I Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to

OUT

NOTE: Total of 48 pins; ALL pins are used.

External Interfaces

There are three primary digital interface ports for the HFA3860 that are used for conﬁguration and during normal operation of the device as shown in Figure 1. These ports are:

• The Control Port, which is used to conﬁgure, write and/or read the status of the internal HFA3860 registers.

• The TX Port, which is used to accept the data that needs to be transmitted from the network processor.

• The RX Port, which is used to output the received demodulated data to the network processor.

In addition to these primary digital interfaces the device includes a byte wide parallel Test Port which can be conﬁgured to output various internal signals and/or data. The device can also be set into various power consumption modes by external control. The HFA3860 contains three Analog to Digital (A/D) converters. The analog interfaces to the HFA3860 include, the In phase (I) and quadrature (Q) data component inputs, and the RF signal strength indicator input. A reference voltage divider is also required external to the device.

(Continued)

0-7).

HFA3860 goes into the power standby mode. RESET does not alter any of the configuration register values nor does it preset any of the registers into default values. Device requires programming upon power-up. After RESET is de-activated, RX_PE must be activated for at least 2 MCLKs before RX and TX functions are restored.

generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks. 48 O TX Spread baseband I digital output data. Data is output at the chip rate. 47 O TX Spread baseband Q digital output data. Data is output at the chip rate.

Control Port (4 Wire)

The serial control port is used to serially write and read data to/from the device. This serial port can operate up to a 11MHz rate or 1/2 the maximum master clock rate of the device, MCLK (whichever is lower). MCLK must be running during programming. This port is used to program and to read all internal registers. The ﬁrst 8 bits always represent the address followed immediately by the 8 data bits for that register. The two LSBs of address are don’t care, but reserved for future expansion. The serial transfers are accomplished through the serial data pin (SD). SD is a bidirectional serial data bus. Chip Select ( Read/

Write (R/W) are also required as handshake signals for this port. The clock used in conjunction with the address and data on SD is SCLK. This clock is provided by the external source and it is an input to the HFA3860.The timing relationships of these signals are illustrated in Figures 2 and

3. R/

W is high when data is to be read, and low when it is to be written. machine. transfer cycle. The serial control port operates asynchronously from the TX and RX ports and it can accomplish data transfers

CS is an asynchronous reset to the state

CS must be active (low) during the entire data

CS selects the serial control port device only.

CS), and

independent of the activity at the other digital or analog

ANTSEL

ANALOG

INPUTS

REFERENCE

A/D

POWER

DOWN

SIGNALS

TEST

PORT

HFA3860

I (ANALOG) Q (ANALOG) RSSI (ANALOG)

REFN

REFP

TX_PE RX_PE

RESET

TEST

FIGURE 1. EXTERNAL INTERFACE

TXD

TXCLK

TX_RDY

RXD RXC

MD_RDY

C SD

SCLK

SDI

TX_PORT

RX_PORT

CONTROL_PORT

ports. The HF A3860 has 32 internal registers that can be accessed

through the control port. These registers are listed in the Configuration and Control Internal Register table. Table 1 lists the configuration register number,a brief name describing the register,and the HEX address to access each of the registers. The type indicates whether the corresponding register is Read only (R) or Read/Write (R/W). Some registers are two bytes wide as indicated on the table (high and low bytes).

See Tech Brief #360 on timing issues between the serial clock (SCLK) and the chip master clock (MCLK).

HFA3860

SCLK

FIRST ADDRESS BIT

7654321076543210

1234567 01234567

FIRST DATABIT OUT

LSBDATA OUTMSBMSB ADDRESS IN

NOTES:

1. The HFA3860 always uses the rising edge of SCLK. SD, R/W and CS hold times allow the controller to use either the rising or falling edge.

2. This port operates essentially the same as the HFA 3824 with the exception that the AS signal of the 3824 is not required.

FIGURE 2. CONTROL PORT READ TIMING

SCLK

R/W

7654321076543210

1234567 012345670

LSBDATA INMSBMSB ADDRESS IN

FIGURE 3. CONTROL PORT WRITE TIMING

TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST

CONFIGURATION

CR0 Part/Version Code R 00 CR1 I/O Polarity R/W 04 CR2 TX and RX Control R/W 08 CR3 A/D_CAL_POS Register R/W 0C CR4 A/D_CAL_NEG Register R/W 10 CR5 CCA Antenna Control R/W 14 CR6 Preamble Length R/W 18 CR7 Scramble_Tap (RX and TX) R/W 1C CR8 RX_SQ1_ ACQ (High) Threshold R/W 20

CR9 RX-SQ1_ ACQ (Low) Threshold R/W 24 CR10 RX_SQ2_ ACQ (High) Threshold R/W 28 CR11 RX-SQ2_ ACQ (Low) Threshold R/W 2C CR12 SQ1 CCA Thresh (High) R/W 30 CR13 SQ1 CCA Thresh (Low) R/W 34 CR14 ED or RSSI Thresh R/W 38 CR15 SFD Timer R/W 3C CR16 Signal Field (BPSK - 11 Chip Sequence) R/W 40 CR17 Signal Field (QPSK - 11 Chip Sequence) R/W 44

ADDRESS HEX

HFA3860

TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST (Continued)

CONFIGURATION

CR18 Signal Field (BPSK - Mod. Walsh Sequence) R/W 48 CR19 Signal Field (QPSK - Mod. Walsh Sequence) R/W 4C CR20 TX Signal Field R/W 50 CR21 TX Service Field R/W 54 CR22 TX Length Field (High) R/W 58 CR23 TX Length Field (Low) R/W 5C CR24 RX Status R 60 CR25 RX Service Field Status R 64 CR26 RX Length Field Status (High) R 68 CR27 RX Length Field Status (Low) R 6C CR28 Test Bus Address R/W 70 CR29 Test Bus Monitor R 74 CR30 Test Register 1, Must Load 00H R/W 78 CR31 Test Register 2, Must Load 02H R/W 7C

ADDRESS HEX

TX Port

The transmit data port accepts the data that needs to be transmitted serially from an external data source. The data is modulated and transmitted as soon as it is received from the external data source. The serial data is input to the HF A3860 through TXD using the next rising edge of TXCLK to clock it in the HF A3860. TXCLK is an output from the HFA3860. A timing scenario of the transmit signal handshakes and sequence is shown on timing diagram Figure 4.

The external processor initiates the transmit sequence by asserting TX_PE. TX_PE envelopes the transmit data packet onTXD.The HFA3860responds bygeneratinga Preamble and Header. Bef ore the last bit of the Header is sent, the HFA3860 begins generating TXCLK to input the serial data on TXD. TXCLK will run until TX_PE goes back to its inactive state indicating the end of the data packet. The user needs to hold TX_PE high for as many clocks as there bits to transmit. For the higher data rates, this will be in multiples of the number of bits per symbol. The HF A3860 will continue to output modulated signal for 2 flush the modulation path. TX_PE must be held until the last data bit is sampled. The minimum TX_PE inactive pulse required to restart the preamble and header generation is

2.22

µs after the last data bit is output, to supply bits to

µs and to reset the modulator is 4.22µs.

the preamble has been generated and the device is ready to receive the data packet (MPDU) to be transmitted from the external processor. Signals TX_RDY, TX_PE and TXCLK can be set individually, by programming Configuration Register (CR) 1, as either active high or active low signals.

The transmit port is completely independent from the operation of the other interface ports including the RX port, therefore supporting a full duplex mode.

The HFA3860 internally generates the preamble and header information from information supplied via the control registers. The external source needs to provide only the data portion of the packet and set the control registers. The timing diagram of this process is illustrated on Figure

4. Assertion of TX_PE will initialize the generation of the preamble and header. TX_RDY, which is an output from the HFA3860, is used to indicate to the external processor that

TXCLK

HFA3860

TX_PE

TXD

TX_RDY

NOTE: Preamble/Header and Data is transmitted LSB ﬁrst. TXD shown generated from rising edge of TXCLK.

RXCLK

RX_PE

HEADER FIELDS

PROCESSING

MD_RDY

RXD

NOTE: MD_RDY active after CRC16. See detailed timing diagrams on page 35.

PREAMBLE/HEADER

FIRST DATA BIT SAMPLED

LSB DATA PACKET

FIGURE 4. TX PORT TIMING

MPDU DATA

LSB DATA MSB

FIGURE 5. RX PORT TIMING

MSB

LAST DATA BIT SAMPLED

DEASSERTED WHEN LAST CHIP OF MPDU CLEARS MOD PATH OF 3860

RX Port

The timing diagram Figure 5 illustrates the relationships between the various signals of the RX port. The receive data port serially outputs the demodulated data from RXD. The data is output as soon as it is demodulated by the HFA3860. RX_PE must be at its active state throughout the receive operation. When RX_PE is inactive the device's receive functions, including acquisition, will be in a stand by mode.

RXCLK is an output from the HFA3860 and is the clock for the ser ial demodulated data on RXD.MD_RDY is an output from the HFA3860 and it may be set to go active after SFD or CRC fields. Note that RXCLK becomes active after the Start Frame Delimiter (SFD) to clock out the Signal, Service, and Length fields, then goes inactive during the header CRC field. RXCLK becomes active again for the MPDU.MD_RDY retur ns to its inactive state after RX_PE is deactivated by the external controller,or if a header error is detected. A header error is either a failure of the CRC check, or the failure of the received signal field to match one of the 4 programmed signal fields. For either type of header error, the HFA3860 will reset itself after reception of the CRC field. If MD_RDY had been set to go active after CRC, it will remain low.

MD_RDY and RXCLK can be configured through CR 1, bit 6-7 to be active low, or active high. The receive port is completely independent from the operation of the other interface ports including the TX port, supporting therefore a full duplex mode.

I/Q A/D Interface

The PRISM baseband processor chip (HFA3860) includes two 3-bit Analog to Digital converters (A/Ds) that sample the analog input from the IF down converter. The I/Q A/D clock, samples at twice the chip rate. The nominal sampling rate is 22MHz.

The interface speciﬁcations for the I and Q A/Ds are listed in Table 2.

HFA3860

TABLE 2. I, Q, A/D SPECIFICATIONS

PARAMETER MIN TYP MAX

Full Scale Input Voltage (V Input Bandwidth (-0.5dB) - 20MHz Input Capacitance (pF) - 5 Input Impedance (DC) 5kΩ -FS (Sampling Frequency) - 22 22MHz

The voltages applied to pin 16,V

) 0.25 0.50 1.0

P-P

and pin 17, V

REFP

REFN

set the references for the internal I and Q A/D converters. In addition, V reference. For a nominal I/Q input of 500mV suggested V V

is 0.93V. V

REFN

is also used to set the RSSI A/D converter

REFP

voltage is 1.75V, and the suggested

REFP

should never be less than 0.25V.

REFN

P-P

, the

Figure 6 illustrates the suggested interface conﬁguration for the A/Ds and the reference circuits

Since these A/Ds are intended to sample AC voltages, their inputs are biased internally and they should be capacitively coupled. The HPF corner frequency in the baseband receive path should be less than 1kHz.

A/D Calibration Circuit and Registers

The A/D compensation or calibration circuit is designed to optimize A/D performance for the I and Q inputs by maintaining the full 3-bit resolution of the outputs. There are two registers (CR 3 AD_CAL_POS and CR 4 AD_CAL_NEG) that set the parameters for the internal I and Q A/D calibration circuit.

Both I and Q A/D outputs are monitored by the A/D calibration circuit as shown in Figure 7 and if either has a full scale value, a 24-bit accumulator is incremented as deﬁned by parameter AD_CAL_POS. If neither has a full scale value, the accumulator is decremented as deﬁned by parameter AD_CAL_NEG. The output of this accumulator is used to drive D/A converters that adjust the A/D’s references. Loop gain reduction is accomplished by using only the 5 MSBs out of the 24 bits. The compensation adjustment is updated at a 1kHz rate. The A/D calibration circuit is only intended to remove slow component variations.

Forbest performance, the optimum probability that either the I or Q A/D converter is at the saturation level was determined to be 33%. The probability P is set by the formula:

P(AD_CAL_POS)+(1-P)(AD_CAL_NEG) = 0.

REFP

REFN

HFA3860

3.9K

0.15µF

8.2K

9.1K

FIGURE 6. INTERFACES

0.01µF

The A/D section includes a compensation (calibration) circuit that automatically adjusts for temperature and component variations of the RF and IF strips. The variations in gain of limiters, AGC circuits, ﬁlters etc. can be compensated for up to ±4dB. Without the compensation circuit, the A/Ds could see a loss of up to 1.5 bits of the 3 bits of quantization. The A/D calibration circuit adjusts the A/D reference voltages to maintain optimum quantization of the IF input over this variation range. It works on the principle of setting the reference to insure that the signal is at full scale (saturation) a certain percentage of the time. Note that this is not an AGC and it will compensate only for slow variations in signal levels (several seconds).

The procedure for setting the A/D references to accommodate various input signal voltage lev els is to set the reference voltages so that the A/D calibration circuit is operating at half scale with the nominal input. This leaves the maximum amount of adjustment room for circuit tolerances.

One solution to this formula for P = 1/3 is: AD_CAL_POS= 2

AD_CAL_NEG = -1 This also sets the levels so that operation with either NOISE

or SIGNAL is approximately the same. It is assumed that the RF and IF sections of the receiver have enough gain to cause limiting on thermal noise. This will keep the levels at the A/D approximately the same regardless of whether signal is present or not. The A/D calibration is normally set to work only while the receiver is tracking, but it can be set to operate all the time the receiver is on or it can be turned off and held at mid scale.

The A/D calibration circuit operation can be deﬁned through CR 2, bits 3 and 4. Table 3 illustrates the possible conﬁgurations. The A/D Cal function should initially be programmed for mid scale operation to preset it, then programmedfor either trackingmode. This initializes the part for most rapid settling on the appropriate values.

TABLE 3. A/D CALIBRATION

CR 2

BIT 4

0 0 OFF, Reference set at mid scale. 0 1 OFF, Reference set at mid scale. 1 0 A/D_Cal while tracking only. 1 1 A/D_Cal while RX_PE active.

CR 2

BIT 3

A/D CALIBRATION CIRCUIT

CONFIGURATION

RX_I_IN

RX_Q_IN

A/D

A/D_CK

HFA3860

+FS OR -FS

COMPARE

+FS OR -FS

COMPARE

TO CORRELATOR

TO RSSI A/D

A/D_CAL_CK

(APPROX 1KHz)

SELECT

REFN

ANALOG BIASES

REFP

A/D_CAL_POS A/D_CAL_NEG

D/A

FIGURE 7. A/D CAL CIRCUIT

RSSI A/D Interface

The Receive Signal Strength Indication (RSSI) analog signal is input to a 6-bit A/D, indicating 64 discrete levels of received signal strength. This A/D measures a DC voltage, so its input must be DC coupled. Pin 16 (V RSSI A/D converter. V

is common for the I and Q and

REFP

) sets the referencefor the

REFP

RSSI A/Ds. The RSSI signal is used as an input to the Clear Channel Assessment (CCA) algorithm of the HFA3860. The RSSI A/D output is stored in an 6-bit register available via the TEST Bus and the TEST Bus monitor register. CCA is further described on page 15.

The interface speciﬁcations for the RSSI A/D are listed in Table 4 below (V

TABLE 4. RSSI A/D SPECIFICATIONS

PARAMETER MIN TYP MAX

Full Scale Input Voltage - - 1.15 Input Bandwidth (0.5dB) 1MHz - Input Capacitance - 7pF Input Impedance (DC) 1M - -

REFP

= 1.75V).

Test Port

The HFA3860provides the capability to access a number of internal signals and/or data through the Testport, pins TEST 7:0. In addition pin 1 (TEST_CK) is an output that can be used in conjunction with the data coming from the test port outputs.The test port is programmable through conﬁguration register (CR28). Any signal on the test port can also be read from conﬁguration register (CR29) via the serial control port.

ACCUMULATOR

(25-BIT)

5 MSBs

There are 32 modes assigned to the PRISM test port. Some are only applicable to factory test (Table 5).

TEST REG

MODE 1 (7)

A/DCAL

A/D_CAL_ACCUM

(1/4 dB PER LSB)

REG

TEST REG

MODE 25 (8:0)

TABLE 5. TEST MODES

MODE DESCRIPTION TEST_CLK TEST (7:0)

0 Quiet Test Bus 0 00 1 RX Acquisition

Monitor

Initial Detect A/DCal, CRS, ED,

Track, SFD Detect, Signal Field Ready, Length Field Ready, Header CRC Valid

2 TX Field Monitor IQMARK A/DCal,TXPEInternal,

Preamble Start, SFD Start, Signal Field Start, Length Field Start, CRC Start, MPDU Start

3 RSSI Monitor RSSI Pulse CSE Latched, CSE,

RSSI Out (5:0)

4 SQ1 Monitor Pulse after

SQ1 (7:0)

SQ is valid

5 SQ2 Monitor Pulse after

SQ2 (7:0)

SQ is valid

6 Correlator Lo

Rate

7 Freq Test Lo

Rate

8 Phase Test Lo

Rate

9 NCO Test Lo

Rate

Sample CLK Correlator Magnitude

(7:0)

Subsample CLK

Subsample

Frequency Register (18:11)

Phase Register (7:0)

CLK Subsample

NCO Register (15:8)

CLK

TABLE 5. TEST MODES (Continued)

MODE DESCRIPTION TEST_CLK TEST (7:0)

Bit Sync Accum

(0Ah)

Lo Rate 11 Reserved Reserved Factory Test Only 12 A/D Cal Test

Mode 13 Correlator I High

Rate 14 CorrelatorQHigh

Rate 15 Chip Error

Accumulator 16 NCO Test Hi

Rate 17 Freq Test Hi Rate Sample CLK Lag Accum (18:11) 18 Carrier Phase

Error Hi Rate 19 Reserved Sample CLK Factory Test Only 20 Reserved Sample CLK Factory Test Only 21 I_A/D, Q_A/D Sample CLK 0,0,I_A/D (2:0),Q_A/D

22 Reserved Reserved Factory Test Only 23 Reserved Reserved Factory Test Only 24 Reserved Reserved Factory Test Only 25 A/D Cal AccumLoA/D Cal

26 A/D Cal AccumHiA/D Cal

27 Freq Accum Lo Freq Accum

28 Reserved Reserved Factory Test Only 29 SQ2 Monitor Hi Pulse After

30-31 Reserved Reserved Factory Test Only

Sample CLK Bit Sync Accum (7:0)

A/D Cal CLK A/DCal, ED, A/DCal

Disable, ADCal (4:0)

Sample CLK Correlator I (8:1)

Sample CLK Correlator Q (8:1)

0 Chip Error Accum

(14:7)

Sample CLK NCO Accum (19:12)

Sample CLK Carrier Phase Error

(6,6:0)

(2:0)

A/D Cal Accum (7:0)

Accum (8)

A/D Cal Accum (16:9)

Accum (17)

Freq Accum (14:7)

(15)

SQ2 (15:8)

SQ Valid

HFA3860

TABLE 6. POWER DOWN MODES

MODE RX_PE TX_PE RESET AT 44MHz DEVICE STATE

SLEEP Inactive Inactive Active 4mA Both transmit and receive functions disabled. Device in sleep mode. Control

Interface is still active.Register values are maintained. Device will return to its active state within 10µs plus settling time of AC coupling capacitors (about 5ms).

STANDBY Inactive Inactive Inactive 11mA Both transmit and receive operations disabled. Device will resume its

operational state within 1µs of RX_PE or TX_PE going active.

TX Inactive Active Inactive 15mA Receiver operations disabled. Receiver will return in its operational state

within 1µs of RX_PE going active.

RX Active Inactive Inactive 24mA Transmitter operations disabled. Transmitter will return to its operational state

within 2 MCLKs of TX_PE going active.

NO CLOCK ICC Standby Active 300µA All inputs at VCC or GND.

HFA3860

Deﬁnitions

ED. Energy Detect, indicates that the RSSI value exceeds its

programmed threshold. CRS. Carrier Sense, indicates that a signal has been acquired

(PN acquisition).

TXCLK. Transmit clock. Track. Indicates start of tracking and start of SFD time-out. SFD Detect. Variable time after track starts. Signal Field Ready. ~ 8µs after SFD detect. Length Field Ready. ~ 32µs after SFD detect. Header CRC Valid. ~ 48µs after SFD detect. DCLK. Data bit clock. FrqReg. Contents of the NCO frequency register. PhaseReg. phase of signal after carrier loop correction. NCO PhaseAccumReg. Contents of the NCO phase accu-

mulation register. SQ1. Signal Quality measure #1. Contents of the bit sync

accumulator.Eight MSBs of most recent 16-bit stored value. SQ2. Signal Quality measure #2. Signal phase variance

after removal of data, Eight MSBs of most recent 16-bit stored value.

Sample CLK. Receive clock (RX sample clock). Nominally 22MHz.

Subsample CLK. LO rate symbol clock. Nominally 1MHz. BitSyncAccum. Real time monitor of the bit synchronization

accumulator contents, mantissa only.

A/D_Cal_ck. Clock for applying A/D calibration corrections. A/DCal. 5-bit value that dr ives the D/A adjusting the A/D

reference.

Power Down Modes

The power consumption modes of the HFA3860 are controlled by the following control signals.

Receiver Power Enable (RX_PE, pin 33), which disables the receiver when inactive.

Transmitter PowerEnable (TX_PE, pin 2), which disables the transmitter when inactive.

RESET, pin 28), which puts the receiver in a sleep

Reset ( mode. The power down mode where, both RX_PE are used is the lowest possible power consumption mode for the receiver.Exiting this mode requires a maximum of 10µs before the device is back at its operational mode. It also requires that RX_PE be activated brieﬂy to clock in the change of state.

The contents of the Conﬁguration Registers are not effected by any of the power down modes. The external processor does have access and can modify any of the CRs during the

RESET and

power down modes. No reconﬁguration is required when returning to operational modes.

Table 6 describes the power down modes available for the HFA3860 (V other inputs to the part (MCLK, SCLK, etc.) continue to run except as noted.

= 3.3V). The table values assume that all

Transmitter Description

The HFA3860 transmitter is designed as a Direct Sequence Spread Spectrum Phase Shift Keying (DSSS PSK) modulator.It can handle data rates of up to 11 Mbps (refer to AC and DC speciﬁcations). The various modes of the modulator are Differential Binary Phase Shift Keying (DBPSK), Differential Quaternary Phase Shift Keying (DQPSK), Binary M-ary Bi-Orthogonal Keying (BMBOK), and Quaternary M-ary Bi-Orthogonal Keying (QMBOK). These implement data rates of 1, 2, 5.5 and 11 Mbps as shown in Figure 8. The major functional blocks of the transmitter include a network processor interface, DPSK modulator, high rate modulator, a data scrambler and a spreader, as shown on Figure 8. A description of (M-ARY) Bi-Orthogonal Keying can be found in Chapter 5 of: “Telecommunications System Engineering”, by Lindsey and Simon, Prentis Hall publishing.

The preamble and header are always transmitted as DBPSK waveforms while the data packets can be conﬁgured to be either DBPSK, DQPSK, BMBOK, or QMBOK. The preamble is used by the receiver to achieve initial PN synchronization while the header includes the necessary data ﬁelds of the communications protocol to establish the physical layer link. The transmitter generates the synchronization preamble and header and knows when to make the DBPSK to DQPSK or B/QMBOK switchover, as required.

For the PSK modes, the transmitter accepts data from the external source, scrambles it, differentially encodes it as either DBPSK or DQPSK, and mixes it with the BPSK PN spreading. The baseband digital signals are then output to the external IF modulator.

For the MBOK modes, the transmitter inputs the data and forms it into nibbles (4 bits). At 5.5 Mbps, it selects one of 8 spread sequences from a table of sequences with 3 of those bits and then picks the true or inverted version of that sequence with the remaining bit. Thus, there are 16 possible spread sequences to send, but only one is sent. This sequence is then modulated on both the I and Q outputs. The phase of the last bit of the header is used as an absolute phase reference for the data portion of the packet. At 11 Mbps, two nibbles are used, and each one is used as above independently. One of the resulting sequences is modulated on the I Channel and the other on the Q Channel output. with 16 possible sequences on I and another 16 independently on Q, the total possible number of combinations is 256. Of these only one is sent.

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