Intersil Corporation HFA3841 Datasheet

TM

HFA3841

PRELIMINARY

Data Sheet January 2000

Wireless LAN Medium Access Controller

The Intersil HFA3841 Wireless LAN
Medium Access Controller is part of the
PRISM® Enterprise 2.4GHz WLAN
chip set. The HFA3841 directly

interfaces with the Intersil HFA386x
family of Baseband Processors, offering a complete end-to­end chip set solutionforwirelessLANproducts. Protocol and
PHY support are implemented in firmware to allow custom
protocol and different PHY transceivers.

The HFA3841isdesigned to provide maximum performance
with minimum power consumption. External pin layout is
organized to provide optimal PC board layout to all user
interfaces.

Firmware implements the full IEEE 802.11 Wireless LAN
MAC protocol. It supports BSS and IBSS operation under
DCF, and operation under the optional Point Coordination
Function (PCF). Low level protocol functions such as
RTS/CTS generation and acknowledgement, fragmentation
and de-fragmentation, and automatic beacon monitoring are
handed without host intervention. Active scanning is
performed autonomously once initiated by host command.
Host interface command and status handshakes allow
concurrent operations from multi-threaded I/O drivers.
Additional firmware functions specific to access point
applications are also available.

Designing wireless protocol systems using the HFA3841 is
made easier with the availability of evaluation board,
firmware, software device drivers, and complete
documentation.

File Number 4661.2

Features

• IEEE802.11 Standard Data Rates: 1, 2, 5.5 and 11Mbps

• Part of the Intersil PRISM Wireless LAN Chip Set

• Full Implementation of the MAC Protocol Specified in
IEEE Std. 802.11-1999 and the 802.11b Draft Standard

• Host Interface Supports Full 16-Bit Implementation of PC
Card 95, also ISA PnP with Additional Chip

• Host Interface Provides Dual Buffer Access Paths

• External Memory Interface Supports up to 4M bytes RAM

• Internal Encryption Engine Executes IEEE802.11 WEP

• Low PowerOperation;25mAActive ,8mADoze,<1mASleep

• Operation at 2.7V to 3.6V Supply

• 3V to 5V Tolerant Input/Outputs

• 128 Pin LQFP Package Targeted for Type II PC Cards

• IEEE802.11 Wireless LAN MAC Protocol Firmware and
Microsoft® Windows® Software Drivers

Applications

• High Data Rate Wireless LAN

• PC Card Wireless LAN Adapters

• ISA, ISA PnP WLAN Cards

• PCI Wireless LAN Cards (Using Ext. Bridge Chip)

• Wireless LAN Modules

• Wireless LAN Access Points

• Wireless Bridge Products

• Wireless Point-to-Multipoint Systems

Ordering Information

PART

NUMBER

HFA3841CN 0 to 70 128 Ld LQFP Q128.14x20
HFA3841CN96 0 to 70 Tape and Reel

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

Microsoft® and Windows® are registered trademarks of Microsoft Corporation.

TEMP. RANGE

(oC) PACKAGE PKG. NO.

Pinout

Preliminary - HFA3841

HINP A CK-

HWAIT-

_IO5

V

CC

HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7

HIREQ-

_IO3

V

SS

HWE-

HA8
HA9

HIOWR-

HIORD-

HOE-

HCE2-

HD15

_IO3

V

CC

HD14
HD13
HD12
HD11

103
104
105

106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

MA11

MA10

84

85

_IO3

CC

V

83

_IO3

SS

V

82

MA9

81

MA8

80

MA7

79

MA6

78

MA5

77

MA4

76

_IO3

_IO3

CC

SS

HD8

V

HD2

HD1

HD0

HREG-

99

102

1

2

98

100

101

345678910111213141516171819202122232425262728293031

HD9

V

95

96

97

INDEX

HD10

94

PL7

93

MA18

MA17

92

91

MA16

90

MA15

MA14

88

89

MA13

87

MA12

86

MA3

75

MA2

74

MA1

73

MA0

72

MWEL-

71

32

_IO3

_IO3

RAMCS-

NVCS-

68

69

SS

V

V

67

MOE-

70

3334353637

66

CC

65

64
63

62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40

39
38

PJ4

PK4
PK3
TRST­MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7

_CORE3

V

CC

V

_IO3

SS

MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
PL4
V

_IO3

SS

XTALO
XTALI
VCC_CORE3

HD7

HCE1-

HD6

HD5

HD4

HD3

PJ6

Simplified Block Diagram

PRISM RADIO

BASEBAND

PROCESSOR

TXD/RXD

CTRL/STATUS

SERIAL CONTROL

PRISM RADIO

RF SECTION

RADIO AND SYNTH

SERIAL CONTROL

PJ5

PJ7

PL5

PL6

TCLKIN

HFA3841

PHY

INTERFACE

(MDI)

SERIAL

CONTROL

(MMI)

44MHz CLOCK

SOURCE

_CORE3

_CORE3

SS

CC

V

V

PL0

TXD

RESET

TXC

PK5

RXD

RXC

MICRO-

PROGRAMMED

MAC ENGINE

MEMORY

CONTROLLER

ADDRESS

PK7

PK6

WEP

ENGINE

DAT A

_CORE3

_CORE3

SS

CC

V

V

EXTERNAL
SRAM AND

FLASH

SELECT

MEMORY

PL2

PL1

PL3

PC CARD

HOST

INTERFACE

ON-CHIP

MEMORY

PJ3

PJ1

PJ0

PJ2

PK2

DAT A
ADDRESS
CONTROL

PK1

PK0

HSTSCHG-

HOST

COMPUTER

_CORE3

CLKOUT

SS

V

2

Preliminary - HFA3841

HFA3841 Pin Descriptions

Host Interface Pins

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

HA0-9 106-113, 117, 118 5V tol, CMOS, Input, 50K Pull Down PC Card address input, bits 0 to 9
HCE1- 1 5V tol, CMOS, Input, 50K Pull Up PC Card card select, low byte
HCE2- 122 5V tol, CMOS, Input, 50K Pull Up PC Card card select, high byte
HD0-15 101-99, 6-2,

96-94, 128-125,

123
HINPACK- 103 CMOS Output, 2mA PC Card I/O decode confirmation
HIORD- 120 5V tol, CMOS, Input, 50K Pull Up PC Card I/O space read
HIOWR- 119 5V tol, CMOS, Input, 50K Pull Up PC Card I/O space write
HRDY/HIREQ- 114 CMOS Output, 4mA PC Card interrupt request (I/O mode) Card ready

HOE- 121 5V tol, CMOS, Input, 50K Pull Up PC Card memory attribute space output enable
HREG- 102 5V tol, CMOS, Input, 50K Pull Up PC Card attribute space select
HRESET 16 5Vtol,CMOS,ST Input, 50K Pull Up Hardware Re-

HSTSCHG- 36 CMOS Output, 4mA PC Card status change
HWAIT- 104 CMOS Output, 4mA PC Card not ready (force host wait state)
HWE- 116 5V tol, CMOS Input, 50K Pull Up PC Card memory attribute space write enable

5V tol, BiDir, 2mA, 50K Pull Down PC Card data bus, bit 0 to 15

(memory mode)

set

Memory Interface Pins

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

MA0 MWEH- 72 CMOS TS Output, 2mA MBUSaddress bit0 (byte)for x8memory Highbyte

write enable for x16 memory
MA1-18 73-81, 84-92 CMOS TS Output, 2mA MBUS address bits 1 to 18
PL4 43 CMOS BiDir, 2mA MBUS address bit 19
PL5 12 CMOS BiDir, 2mA, 50K Pull Up MBUS address bit 20
PL6 11 CMOS BiDir, 2mA MBUS address bit 21
MOE- 70 CMOS TS Output, 2mA Memory output enable
MWEL- 71 CMOS TS Output, 2mA Low (or only) byte memory write enable
RAMCS- 69 CMOS TS Output, 2mA RAM select
NVCS- 68 CMOS TS Output, 2mA NV memory select
MD0-7 61-54 5V tol, CMOS, BiDir, 2mA, 100K Pull Up MBUS low data byte, bits 0 to 7
MD8-15 51-44 5V tol, CMOS, BiDir, 2mA 50K Pull Down MBUS high data byte, bits 8 to 15

3

Preliminary - HFA3841

Radio Interface and General Purpose Port Pins

DESCRIPTION OF FUNCTION

PIN NAME PIN NUMBER PIN I/O TYPE

TXD 17 CMOS Output, 2mA, 50K Pull Down Transmit data out
TXC 18 5V tol, CMOS, BiDir 2mA, ST Transmit clock in/out
RXD 19 CMOS Input Receive data in
RXC 20 CMOS Input, ST Receive clock in
PJ0 31 CMOS BiDir, 2mA, ST, 50K Pull Down MMI serial clock in/out
PJ1 30 CMOS BiDir, 2mA, 50K Pull Down MMI serial data in/out
PJ2 32 CMOS BiDir, 2mA, 50K Pull Down MMI serial data read/write control, or data output
PJ3 29 CMOS BiDir, 2mA MMI device enable
PJ4 65 CMOS BiDir, 2mA
PJ5 8 CMOS BiDir, 2mA, 50K Pull Up
PJ6 7 CMOS BiDir, 2mA
PJ7 9 CMOS BiDir, 2mA, 50K Pull Up
PK0 35 CMOS BiDir, 2mA, ST, 50K Pull Down
PK1 34 CMOS BiDir, 2mA, 50K Pull Down
PK2 33 CMOS BiDir, 2mA, 50K Pull Down
PK3 63 CMOS BiDir, 2mA
PK4 64 CMOS BiDir, 2mA
PK5 21 CMOS BiDir, 2mA MDREADY - PHY or MAC data available (in)
PK6 22 CMOS BiDir, 2mA Medium busy (CCA from PHY)
PK7 23 CMOS BiDir, 2mA
PL0 15 CMOS BiDir, 2mA Transmitter enable
PL1 27 CMOS BiDir, 2mA Receiver enable (or PHY sleep control)
PL2 26 CMOS BiDir, 2mA
PL3 28 CMOS BiDir, 2mA
PL4 43 CMOS BiDir, 2mA MBUS address bit 19
PL5 12 CMOS BiDir, 2mA, 50K Pull Up MBUS address bit

20
PL6 11 CMOS BiDir, 2mA MBUS address bit 21 or PHY control I/O
PL7 93 CMOS BiDir, 2mA Transmitter ready

(IF OTHER THAN IO PORT)

Clocks

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

XTALI 40 CMOS Input, ST Crystal or external clock input (at >= 2X desired

MCLK frequency)
XTALO 41 CMOS Output, 2mA Crystal output
CLKOUT 38 CMOS, TS Output, 2mA Clock output (selectable as OSC or MCLK)
TCLKIN 10 CMOS Input, ST, 50K Pull Down Timebase Reference Clock Input

4

Preliminary - HFA3841

Power

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

VCC_CORE3 14, 25, 39, 53 3.3V Core Supply
VCC_IO3 66, 83, 98. 124 3.3V I/O Supply
VCC_IO5 105 5V Tolerance Supply
VSS_CORE3 13, 24, 37 Core V
VSS_IO3 42, 52, 67, 82, 97, 115 I/O V
TRST- 62 CMOS Input Reserved - Must be tied low through 1K

ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with “-” are active low.
NOTE: Output pins typically drive to positive voltage rail less 0.1V.Hence with a supply of 2.7V the output will just meet 5V TTL signal levels at

rated loads.

Port Pin Uses for PRISM Application

PIN NAME PRISM I USE PRISM II™ USE

20 RXC RXC - Receive clock RXC - Receive clock
19 RXD RXD - Receive data RXD - Receive data
18 TXC TXC - Transmit clock TXC - Transmit clock
17 TXD TXD - Transmit data TXD - Transmit data
31 PJ0 SCLK - Clock for the SD serial bus. SCLK - Clock for the SD serial bus.
30 PJ1 SD - Serial bi-directional data bus SD - Serial bi-directional data bus
32 PJ2 R/W - An input to the HFA3860A used to change

the direction of the SD bus when reading or writing
data on the SD bus.

29 PJ3 CS - A Chip select for the device to activate the se-

rial control port. (active low)
65 PJ4 Not Used PE1 - Power Enable 1
8 PJ5 SYNTH_LE - Latches a frame of 22 bits after it has

been shifted by the SCLK into the synthesizer reg-

isters.
7 PJ6 LED - Activity indicator LED - Activity indicator
9 PJ7 Not Used RADIO_PE - RF power enable
35 PK0 Not Used LE_RF - Load enable for HFA3983 RF chip
34 PK1 Not Used SYNTHCLK - Serial clock to front end chips
33 PK2 Not Used SYNTHDATA - Serial data to front end chips
63 PK3 TX_PE_RF - Power Enable PA_PE - Transmit PA power enable
64 PK4 RX_PE_RF - Power Enable PE2 - Power Enable 2
21 PK5 MD_RDY - Header data and data packet are ready

to be transferred from Baseband on RXD
22 PK6 CCA - Signal that the channel is clear to transmit. CCA - Signal that the channel is clear to transmit.
23 PK7 RADIO_PE - Master power control for the RF

section
15 PL0 TX_PEand PA_PE - Transmit Enable to Baseband TX_PE - Transmit Enable to Baseband
27 PL1 RX_PE - Receive Enable to Baseband RX_PE - Receive Enable to Baseband
26 PL2 RESET - Reset to Baseband RESET_BB - Reset Baseband
28 PL3 Not Used T/R-SW_BAR - Transient/Receive Control (Inverted)
43 PL4 MA19 (if required) MA19 (if required)
12 PL5 MA20 (if required) MA20 (if required)
11 PL6 MA21 (if required) Reserved
93 PL7 TX_RDY- Baseband ready to receive data on TXD

(not used by firmware)

SS

SS

Not Used

CS_BAR - Chip select for HFA3861 baseband
(active low)

LE_IF - Load enable for HFA3783 Quad IF

MDREADY - Header data and data packet are
ready to be transferred from Baseband on RXD

CAL_EN - Calibration mode enable

T/R_SW - Transmit/Receive Control

5

Preliminary - HFA3841

Special Hardware Functions for Port Pins

PJ0 SCK MMI serial clock in or out
PJ1 SDO/SDIO MMI serial data out or I/O

MOSI SPI Master Out/Slave In Also for MicroWire

PJ2 SDI/MISO MMI serial data in Or SPI Master In/Slave Out

SDDIR MMI (SDIO) data direction Low while SDIO is driven as an output

PJ3 SDE0 MMI serial device enable 0 Generally selects PHY controller

PCS- SPI/MMI transfer qualifier Asserted by hardware during transfer
PHYCS- PHY chip select (3-3.5MB) For memory-mapped PHY controllers

PJ4 SDE1 MMI serial device enable 1 For serial EPROM, synthesizer, etc.

SDDQ MMI data delivery qualifier Low for data on SDIO, high for address

SS- SPI slave select In slave mode SCK is serial clock input
PJ5 MREQ- MBUS request
PJ6 MGNT- MBUS grant

LED2 LED 2 driver (Directly from I/O port)
PJ7 LED1 LED 1 driver (Directly from I/O port)
PK0 GPCK GP serial port clock in or out

UHSIn Async handshake in Indicates external async Rx ready
PK1 GPDO GP serial port data output

UTXD Async transmit data
PK2 GPDI GP serial port data input

URXD Async receive data
PK3 GPDS0 GP device select 0

UHSOut Async handshake out Indicates GP port async Rx ready
PK4 GPDS1 GP device select 1
PK5 PDA PHY (or MAC) data available Qualifies RXD input to MAC controller

UWDET Unique word detected Output from MAC controller
PK6 MBUSY Medium busy CCA status (PHY-dependent source)

RATE0 Data Rate select 0
PK7 EDET Energy (or modulation) detect

RATE1 Data Rate select 1
PL0 TXE Transmitter enable
PL1 RXE Receiver enable Can drive “awake” LED

PHYSLP PHY sleep (Directly from I/O port)
PL2 PHYRES PHY reset (Directly from I/O port)
PL3 SLOT Slot time reference (in or out)

ANTSEL Antenna select (Directly from I/O port)
PL4 MA19 MBUS address bit 19 For 1M byte SRAM

LED0 LED 0 driver (Directly from I/O port)
PL5 MA20 MBUS address bit 20 For 2M byte SRAM
PL6 MA21 MBUS address bit 21 For 4M byte SRAM
PL7 TXR Transmitter ready

6

Preliminary - HFA3841

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V

Input, Output or I/O Voltage. . . . . . . . . . . .GND -0.5V to VCC+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2

Operating Conditions

Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.70V to +3.60V

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .100oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(Lead Tips Only)

DC Electrical Specifications Maximum test temperature = 100

o

C, VCC = 3.0V to 3.3V ±10%, TA = -40oC to 85oC

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Power Supply Current I
Standby Power Supply Current I

CCOP
CCSB

Input Leakage Current I
Output Leakage Current I
Logical One Input Voltage V
Logical Zero Input Voltage V
Logical One Output Voltage V
Logical Zero Output Voltage V
Input Capacitance C

OH
OL

VCC = 3.6V, CLK Frequency 44MHz - 35 45 mA
VCC = Max, Outputs not Loaded - 0.5 1 mA
VCC = Max, Input = 0V or V

I

VCC = Max, Input = 0V or V

O

VCC = Max, Min 0.7V

IH

VCC = Min, Max - - VCC/3 V

IL

CC
CC

-10 1 10 mA

-10 1 10 mA

CC

IOH = -1mA, VCC = Min VCC-0.2 - - V
IOL = 2mA, VCC = Min - 0.2 0.2 V
CLK Frequency 1MHz. All measurements

IN

- 5 10 pF

referenced to GND. TA = 25oC

Output Capacitance C

OUT

CLK Frequency 1MHz. All measurements

- 5 10 pF

referenced to GND. TA = 25oC

NOTE: All values in this table have not been measured and are only estimates of the performance at this time.

AC Electrical Specifications

PARAMETER SYMBOL MIN TYP MAX UNITS

CLOCK SIGNAL TIMING

OSC Clock Period (Typ. 44MHz) t
High Period t
Low Period t
Delay from OSC Edge to MCLK Edge t

EXTERNAL MEMORY INTERFACE

Rising Edge MCLK to EMA[15:0], EMCSxN, EMOEN, EMWRN t
Width EMOEN t
EMD[15:0] Read Data Setup t
EMD[15:0] Read Data Hold t
Minimum Width between Read and Write t
Width EMWRN t
EMWRN Rising to EMCSxN Rising t
EMD[15:0] Write Data Hold Time to Rising Edge EMWRN t

CYC

H1
L1
D1

D1
D2
S1
H1
D3
D4
D5
D6

22 22.7 200
15 11.36 ­15 11.36 -

-10-

0 - 10 ns

2*t

-10 - 9*t

MCLK

10 - - ns

--0ns

t

- 10 t

MCLK

2*t
1*t
1*t

-10 - 9*t

MCLK

- 10 1*t

MCLK

- 10 1*t

MCLK

--V

+10 ns

MCLK

t

MCLK

MCLK
MCLK

MCLK

1*t
1*t

MCLK
MCLK
MCLK

+ 10 ns

+10 ns
+10 ns
+10 ns

7

Preliminary - HFA3841

AC Electrical Specifications (Continued)

PARAMETER SYMBOL MIN TYP MAX UNITS

SYNTHESIZER

SPCLK Period t
SPCLK Width Hi t
SPCLK Width Lo t
SYNCLE to Rising Edge SPCLK t
SPDATA Hold Time from Falling Edge of SPCLK t
SPCLK Falling Edge to SYNLE Inactive t

SERIAL PORT - HFA3824A/HFA3860B

SPCLK Clock Period t
High Period t
Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD, SPDATA Outputs t
Setup Time of SPDATA Read to SPCLK Falling Edge t
Hold Time of SPDATA Read from SPCLK Falling Edge t
Hold Time of SPDATA Write from SPCLK Falling Edge t

SYSTEM INTERFACE - PC CARD IO READ 16

Data Delay After SIORDN t
Data Hold Following SIORDN t
SIORDN Width Time t
Address Setup Before SIORDN t
SCE(1,2)N Setup Before SIORDN t
SCE(1,2)N Hold After SIORDN t
SREGN Setup Before SIORDN t
SREGN Hold Following SIORDN t
SINPACKN Delay Falling from SIORDN t
SINPACKN Delay Rising from SIORDN d
SIOIS16N Delay Falling from Address t
SIOIS16N Delay Rising from Address t
SWAITN t
Data Delay from SWAITN Rising t
SWAITN Width Time t

SYSTEM INTERFACE - PC CARD IO WRITE 16

Data Setup Before SIOWRN t
Data Hold Following SIOWRN t
SIOWRN Width Time t
Address Setup Before SIOWRN t
Address Hold Following SIOWRN t
SCE(1,2)N Setup Before SIOWRN t
SCE(1,2)N Hold Following SIOWRN t
SREGN Setup Before SIOWRN t
SREGN Hold Following SIOWRN t

DFINPACK

CYC

H1
L1
D1
D2
D3

CYC

, t

H1

L1

CD
DRS
DRH

DWH

DIORD
HIORD

WIORD

SUA

SUCE

HCE

SUREG

HREG

DRINPACK

DFIOIS16
DRIOIS16

DFWT

DRWT

WWT

SUIOWR

HIOWR
WIOWR

SUA

HA

SUCE

HCE

SUREG

HREG

90 - 4,000 ns

t

/2 - 10 - t

CYC

t

/2 - 10 - t

CYC

/2 + 10 ns

CYC

/2 + 10 ns

CYC

35 - - ns

0--ns

35 - - ns

90ns - 4µs

t

/2 -10 - t

CYC

CYC

/2 + 10

-10-ns

15 - - ns

0-­0--

- - 100 ns

0--ns

165 - - ns

70 - - ns

5--ns

20 - - ns

5--ns
0--ns
0 - 45 ns

- - 45 ns

- - 35 ns

- - 35 ns

- - 35 ns

--0ns

- - 12,000 ns

60 - - ns
30 - - ns

165 - - ns

70 - - ns
20 - - ns

5--ns

20 - - ns

5--ns
0--ns

8

Preliminary - HFA3841

AC Electrical Specifications (Continued)

PARAMETER SYMBOL MIN TYP MAX UNITS

SIOIS16N Delay Falling from Address t
SIOIS16N Delay Rising from Address t
SWAITN Delay Falling from IOWRN t
SWAITN Width Time t
SIOWRN High from SWAITN High t

DFIOIS16
DRIOIS16

DFWT

WWT

DRIOWR

RADIO TX DATA - TX PATH

TXC Rising to TXD t
TXC Period t
TXC Width Hi t
TXC Width Lo t
MCLK Period t
TXC Rising to TX_PE2 Deassert (See Note 9) t
TX_RDY Assert Before TXC Rising t
TX_RDY Hold After TXC Rising (See Note 2) t

DTXD

TXC

CHM

CLM

tMCK

DTX_PE2

TX_RDY

TX_RDYH

RADIO RX DATA - RX PATH

RX_RDY Setup Time to RXC Positive Edge (See Note 3) t
RX_RDY Hold Time from RXC Positive Edge (See Note 4) t
RX_PE2 Delay from RX_RDY deAssert (See Note 8) t
RX_PE2 Low Pulse Width (See Note 7) t
RXD Setup Time to RXC Positive Edge (See Note 5) t
RXD Hold Time from RXC Positive Edge (See Note 5) t
RXC Period (See Note 9) t
MCLK Period t
RXC Width Hi t
RXC Width Lo t

SURX_RDY

HRX_RDY

DRX_PE2

WRX_PE2

SURXD

HRXD

RXC

MCLK

RCHM

RCLM

NOTES:

2. TX_RDY is and'd with TXC_ONE_SHOT to shift data in shift register. However, once the last data bit is put on TXD output pin no further shifting
of bits is required. In addition, TX_RDY remains asserted until TX_PE2 is de-asserted which occurs several MAC MCLK's after the last data bit
is shifted into the BBP TX_PORT. Therefore, 0ns hold time is required for this signal.
TX_RDY is used by the BBP to signal that the PLCP header and preamble have been generated and the MAC must provide the MPDU data.
TX_RDY will remain asserted until TX_PE2 is deasserted by the MAC.
TX_PE2 is async to the TX_PORT.

3. MD_RDY is and'd with RXC_ONE_SHOT (RXDAV) to shift data in shift register. RX_RDY is not required to be valid until 1 MCLK after RXC is
sampled high. Therefore, a negative setup time could be used. Since this is an unlikely scenario, we will leave it at a nominal 10ns setup time.

4. MD_RDY isand'd with RXC_ONE_SHOT (RXDAV) to shift datain shiftregister. Therefore, for the last data bit,the MD_RDYmust be held active
until RXC_ONE_SHOT is sampled high by MAC's MCLK. However, it is assumed that BBP will be used in a mode that keeps RX_RDY
(MD_RDY) and RXC running until RX_PE2 is de-asserted. The MAC will stop processing data after the number of bits retrieved from the PLCP
header length field are received. THEREFORE, the RX_RDY hold time with respect to RXC does not matter. However, should the RX_RDY
signal be cleared when the last RXD bit is received the hold time w/r RXC must be honored.

5. RXC positive edge clocks a flop which stores the RXD for internal usage.

6. RXC period (and Hi/Lo times) must belong enough for flops clocked by MAC MCLK to see 1 RXC high and 1 RXC low. Since RXCcan be async
to MAC MCLK it is assumed that 3 MCLK periods will suffice.

7. RX_PE inactive width at BBP is 3 BBP MCLK's. Since BBP MCLK and MAC MCLK can be async minimum should be 4 MAC MCLK's.

8. Not yet verified, but seems reasonable. When RX_RDY drops before expected number of RXD bits is received, then Tx/Rx FSM in mpctl.v
signals timers which clear rx_pe2_int. More of a functional spec than a timing spec.

9. Need to sample 1 RXC high and 1 RXC low with MAC MCLK.

- - 35 ns

- - 35 ns

- - 35 ns

- - 12,000 ns

0--ns

- - 10 ns

4* t

TMCK

--ns
31 - - ns
31 - - ns

22.7 - - ns

- TBD TBD ns

10 - - ns

0--

10 - - ns
45 - - ns

- 3 * t

- 4 * t

MCLK
MCLK

-ns

-ns

10 - - ns

0--ns

- 3 * t

MCLK

-ns

22.7 - - ns
31 - - ns
31 - - ns

9