Intersil Corporation HFA3824A Datasheet

HFA3824A

Data Sheet August 1998 File Number

Direct Sequence Spread Spectrum
Baseband Processor

™

The Intersil HFA3824A Direct
Sequence (DSSS) baseband
processor is part of the PRISM™

2.4GHz radio chipset, and contains all
the functions necessary for a full or

half duplex packet baseband transceiver.
The HFA3824A has on-board ADC’s for analog I and Q

inputs, for which the HFA3724/6 IF QMODEM is
recommended. Differential phase shift keying modulation
schemes DBPSKand DQPSK, with optional data scrambling
capability, are combined with a programmablePN sequence
of up to 16 bits. Built-in flexibility allows the HFA3824A to be
configured through a general purpose control bus, fora wide
range of applications. A Receive Signal Strength Indicator
(RSSI) monitoring function with on-board 6-bit 2 MSPS ADC
provides Clear Channel Assessment (CCA) to avoid data
collisions and optimize network throughput. The HFA3824A
is housed in a thin plastic quad flat package (TQFP) suitable
for PCMCIA board applications.

Ordering Information

TEMP.

PART NO.

HFA3824AIV -40 to 85 48 Ld TQFP Q48.7x7
HFA3824AIV96 -40 to 85 Tape and Reel

RANGE (oC) PKG. TYPE PKG. NO.

4459.2

Features

• Complete DSSS Baseband Processor

• High Data Rate. . . . . . . . . . . . . . . . . . . . . . .up to 4 MBPS

• Processing Gain. . . . . . . . . . . . . . . . . . . . . . . . up to 12dB

• Programmable PN Code . . . . . . . . . . . . . . . .up to 16 Bits

• Ultra Small Package. . . . . . . . . . . . . . . . . . . . 7 x 7 x 1mm

• Single Supply Operation (44MHz Max) . . . . . 2.7V to 5.5V

• Modulation Method. . . . . . . . . . . . . . . .DBPSK or DQPSK

• Supports Full or Half Duplex Operations

• On-Chip A/D Converters for I/Q Data (3-Bit, 44 MSPS)
and RSSI (6-Bit, 2 MSPS)

• Backward Compatible with HSP3824

• Programmable Rotation I, Q Sense

Applications

• Systems Targeting IEEE802.11 Standard

• DSSS PCMCIA Wireless Transceiver

• Spread Spectrum WLAN RF Modems

• TDMA Packet Protocol Radios

• Part 15 Compliant Radio Links

• Portable Bar Code Scanners/POS Terminal

• Portable PDA/Notebook Computer

• Wireless Digital Audio

• Wireless Digital Video

• PCN/Wireless PBX

Pinout

TEST_CK

TX_PE

TXD

TXCLK

TX_RDY

GND

V

DD

W

R/

CS

V

DDA

GND

I

IN

OUT

I

Q

1
2

3
4
5
6

7
8
9
10
11

12

13 14 15 16

IN

Q

RSSI

HFA3824A (TQFP)

OUT

TEST7

TEST6

TEST5

VDDGND

TEST4

DDA

REFN

V

GND

V

GND

REFP

V

2-99

Simplified Block Diagram

TEST3

TEST2

TEST1

TEST0

373839404142434445464748

36
35
34
33
32
31
30
29
28
27
26
25

2423222120191817

DD

DDA

V

AS

V

GND

SCLK

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

RXCLK
RXD
MD_RDY
RX_PE
CCA
GND
MCLK
V

DD

RESET
ANTSEL
A/D_CAL
SD

http://www.intersil.com or 407-727-9207

RSSI

I

OUT

Q

OUT

I

IN

Q

IN

3-BIT

A/D

3-BIT

A/D

6-BIT

A/D

DPSK

DEMOD.

PRO-

CCA

SPREADER DE-SPREADER

CESSOR

INTER-

FACE

DPSK

MOD.

| Copyright © Intersil Corporation 1999

DATA TO NETWORK

CTRL

PROCESSOR

HFA3824A

Table of Contents

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99

Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99

Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99

Typical Application Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102

External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-105

Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-105

TX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108

RX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-109

I/Q ADC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-109

ADC Calibration Circuit and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-110

RSSI ADC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-110

Test Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-110

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111

External AGC Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111

Power Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112

Transmitter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112

Header/Packet Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113

PN Generator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-114

Scrambler and Data Encoder Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115

Modulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116

Clear Channel Assessment (CCA) and Energy Detect (ED) Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116

Receiver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116

Acquisition Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117

Two Antenna Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117

One Antenna Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117

Acquisition Signal Quality Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117

Procedure to Set Acq. Signal Quality Parameters (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-118

PN Correlator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-119

Data Demodulation and Tracking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-119

Procedure to Set Signal Quality Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-119

Data Decoder and Descrambler Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-120

Demodulator Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-120

Overall Eb/N0 Versus BER Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-120

Clock Offset Tracking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121

Carrier Offset Frequency Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121

I/Q Amplitude Imbalance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121

A Default Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-124

Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-137

PAGE

2-100

Typical Application Diagram

HFA3824A

HF A3424 (NOTE)

(FILE# 4131)

HF A3624

UP/DOWN

CONVERTER

(FILE# 4066)

RFPA

HF A3925

(FILE# 4132)

TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3824A

NOTE: Required for systems targeting 802.11 specifications.

VCO

VCO

DUAL SYNTHESIZER

HFA3524

(FILE# 4062)

HFA3724/6

(FILE# 4067)

÷2

QUAD IF MODULATOR

0o/90

TUNE/SELECT

I

M

o

U
X

Q

HF A3824, HFA3824A

(FILE# 4308, 4459)

RXI

RXQ

RSSI

M
U
X

A/D

DE-

SPREAD

A/D

CCA

A/D

TXI

SPREAD

TXQ

DSSS BASEBAND PROCESSOR

PRISM™ CHIP SET FILE #4063

DPSK

DEMOD

802.11

MAC-PHY

INTERFACE

DPSK

MOD.

DATA TO MACCTRL

For additional information on the PRISM™ chip set, call
[phone] to access Intersil’ AnswerFAXsystem. When
prompted, key in the four-digit document number (File #) of
the data sheets you wish to receive.

The four-digit file numbers are shown in Typical Application
Diagram, and correspond to the appropriate circuit.

2-101

HFA3824A

Pin Description

NAME PIN TYPE I/O DESCRIPTION

V

DDA

(Analog)

VDD (Digital) 7, 21, 29, 42 Power DC power supply 2.7V - 5.5V

GND (Analog) 11, 15, 19 Ground DC power supply 2.7V - 5.5V, ground (Not Hardwire Together On Chip).

GND (Digital) 6, 22, 31, 41 Ground DC power supply 2.7V - 5.5V, ground.

V

REFN

V

REFP

I

IN

Q

IN

RSSI 14 I Receive Signal Strength Indicator Analog input.

A/D_CAL 26 O This signal is used internally as part of the I and Q ADC calibration circuit. When the ADC

TX_PE 2 I When active, thetransmitter is configured to be operational, otherwise thetransmitter is in

TXD 3 I TXD is an input, used to transfer serial Data or Preamble/Header information bits from the

TXCLK 4 O TXCLK is a clock output used to receive the data on the TXD from the MAC or network

TX_RDY 5 O When the HFA3824A is configured to generate the preamble and Header information in-

CCA 32 O Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to

RXD 35 O RXD is an output to the external network processor transferring demodulated Header in-

RXCLK 36 O RXCLK is the clock output bit clock. This clock is used to transfer Header information and

10, 18, 20 Power DC power supply 2.7V - 5.5V (Not Hardwire Together On Chip).

17 I “Negative” voltage reference for ADC’s (I and Q) [Relative to V
16 I “Positive” voltage reference for ADC’s (I, Q and RSSI)
12 I Analog input to the internal 3-bit A/D of the In-phase received data.
13 I Analog input to the internal 3-bit A/D of the Quadrature received data.

calibration circuit is active, thevoltage referencesof the ADCs are adjustedto maintainthe
outputs of theADCs in their optimum range. A logic 1 on this pinindicates that oneor both
of the ADC outputs are at their full scale value. This signal can be integrated externally as
a control voltage for an external AGC.

standby mode. TX_PE is an input from the external MediaAccess Controller (MAC)or net­work processor to the HFA3824A. The rising edge of TX_PE will start theinternal transmit
state machine and the falling edge will inhibit the state machine. TX_PE envelopes the
transmit data.

MAC or network processor to the HFA3824A. The data is received serially with the LSB
first. The data is clocked in the HFA3824A at the falling edge of TXCLK.

processor to the HFA3824A, synchronously. Transmitdata on theTXD bus isclocked into
the HFA3824A on the falling edge.The clockingedgeis also programmable to beon either
phase of the clock. The rate of the clock will be depending upon the modulation type and
data rate that is programmed in the signalling field of the header.

ternally, TX_RDY is an output to the external network processor indicating that Preamble
and Header information has been generated and that the HFA3824A is ready to receive
the data packet from the network processorover the TXDserial bus. The TX_RDY returns
to the inactivestate when the TX_PE goes inactive indicating the end of the data transmis­sion. TX_RDY is an active high signal. This signal is meaningful only when the HFA3824A
generates its own preamble.

transmit. The CCA algorithm is user programmable and makes its decision as a function
of RSSI, Energy detect (ED), and Carrier Sense (CRS). The CCA algorithm and its pro­grammable features are described in the data sheet.
Logic 0 = Channel is clear to transmit.
Logic 1 = Channel is NOT clear to transmit (busy).

This polarity is programmable and can be inverted.

formation and data in a serial format. The data is sent serially with the LSB first. The data
is frame aligned with MD_RDY.

data through the RXD serial bus to the network processor. This clock reflects the bit rate
in use. RXCLK will be held to a logic “0” state during the acquisition process. RXCLK be­comes active when the HFA3824A enters in the data mode. This occurs once bit sync is
declared and a valid signal qualityestimate is made, when comparingthe programmedsig­nal quality thresholds.

REFP

]

2-102

HFA3824A

Pin Description

NAME PIN TYPE I/O DESCRIPTION

MD_RDY 34 O MD_RDY isan output signal to the network processor, indicating a data packet is readyto

RX_PE 33 I When active, receiver is configured to be operational, otherwise receiver is in standby

ANTSEL 27 O The antennaselectsignal changes state as thereceiverswitches from antenna to antenna

SD 25 I/O SD is a serial bidirectional data bus which is used to transfer address and data to/from the

SCLK 24 I SCLKis the clock for the SDserial bus.The dataonSD is clocked at the rising edge.SCLK

AS 23 I AS is an address strobe used to envelope the Address or the data on SD.

R/W8 IR/W is aninput to the HFA3824Aused to change the directionof the SD bus whenreading

CS 9 I CS is aChip select for the device to activate the serial control port. The CS doesn’t impact

TEST 0-7 37,38, 39, 40,

TEST_CK 1 O This is the clock that is used in conjunction with the data that is being output from the test

RESET 28 I Master reset for device. When active TX and RX functions are disabled. If RESET is kept

MCLK 30 I Master Clock for device. The maximum frequency of this clock is 44MHz. This is used in-

I

OUT

Q

OUT

NOTE: Total of 48 pins; ALL pins are used.

(Continued)

betransferred to the processor. MD_RDY isan activehigh signaland itenvelopesthe data
transfer over the RXD serial bus. MD_RDY returns to its inactive state when there is no
morereceiver data, when the programmable data lengthcounter reachesits valueor when
the link has beeninterrupted. MD_RDY remainsinactive during preamble synchronization.

mode. This is an active high input signal. In standby, all A/D converters are disabled.

during the acquisition process in the antenna diversity mode.

internal registers. The bit ordering of an 8-bit word is MSB first. The first 8 bitsduring trans­fers indicate the register address immediately followed by 8 more bits representing the
data that needs to be written or read at that register. This pin goes to high impedance
(three-state) when CS is high or R/W is low.

is an input clock andit is asynchronous to the internal masterclock (MCLK)The maximum
rate of this clock is 11MHz or one half the master clock frequency, whichever is lower.

Logic 1 = envelopes the address bits.
Logic 0 = envelopes the data bits.

or writing data on the SD bus. R/W must beset up prior to the rising edge of SCLK. A high
level indicates read while a low level is a write.

any of the other interface ports and signals, i.e., the TX or RX ports and interface signals.
This is an active low signal. When inactive SD, SCLK, AS and R/W become “don’t care”
signals.

I/O This is a data port that can be programmed to bring out internal signals or data for moni-

43, 44, 45, 46

48 O TX Spread baseband I digital output data. Data is output at the programmed chip rate.
47 O TX Spread baseband Q digital output data. Data is output at the programmed chip rate.

toring. These bits are primarily reserved by the manufacturer for testing. A further descrip­tion of the test port is given at the appropriate section of this data sheet. The direction of
these pins are not established until programming of test registers is complete.

bus (TEST 0-7).

low the HFA3824A goes into the power standby mode. RESET does not alter any of the
configuration register values nor it presets any of the registers into default values. Device
requires programming upon power-up.

ternally to generate all other internal necessary clocks and isdivided by 1,2, 4, or 8 for the
transceiver clocks.

2-103

HFA3824A

REF

2V

1.75V
(MAX)

0.25V
(MIN)

I

(12)

IN

Q

(13)

IN

V

REFP

V

REFN

AGC (26)

RSSI (14)

(16)

(17)

VR3+

3-BIT

A/D

3-BIT

A/D

VR3-

6-BIT

A/D

RSSI

REF

V

(ANALOG)

DD

(10, 18, 20)

3

3

A/D REFERENCE

LEVEL ADJUST.

ANALOG

AND

GND (ANALOG)

(11, 15, 19)

PN CODE

11 TO 16-BIT

DE-SPREADER/ACQUISITION

MF CORRELATOR

11 TO 16-BIT

MF CORRELATOR

11 TO 16-BIT

PHASE

ROTATE

PHASE
ERROR

NCO

(DIGITAL)

V

DD

(7, 21, 29, 42)

PSK

DEMOD

LEAD

/LAG

FILTER

8

8

8

DIFF

DECODER

d(t)

-1

Z

d(t-1)

GND (DIGITAL)

(6, 22, 31, 41)

MAG. /

PHASE

AND

TIMING

DISTRIB.

BIT

SYNC

CLEAR CHANNEL

ASSESSMENT/

SIGNAL QUALITY

SIGNAL

QUALITY

AND
RSSI

(36) RXCLK

SYMBOL CLOCK

SIGNAL QUALITY

(32) CCA

THRESHOLD

SQ AND RSSI

ANTSEL (27)

I

(48)

OUT

Q

(47)

OUT

XOR

XOR

PN GENERATOR

CHIP RATE

SPREADER

TIMING

GENERATOR

MCLK

(28)

RESET

DPSK MODULATOR

CLK

I

LATCH

Q

MUX CLK

FOR DQPSK

I CH ONLY FOR DBPSK

PN CODE

11 TO 16-BIT

(30)

MCLK

DPSK DEMOD
AND AFC

DIFFERENTIAL
ENCODER

b(t)

b(t-1)

-1

Z

XOR

(1)

TEST_CK

XOR

RX_DATA

DESCRAMBLER

TX_DATA

SCRAMBLER

TEST PORT

(38)

(37) (39)

CODE

(40)

PREAMBLE/HEADER

(43)

(44)

CRC-16

PROCESSOR INTERFACE

(45)

(46)

PORT

RECEIVE

PORT

TRANSMIT

PORT

SERIAL CONTROL

(33) RX_PE
(35) RXD
(34) MD_RDY

(5) TX_RDY
(4) TXCLK

(3) TXD
(2) TX_PE

(25) SD
(24) SCLK

(23) AS
(8) R/W
(9) CS

2-104

TEST 0

TEST 1

FIGURE 1. DSSS BASEBAND PROCESSOR

TEST 2

TEST 3

TEST 4

TEST 5

TEST 6

TEST 7

HFA3824A

External Interfaces

There are three primary digital interface ports for the
HFA3824A that are used for configuration and during normal
operation of the device. These ports are:

• The TX Port, which is used to accept the data that needs

to be transmitted from the network processor.

• The RX Port, which is used to output the received

demodulated data to the network processor.

• The Control Port, which is used to configure, write and/or

read the status of the internal HFA3824A registers.
In addition to these primary digital interfaces the device

includes a byte wide parallel Test Port which can be config­ured to output various internal signals and/or data (i.e., PN
acquisition indicator, Correlator magnitude output etc.). The
device can also be set into various power consumption
modes by external control. The HFA3824A contains three
Analog to Digital (A/D) converters. The analog interfaces to
the HFA3824A include, the In phase (I) and quadrature (Q)
data component inputs, and the RF signal strength indicator
input. A reference voltage divider is also required external to
the device.

HFA3824A

ANALOG

INPUTS

REFERENCE

A/D

POWER

DOWN

SIGNALS

TEST

PORT

I (ANALOG)
Q (ANALOG)
RSSI (ANALOG)

V

REFN

V

REFP

TX_PE
RX_PE

RESET

8

TEST

FIGURE 2. EXTERNAL INTERFACE

TXD

TXCLK

TX_RDY

RXD
RXC

MD_RDY

C
SD

SCLK

R/W

AS

S

TX_PORT

RX_PORT

CONTROL_PORT

Control Port

The serial control port is used to serially write and read data
to/from the device. The serial control port is used to serially
write and read data to/from the device. This serial port can
operate up to a 11MHz rate or the maximum master clock
rate of the device, MCLK (whichever is lower). MCLK must
be running and
port is used to program and to read all internal registers. The
first 8 bits always represent the address followed immedi­ately by the 8 data bits for that register. The two LSBs of
address are don’t care. The serial transfers are accom­plished through the serial data pin (SD). SD is a bidirectional
serial data bus. An Address Strobe (AS), Chip Select (
and Read/
nals for this port. The clock used in conjunction with the
address and data on SD is SCLK. This clock is provided by
the external source and it is an input to the HFA3824A. The
timing relationships of these signals are illustrated on Figure
3 and 4. AS is active high during the clocking of the address
bits. R/

W is high when data is to be read, and low when it is
to be written.
machine.
transfer cycle.
operates asynchronously from the TX and RX ports and it
can accomplish data transfers independent of the activity at
the other digital or analog ports.
RX operation of the device; impacting only the operation of
the Control port. The HFA3824A has 57 internal registers
that can be configured through the control port. These regis­ters are listed in the Configuration and Control Internal Reg­ister table. Table 1 lists the configuration register number, a
brief name describing the register, and the HEX address to
access each of the registers. The type indicates whether the
corresponding register is Read only (R) or Read/Write
(R/W). Some registers are two bytes wide as indicated on
the table (high and low bytes).

RESET inactive during programming. This

CS),

Write (R/W) are also required as handshake sig-

CS must be sampled high to initialize state

CS must be active (low) during the entire data

CS selects the device. The serial control port

CS does not effect the TX or

FIRST ADDRESS BIT

SCLK

SD

AS

R/

W

CS

NOTES:

1. These diagrams assume the HFA3824A always uses the rising edge of SCLK, the controller the falling edge.

2. The CS is a synchronous interface in reference to SCLK. There is at least one clock required before CS transitions to its active state.

3. If the SD bus is shared, then R/W should be left Low, or CS High, to avoid bus conflicts.

76543210765432107654

1234567 01234567

FIGURE 3. CONTROL PORT READ TIMING

FIRST DATABIT OUT

LSBDATA OUTMSBMSB ADDRESS IN

2-105

HFA3824A

SCLK

SD

AS

R/W

CS

76543210765432107654

1234567 012345670

NOTE: Using falling edge SCLK to generate address/control and data.

FIGURE 4. CONTROL PORT WRITE TIMING

TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST

CONFIGURATION

REGISTER NAME TYPE

CR0 Modem Config. Register A R/W 00
CR1 Modem Config. Register B R/W 04
CR2 Modem Config. Register C R/W 08
CR3 Modem Config. Register D R/W 0C
CR4 Internal Test Register A R/W 10
CR5 Internal Test Register B R/W 14
CR6 Internal Test Register C R 18
CR7 Modem Status Register A R 1C
CR8 Modem Status Register B R 20

CR9 I/O Definition Register R/W 24
CR10 RSSI Value Register R 28
CR11 ADC_CAL_POS Register R/W 2C
CR12 ADC_CAL_NEG Register R/W 30
CR13 TX_Spread Sequence (High) R/W 34
CR14 TX_Spread Sequence (Low) R/W 38
CR15 Scramble_Seed R/W 3C
CR16 Scramble_Tap (RX and TX) R/W 40
CR17 Reserved R/W 44
CR18 Reserved R/W 48
CR19 RSSI_TH R/W 4C
CR20 RX_Spread Sequence (High) R/W 50
CR21 RX_Spread Sequence (Low) R/W 54
CR22 RX_SQ1_ ACQ (High) Threshold R/W 58
CR23 RX-SQ1_ ACQ (Low) Threshold R/W 5C
CR24 RX-SQ1_ ACQ (High) Read R 60
CR25 RX-SQ1_ ACQ (Low) Read R 64
CR26 RX-SQ1_ Data (High) Threshold R/W 68
CR27 RX-SQ1-SQ1_ Data (Low) Threshold R/W 6C
CR28 RX-SQ1_ Data (High) Read R 70
CR29 RX-SQ1_ Data (Low) Read R 74

LSBDATA INMSBMSB ADDRESS IN

REGISTER

ADDRESS HEX

2-106

HFA3824A

TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST (CONTINUED)

CONFIGURATION

REGISTER NAME TYPE

CR30 RX-SQ2_ ACQ (High) Threshold R/W 78
CR31 RX-SQ2- ACQ (Low) Threshold R/W 7C
CR32 RX-SQ2_ ACQ (High) Read R 80
CR33 RX-SQ2_ ACQ (Low) Read R 84
CR34 RX-SQ2_Data (High) Threshold R/W 88
CR35 RX-SQ2_Data (Low) Threshold R/W 8C
CR36 RX-SQ2_Data (High) Read R 90
CR37 RX-SQ2_Data (Low) Read R 94
CR38 RX_SQ_Read; Full Protocol R 98
CR39 Modem Configuration Register E R/W 9C
CR40 Reserved (must load 00h) W A0
CR41 UW_Time Out_Length R/W A4
CR42 SIG_DBPSK Field R/W A8
CR43 SIG_DQPSK Field R/W AC
CR44 RX_SER_Field R B0
CR45 RX_LEN Field (High) R B4
CR46 RX_LEN Field (Low) R B8
CR47 RX_CRC16 (High) R BC
CR48 RX_CRC16 (Low) R C0
CR49 UW (High) R/W C4
CR50 UW (Low) R/W C8
CR51 TX_SER_F R/W CC
CR52 TX_LEN (High) R/W D0
CR53 TX_LEN (LOW) R/W D4
CR54 TX_CRC16 (HIGH) R D8
CR55 TX_CRC16 (LOW) R DC
CR56 TX_PREM_LEN R/W E0

REGISTER

ADDRESS HEX

2-107

HFA3824A

TX Port

The transmit data port accepts the data that needs to be
transmitted serially from an external data source. The data is
modulated and transmitted as soon as it is received from the
external data source. The serial data is input to the HFA3824A
through TXD using the falling edge of TXCLK to clock it in the
HF A3824A.TXCLK is an output from the HFA3824A. A timing
scenario of the transmit signal handshakes and sequence is
shown on timing diagram Figures 5 and 6.

The external processor initiates the transmit sequence by
asserting TX_PE. TX_PE envelopes the transmit data packet
on TXD. The HFA3824A responds by generating TXCLK to
input the serial data on TXD. TXCLK will run until TX_PE goes
back to its inactive state indicating the end of the data packet.
TX_PE should be held active at least 3 symbols beyond the
MSB of the data packet to insure modulation by the
HF A3824A. There are tw o possible transmit scenarios.

One scenario is when the HFA3824A internally generates
the preamble and header information. During this mode the
external source needs to provide only the data portion of the
packet. The timing diagram of this mode is illustrated on
Figure 6. When the HFA3824A generates the preamble
internally, assertion of TX_PE will initialize the generation of
the preamble and header. TX_RDY, which is an output from
the HFA3824A, is used to indicate to the external processor
that the preamble has been generated and the device is
ready to receive the data packet to be transmitted from the

external processor. The TX_RDY timing is programmable in
case the external processor needs several clocks of
advanced notice before actual data transmission is to begin.

The second transmit scenario supported by the HFA3824A
is when the preamble and header information are provided
by the external data source. During this mode TX_RDY is
not required as part of the TX handshake. The HFA3824A
will immediately start transmitting the data available on TXD
upon assertion of TX_PE. The timing diagram of this TX sce­nario, where the preamble and header are generated exter­nal to the HFA3824A, is illustrated on Figure 5.

One other signal that can be used for certain applications as
part of the TX interface is the Clear Channel Assessment
(CCA) signal which is an output from the HFA3824A. The CCA
is programmable and it is described with more detail in the
Transmitter section of this document. CCA provides the indica­tion that the channel is clear of energy and the transmission will
not be subject to collisions. CCA can be monitored bythe exter­nal processor to assist in deciding when to initiate transmis­sions. The CCA indication can bypassed or ignored by the
external processor. The state of the CCA does not effect the
transmit operation of the HFA3824A. TX_PE alone will always
initiate the transmit state independent of the state of CCA. Sig­nals TX_RDY, TX_PE and TXCLK can be set individually, by
programming Configuration Register (CR) 9, as either active
high or active low signals.

The transmit port is completely independent from the
operation of the other interface ports including the RX port,
therefore supporting a full duplex mode.

TXCLK

TX_PE

TXD

NOTE: Preamble/Header and Data istransmitted LSB firstTX_RDYisinactiveLogic0 when generated externally.TXD shown generated from rising
edge TXCLK.

TXCLK

TX_PE

TXD

TX_RDY

PREAMBLE - HEADER

MSB OF LAST HEADER FIELD

FIGURE 5. TX PORT TIMING (EXTERNAL PREAMBLE)

LSB DATA PACKET MSB

LSB DATA PACKET MSB

MSB OF LAST HEADER FIELD

NOTE: Preamble/Header and Data istransmittedLSB first TX_RDYis inactive Logic 0whengeneratedexternally. TXD shown generated from rising
edge TXCLK.

FIGURE 6. TX PORT TIMING (INTERNAL PREAMBLE)

2-108

HFA3824A

RX Port

The timing diagram Figure 7 illustrates the relationships
between the various signals of the RX port. The receive data
port serially outputs the demodulated data from RXD. The
data is output as soon as it is demodulated by the
HFA3824A. RX_PE must be at its active state throughout the
receive operation. When RX_PE is inactive the device's
receive functions, including acquisition, will be in a stand by
mode.

RXCLK is an output from the HFA3824A and is the clock for
the serial demodulated data on RXD. MD_RDY is an output
from the HFA3824A and it envelopes the valid data on RXD.
The HFA3824A can be also programmed to ignore error
detections during the CCITT - CRC 16 check of the header
fields. If programmed to ignore errors the device continues to
output the demodulated data in its entirety regardless of the
CCITT - CRC 16 check result. This option is programmed
through CR 2, bit 5.

Note that RXCLK becomes active after acquisition, well
before valid data begins to appear on RXD and MD_RDY is
asserted. MD_RDY returns to its inactive state under the fol­lowing conditions:

• The number of data symbols, as defined by the length
field in the header, has been received and output
through RXD in its entirety (normal condition).

• PN tracking is lost during demodulation.

• RX_PE is deactivated by the external controller.

MD_RDY and RXCLK can be configured through CR 9, bit 6­7 to be active low, or active high. Energy Detect (ED) pin 45
(Test port), and Carrier Sense (CRS) pin 46 (Test port), are
available outputs from the HFA3824A and can be useful
signals for an effective RX interface design. Use of these
signals is optional. CRS and ED are further described within
this document. The receive port is completely independent
from the operation of the other interface ports including the
TX port, supporting therefore a full duplex mode.

I/Q ADC Interface

The PRISM baseband processor chip (HFA3824A) includes
two 3-bit Analog to Digital converters (ADCs) that sample
the analog input from the IF down converter. The I/Q ADC
clock, MCLK, samples at twice the chip rate. The maximum
sampling rate is 44MHz.

The interface specifications for the I and Q ADCs are listed
in Table 2.

TABLE 2. I, Q, ADC SPECIFICATIONS

PARAMETER MIN TYP MAX

Full Scale Input Voltage (V
Input Bandwidth (-0.5dB) - 20MHz ­Input Capacitance (pF) - 5 ­Input Impedance (DC) 5kΩ -­FS (Sampling Frequency) - - 44MHz

The voltagesapplied to pin 16,V
the references for the internal I and Q ADC converters. In
addition, V

is also used to set the RSSI ADC converter

REFP

reference. For a nominal 500mV
voltage is 1.75V, and the suggested V
should never be less than 0.25V. Since these ADCs are
intended to sample AC voltages, their inputs are biased
internally and they should be capacitively coupled.

The ADC section includes a compensation (calibration) cir­cuit that automatically adjusts for temperature and compo­nent variations of the RF and IF strips. The variations in gain
of limiters, AGC circuits, filters etc. can be compensated for
up to ±4dB. Without the compensation circuit, the ADCs
could see a loss of up to 1.5 bits of the 3 bits of quantization.
The ADC calibration circuit adjusts the ADC reference volt­ages to maintain optimum quantization of the IF input over
this variation range. It works on the principle of setting the
reference to insure that the signal is at full scale (saturation)
a certain percentage of the time. Note that this is not an
AGC and it will compensate only for slow variations in signal
levels (several seconds).

) 0.25 0.50 1.0

P-P

and pin 17, V

REFP

, the suggested V

P-P

REFN

is 0.93V. V

REFN

set

REFP
REFN

RXCLK

RX_PE

CRS (TEST 7)

MD_RDY

RXD

NOTE: MD_RDY active after CRC16.

2-109

PROCESSING

PREAMBLE/HEADER

LSB DATA MSB

FIGURE 7. RX PORT TIMING

HFA3824A

The procedure for setting the ADC references to
accommodate various input signal voltage levels is to set the
reference voltages so that the ADC calibration circuit is oper­ating at half scale. This leaves the maximum amount of
adjustment room for circuit tolerances.

Figure 8 illustrates the suggested interface configuration for
the ADCs and the reference circuits.

I

IN

Q

IN

V

REFP

V

REFN

HFA3824A

2V

I

Q

0.01µF

3.9K

0.01µF

8.2K

9.1K

FIGURE 8. INTERFACES

0.01µF

0.01µF

ADC Calibration Circuit and Registers

The ADC compensation or calibration circuit is designed to
optimize ADC performance for the I and Q inputs by main­taining the full 3-bit resolution of the outputs. There are two
registers (CR 11 AD_CAL_POS and CR 12 AD_CAL_NEG)
that set the parameters for the internal I and Q ADC calibra­tion circuit.

Both I and Q ADC outputs are monitored by the ADC calibra­tion circuit and if either has a full scale value, a 24-bit accu­mulator is incremented as defined by parameter
AD_CAL_POS. If neither has a full scale value, the accumu­lator is decremented as defined by parameter
AD_CAL_NEG.

A loop gain reduction is accomplished by using only the 5
MSBs out of the 24 bits to drive a D/A converter that adjusts
the ADCs reference. The compensation adjustment is
updated at 2kHz rate for a 2 MBPS operation. The ADC cali­bration circuit is only intended to remove slow component
variations.

The ratio of the values from the two registers CR11 and
CR12 set the probability that either the I or Q ADC converter
will be at the saturation. The probability is set by
(AD_CAL_POS)/(AD_CAL_NEG).

This also sets the levels so that operation with either NOISE
or DPSK is approximately the same. It is assumed that the
RF and IF sections of the receiver have enough gain to
cause limiting on thermal noise. This will keep the levels at
the ADC approximately same regardless of whether signal is
present or not.

The ADC calibration voltage is automatically held during
transmit in half duplex operation.

The ADC calibration circuit operation can be defined through
CR 1, bits 1 and 0. Table 3 illustrates the possible
configurations.

TABLE 3. ADC CALIBRATION

CR 1

BIT 0

0 0 Automatic real time adjustment of reference.
0 1 Reference set at mid scale.
1 0 Reference held at most recent value.
1 1 Reference set at mid scale.

CR 1

BIT 1

ADC CALIBRATION CIRCUIT

CONFIGURATION

RSSI ADC Interface

The Receive Signal Strength Indication (RSSI) analog signal is
input to a 6-bit ADC, indicating 64 discrete levels of received
signal strength. This ADC measures a DC voltage, so its input
must be DC coupled. Pin 16 (V
RSSI ADC converter. V

REFP

) sets the reference for the

REFP

is common for the I and Q and
RSSI ADCs. The RSSI signal is used as an input to the pro­grammable Clear Channel Assessment algorithm of the
HF A3824A. The RSSI ADC output is stored in an 8-bit register
(CR10) and it is updated at the symbol rate for access by the
external processor to assist in network management.

The interface specifications for the RSSI ADC are listed in
Table 4 below (V

TABLE 4. RSSI ADC SPECIFICATIONS

PARAMETER MIN TYP MAX

Full Scale Input Voltage - - 1.15
Input Bandwidth (0.5dB) 1MHz - ­Input Capacitance - 7pF ­Input Impedance (DC) 1M - -

REFP

= 1.75V).

Test Port

The HFA3824A provides the capability to access a number
of internal signals and/or data through the Test port, pins
TEST 0-7. In addition pin 1 (TEST_CK) is an output clock
that can be used in conjunction with the data coming from
the test port outputs. The test port is programmable through
configuration register (CR5).

There are 9 test modes assigned to the PRISM test port
listed in Test Modes Table 5.

TABLE 5. TEST MODES

MODE DESCRIPTION TEST_CLK TEST (7:0)

0 Normal

Operation

1 Correlator Test

Mode

2 Frequency Test

Mode

3 Phase Test

Mode
4 NCO Test Mode DCLK NCO Phase Accum Reg
5 SQ Test Mode LoadSQ SQ2 (15:8) Phase

6 Bit Sync Test

Mode 1

TXCLK CRS, ED, “000”, Initial

Detect, Reserved (1:0)

TXCLK Mag (7:0)

DCLK Frq Reg (7:0)

DCLK Phase (7:0)

Variance

RXCLK Bit Sync Accum (7:0)

2-110