Datasheet HFA3724 Datasheet (Intersil Corporation)

HFA3724

Data Sheet November 1999 File Number 4067.7

400MHz Quadrature IF
Modulator/Demodulator

™

The Intersil 2.4GHz PRISM™ chip set is a
highly integrated five-chip solution for RF
modems employing Direct Sequence
Spread Spectrum (DSSS) signaling. The

HF A3724 400MHz Quadrature IF
Modulator/Demodulator is one of the five chips in the PRISM™
chip set (see the Typical Application Diagram).

The HF A3724 is a highly integr ated baseband con v erter for
quadrature modulation applications. It features all the necessary
blocks for baseband modulation and demodulation of I and Q
signals. It has a two stage integrated limiting IF amplifier with 84db
of gain with a built in Receive Signal Strength Indicator (RSSI).
Baseband antialiasing and shaping filters are integrated in the
design. Four filter bandwidths are programmable via a tw o bit
digital control interface. In addition, these filters are continuously
tunableovera±20%frequencyrangeviaoneexternalresistor .The
modulator channel receives digital I and Q data for processing. To
achieve broadband operation, the Local Oscillator frequency input
is required to be twice the desired frequency of
modulation/demodulation. A selectable buffered divide b y 2 LO
output and a stable reference voltage are provided for convenience
of the user. The de vice is housed in a thin 80 lead TQFP pac kage
well suited for PCMCIA board applications.

Ordering Information

TEMP. RANGE

PART NUMBER

HFA3724IN -40 to 85 80 Ld TQFP Q80.14x14
HFA3724IN96 -40 to 85 Tape and Reel

(oC) PACKAGE PKG. NO.

Features

• Integrates all IF Transmit and Receive Functions

• Broad Frequency Range . . . . . . . . . . .10MHz to 400MHz

• I/Q Amplitude and Phase Balance . . . . . . . . . . . 0.2dB, 2

• 5th Order Programmable

Low Pass Filter. . . . . . . . . . . . . . . . . . .2.2MHz - 17.6MHz

• 400MHz Limiting IF Gain Strip with RSSI. . . . . . . . . .84dB

• Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm

• Fast Transmit-Receive Switching . . . . . . . . . . . . . . . . .1µs

• Power Management/Standby Mode

• Single Supply 2.7V to 5.5V Operation

Applications

• Systems Targeting IEEE 802.11 Standard

• TDD Quadrature-Modulated Communication Systems

• Wireless Local Area Networks

• PCMCIA Wireless Transceivers

• ISM Systems

• TDMA Packet Protocol Radios

• PCS/Wireless PBX

• Wireless Local Loop

o

Simplified Block Diagram

LIM1_IN

MOD_LO_IN

MOD_LO_OUT

LO_GND

MOD_TX_IF_OUT

1

RSSI1
RSSI2

LIM1_OUT

LIM2_IN

LIM2_OUT

MOD_IF_IN

IFIF

÷2

∑

2V

REF

2V REF

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

MOD_RX_I

MOD_RX_Q

LPF_RX_Q

M

o

0o/90

U
X

LPF_TX_I

MOD_TX_I

MOD_TX_Q

1-888-INTERSIL or 321-724-7143

LPF_RX_I

I

Q

LPF_TX_Q

LPF_TUNE_1

LPF_SEL0

LPF_SEL1

LPF_TUNE_0

M
U
X

LPF_RXI_OUT

LPF_RXQ _OUT

LPF_TXI_IN

LPF_TXQ_IN

| Copyright © Intersil Corporation 1999

Pinout

LIM1_RSSI

RSSI_RL1

GND

LIM1_OUT+

80 LEAD TQFP

LIM1_OUT-

LIM1_VCCLIM1_PE

HFA3724

TOP VIEW

GND

GND

GND

GND

GND

GND

GND

GND

GND

LIM2_BYP-

LIM2_IN-

LIM2_IN+

LIM2_BYP+

LIM1_BYP+

LIM1_IN+

LIM1_IN-

LIM1_BYP-

GND
GND
GND

GND

LPF_V

CC

2V REF

LPF_BYP

LPF_TXI_IN

LPF_TXQ_IN

LPF_RXI_OUT

LPF_RXQ_OUT

LPF_SEL1

LPF_SEL0
LPF_TUNE1
LPF_TUNE0

GND

80

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

2122 23 24 2526 27 28 2930 31 32 3334 35 36

GND

GND

LPF_TXI+

LPF_RXQ-

LPF_RXQ+

LPF_RXI-

LPF_RXI+

LPF_TXQ-

LPF_TXQ+

LPF_TX_PE

LPF_RX_PE

LPF_TXI-

MOD_RXI-

MOD_RXI+

MOD_RXQ-

MOD_RXQ+

64656667686970717273747576777879

6362 61

3738 39 40

MOD_TXI-

MOD_TXI+

MOD_TXQ+

LIM2_RSSI

60

RSSI_RL2

59

GND

58

LIM2_OUT+

57

LIM2_OUT-

56

LIM2_V

55
54

LIM2_PE

53

GND

52

GND

51

GND
LO_GND

50
49

MOD_IF_IN-

48

MOD IF_IN+

47

MOD_V

46

MOD_LO_OUT

45

MOD_V

44

MOD_LO_IN
MOD_RX_PE

43

MOD_TX_IF_OUT

42
41

MOD_TX_PE

MOD_TXQ-

CC

CC

CC

2

Block Diagram

HFA3724

LPF_TUNE0

LPF_TUNE1

LPF_RX PE

LPF_RX I -

LPF_RX I +

LPF_RX Q +

LPF_RX Q -

MOD_RX Q -

MOD_RX Q +

MOD_RX I -

MOD_RX I +

MOD_RX PE

MOD_IF_IN +

MOD_IF_IN -

LIM2_OUT -

LIM2_OUT +

LIM2_PE

LIM2_IN+

LIM2_IN-

LIM1_OUT -

LIM1_OUT +

LIM1_PE

LPF_SEL1
LPF_SEL0

DOWN CONV

LPF_RXI_OUT

IF

IF

LPF_RXQ_OUT

I

IF LIMITERS

MUX

MUX

o

/90

o

0

÷2

LPF_TXI_IN

Q

UP CONVERTER

LPF_TXQ_IN

∑

2V

REF

MUX_LPF

LPF_TX_PE

LPF_TX_Q ­LPF_TX_Q +

LPF_TX_I ­LPF_TX_I +

MOD TX I +
MOD TX I -

MOD TX Q +
MOD TX Q -

MOD_TX_PE

2V REF

LIM1_IN+

SAW

IF

LIM1_IN-

LIM1_RSSI

IN

NOTE: VCC, GND and Bypass capacitors not shown.

3

RSSI_RL1

RSSI_RL2

LIM2_RSSI

RSSI

LO_GND

(2XLO)

MOD_LO_IN

CC

V

50Ω

MOD_LO_OUT

IF_OUT

MOD_TX

LPF_BYP

1.25V

Typical Application Diagram

HFA3724

HFA3724

(FILE# 4067)

HF A3424 (NOTE)

(FILE# 4131)

HF A3624

RF/IF

CONVERTER

(FILE# 4066)

RFPA

HF A3925

VCO

VCO

(FILE# 4132)

DUAL SYNTHESIZER

HFA3524

(FILE# 4062)

TYPICAL TRANSCEIVER APPLICATION USING THE HFA3724

NOTE: Required for systems targeting 802.11 specifications.

For additional information on the PRISM™ chip set, call
[phone] to access Intersil’ AnswerFAX system. When
prompted, key in the four-digit document number (File #) of
the datasheets you wish to receive.

÷2

0o/90

QUAD IF MODULATOR

TUNE/SELECT

I

M

o

U

X

Q

HSP3824

(FILE# 4064)

RXI

RXQ

RSSI

M
U
X

A/D

DE-

SPREAD

A/D

CCA

A/D

TXI

SPREAD

TXQ

DSSS BASEBAND PROCESSOR

PRISM™ CHIP SET FILE #4063

DPSK

DEMOD

802.11

MAC-PHY

INTERFACE

DPSK

MOD.

DATA TO MACCTRL

The four-digit file numbers are shown in Typical Application
Diagram, and correspond to the appropriate circuit.

4

HFA3724

Typical Application Diagram (Targeting IEEE 802.11 Standard)

RF/IFIF/RF

HFA3624IA

CONVERTER

TOYOCOM

TQS 432

(NOTE 1)

100p

56n

0.1

V

0.1

2

260

3

1

100p

100p

TOYOCOM

TQS 432

CC

75

4

100p

V

CC

1K

47

(NOTE 4)

NC

V

316

42

50

CC

0.1

45

48

49

44

46

43

47

0.01

34

0.01

0.01

36

0.01

(NOTE 5)

0.01

38

0.01

0.01

40

0.01

V

(NOTE 2)

PE

74

77

76

80

79

VCO

100p

100p

47p

8 TO 40p

100p

10nH

560

0.1

100p

CC

0.1
55

62
63

64

61

100p

100p

LO_IN

(NOTE 6)

TX_IF_OUT

560MHz
VCO (AUXILIARY)

59

PE

54

57

56

60

100p

0.1

47nH

100p

100p

100p

47p

(NOTE 3)

47p 220

56

900

V

CC

0.1

9

3033
29

2835
27

18

19

2637
25

2439
23

RXI_OUT

14

RXQ_OUT

15
20

16

17

10
2V REF

12

680

11
680

13

212241

0.01

0.01

LPF_SEL1

V

CC

LPF_SEL0

0.1

TXI

4.3K

0.1

TXQ

4.3K

RSSI

HSP3824VI

BASEBAND PROCESSOR

DUAL SYNTHESIZER

HFA3524IA

MOD_TX_PE

MOD_RX_PE

LPF_TX_PE

LPF_RX_PE

TYPICAL APPLICATION DIAGRAM (TARGETING IEEE 802.11 STANDARD)

NOTES:

1. Input termination used to match a SAW filter.

2. Typical bandpass filter for 280MHz, BW = 47MHz, Q = 6. Can also be used if desired after the second stage.

3. Network shown for a typical -10dBm input at 50Ω.

4. Output termination used to match a SAW filter.

5. R

value for a 7.7MHz cutoff frequency setting.

TUNE

6. LO buffer output termination is needed only when the buffer is enabled by pin 50 connected to GND, otherwise tie pin 46 to pin 47.

5

HFA3724

Pin Description

PIN SYMBOL DESCRIPTION

1 LIM1_BYP+ DC feedback pin for Limiter amplifier 1. Requires good decoupling and minimum wire length to a solid signal

ground.
2 LIM1_In+ Non inverting analog input of Limiter amplifier 1.
3 LIM1_In- Inverting input of Limiter amplifier 1.
4 LIM1_BYP- DC feedback pin for Limiter amplifier 1. Requires good decoupling and minimum wire length to a solid signal

ground.

5, 6,

7, 8

9 LPF_V

10 2V REF Stable 2V reference voltage output for external applications. Loading must be higher than 10kΩ. A bypass

11 LPF_BYP Internal reference bypass pin. This is the common voltage (VCM) used for the LPF digital thresholds. Requires

12 LPF_TXI_In Low pass filter in phase (I) channel transmit input. Conventionalor attenuated direct coupling is required for digital

13 LPF_TXQ_In Low pass filter quadrature (Q) channel transmit input. Conventional or attenuated direct coupling is required for

14 LPF_RXI_Out Low pass filter in phase (I) channel receive output. Requires AC coupling. (Note 8)
15 LPF_RXQ_Out Low pass filter quadrature (Q) channel receive output. Requires AC coupling. (Note 8)
16 LPF_Sel1 Digitalcontrol input pins. Selects fourprogramed cut off frequencies for both receive and transmit channels. Tuning
17 LPF_Sel0

18 LPF_Tune1 These two pins are used to fine tune the Low pass filter cutoff frequency. A resistor connected between the two
19 LPF_Tune0

20 GND Ground. Connect to a solid ground plane.
21 LPF_RX_PE Digital input control pin to enable the LPF receive mode of operation. Enable logic level is High.
22 LPF_TX_PE Digital input control pin to enable the LPF transmit mode of operation. Enable logic level is High.
23 LPF_TXQ- Negativeoutput of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to

24 LPF_TXQ+ Positive output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to

25 LPF_TXI- Negative output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to

26 LPF_TXI+ Positiveoutput of the transmit Low pass filter,in phase channel. AC coupling is required. Normally connects to the

27 LPF_RXQ- Low pass filter inverting input of the receive quadrature channel. AC coupling is required. This input is normally

28 LPF_RXQ+ Lowpass filternon inverting input of the receive quadrature channel. ACcoupling is required. Thisinput is normally

29 LPF_RXI- Low pass filter inverting input of the receive in phase channel. AC coupling is required. This input is normally

30 LPF_RXI+ Low pass filter non inverting input of the receive in phase channel. AC coupling is required. This input is normally

31, 32 GND Ground. Connect to a solid ground plane.

GND Ground. Connect to a solid ground plane.

CC

Supply pin for the Low pass filter. Use high quality decoupling capacitors right at the pin.

capacitor of at least 0.1µF is required.

0.1µF decoupling capacitor.

inputs. (Note 7)

digital inputs. (Note 7)

speed from one cutoff to another is less than 1µs.

SEL1 SEL0 Cutoff Frequency SEL1 SEL0 Cutoff Frequency

LO LO 2.2MHz HI LO 8.8MHz

LO HI 4.4MHz HI HI 17.6MHz

pins (R

specifications.

the inverting input of the quadrature Modulator (Mod_TXQ-), pin 40.

the non inverting input of the quadrature Modulator (Mod_TXQ+), pin 39.

the inverting input of the in phase Modulator (Mod_TXI-), pin 38.

non inverting input of the in phase Modulator (Mod_TXI+), pin 37.

coupled to the negative output of the quadrature demodulator (Mod_RXQ-), pin 36.

coupled to the positive output of the quadrature demodulator (Mod_RXQ+), pin 35.

coupled to the negative output of the in phase demodulator (Mod_RXI-), pin 34.

coupled to the positive output of the in phase demodulator (Mod_RXI-), pin 33.

) will fine tune both transmit and receive filters. Refer to the tuning equation in the LPF AC

TUNE

6

HFA3724

Pin Description (Continued)

PIN SYMBOL DESCRIPTION

33 Mod_RXI+ In phase demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the

Low pass filter (LPF_RXI+), pin 30.

34 Mod_RXI- In phase demodulator negativeoutput. AC coupling is required. Normally connects to the inverting input of the Low

pass filter (LPF_RXI-), pin 29.

35 Mod_RXQ+ Quadrature demodulator positive output. AC coupling is required. Normally connects to the non inverting input of

the Low pass filter (LPF_RXQ+), pin 28.

36 Mod_RXQ- Quadrature demodulator negative output. AC coupling is required. Normally connects to the inverting input of the

Low pass filter (LPF_RXQ+), pin 27.

37 Mod_TXI+ In phase modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass

filter positive output (LPF_TXI+), pin 26.

38 Mod_TXI- In phase modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter

negative output (LPF_TXI-), pin 25.

39 Mod_TXQ+ Quadraturemodulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass

filter positive output (LPF_TXQ+), pin 24.

40 Mod_TXQ- Quadrature modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter

negative output (LPF_TXQ-), pin 23.

41 Mod_TX_PE Digital input control to enable the Modulator section. Enable logic level is High for transmit.
42 Mod_TX_IF_Out Modulator open collector output, single ended. Termination resistor to VCC with a typical value of 316Ω.
43 Mod_RX_PE Digital input control to enable the demodulator section. Enable logic level is High for receive.
44 Mod_LO_In

(2XLO)

45 Mod_V
46 Mod_LO_Out Divide by 2 buffered output reference from “Mod_LO_in” input. Used for external applications where the modulating

47 Mod_V
48 Mod_IF_In+ Demodulator non inverting input. Requires AC coupling.
49 Mod_IF In- Demodulator inverting input. Requires AC coupling.
50 LO_GND When grounded, this pin enables the LO buffer (Mod_LO_Out). When open (NC) it disables the LO buffer.

51, 52,

53
54 LIM2_PE Digital input control to enable the limiter amplifier 2. Enable logic level is High.
55 LIM2_V
56 LIM2_Out- Positive output of limiter amplifier 2. Requires AC coupling.
57 LIM2_Out+ Negative output of limiter amplifier 2. Requires AC coupling.
58 GND Ground. Connect to a solid ground plane.
59 RSSI_RL2 Load resistor to ground. Nominal value is 6kΩ. This load is used to terminate the LIM RSSI current output and

60 LIM2_RSSI Current output of RSSI for the limiter amplifier 2. Connect in parallel with the RSSI output of the amplifier limiter 1

61 LIM2_BYP+ DC feedback pin for Limiter amplifier 2. Requires good decoupling and minimum wire length to a solid signal

62 LIM2_In+ Non inverting analog input of Limiter amplifier 2.

CC

CC

GND Ground. Connect to a solid ground plane.

CC

Single ended local oscillator current input. Frequency of input signal must be twice the required modulator carrier

and demodulator LO frequency. Input current is optimum at 200µA

be designed for a wide range of power and impedances at this port. Typical input impedance is 130Ω.This pin

requires AC coupling. (Note 9)

NOTE: High second harmonic content input waveforms may degrade I/Q phase accuracy.

Modulator/Demodulator supply pin. Use high quality decoupling capacitors right at the pin.

and demodulating carrier reference frequency is required. 50Ω single end driving capability.This output can be

disabled by use of pin 50. AC coupling is required, otherwise tie to pin 47 (VCC).

Modulator/Demodulator supply pin. Use high quality decoupling capacitors right at the pin.

Limiter amplifier 2 supply pin. Use high quality decoupling capacitors right at the pin.

maintain temperature and process variation to a minimum.

for cascaded response.

ground.

. Input matching networks and filters can

RMS

7

HFA3724

Pin Description (Continued)

PIN SYMBOL DESCRIPTION

63 LIM2_In- Inverting input of Limiter amplifier 2.
64 LIM2_BYP- DC feedback pin for Limiter amplifier 2. Requires good decoupling and minimum wire length to a solid signal

ground.

65, 66,
67, 68,
69, 70,
71, 72,

73
74 LIM1_PE Digital input control to enable the limiter amplifier 1. Enable logic level is High.
75 LIM1_V
76 LIM1_Out- Negative output of limiter amplifier 1. Requires AC coupling.
77 LIM1_Out+ Positive output of limiter amplifier 1. Requires AC coupling.
78 GND Ground. Connect to a solid ground plane.
79 RSSI_RL1 Load resistor to ground. Nominal value is 6kΩ. This load is used to terminate the LIM RSSI current output and

80 LIM1_RSSI Current output of RSSI for the limiter amplifier 1. Connect in parallel with the RSSI output of the amplifier limiter 2

NOTES:

7. The HFA3724 generates a lower sideband signal when the “I” input leads the “Q” input by 90 degrees.

8. For a reference LO frequency higher than a CW IF signal input, the “I” channel leads the “Q” channel by 90 degrees.

9. The in-phase reference LO transitions occur at the rising edges of the 2XLO clock signal. Quadrature LO transitions occur at the falling edges.
180 degrees phase ambiguity is expected for carrier locked systems without differential encoding.

GND Ground. Connect to a solid ground plane.

CC

Limiter amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin.

maintain temperature and process variation to a minimum.

for cascaded response.

TABLE 1. POWER MANAGEMENT

TRANSMIT RECEIVE POWER DOWN

LIM1_PE 0 1 0
LIM2_PE 0 1 0
LPF_RX_PE 0 1 0
MOD_RX_PE 0 1 0
MOD_TX_PE 1 0 0
LPF_TX_PE 1 0 0

8

HFA3724

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V

Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V

Operating Conditions

Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . .+2.7V to +5.5V

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -40oC ≤ TA≤ 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

10. θJAis measured with the component mounted on an low effective thermal conductivity test board in free air. See Technical Brief 379 for details.

Thermal Resistance (Typical, Note 10) θJA (oC/W)

TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Package Power Dissipation at 70oC

TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.1W

Maximum Junction Temperature (Plastic Package . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . .-65oC ≤ TA≤ 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(TQFP - Lead Tips Only)

DC Electrical Specifications V

= 2.7V to 5.5V, Unless Otherwise Specified

CC

(NOTE 11)

TEST

PARAMETER SYMBOL

Total Supply Current, RX Mode at 5.5V RXI
Total Supply Current, TX Mode at 5.5V TXI
Shutdown Current at 5.5V I
All Digital Inputs VIH (TTL Threshold for All VCC)V
All Digital Inputs VIL (TTL Threshold for All VCC)V
High Level Input Current at 2.7V VCC, VIN = 2.4V I
High Level Input Current at 5.5V VCC, VIN = 4.0V I
Low Level Input Current, VIN = 0.8V I

CC

CC

CCOFF

IH
IL

IHI

IHh

IL

LEVEL

A Full - 70 105 mA
A Full - 60 80 mA
A Full - 0.8 2.0 mA
A Full 2.0 - V
A Full -0.2 - 0.8 V
A25--80µA
A 25 - - 400 µA
A 25 -20 - +20 µA

TEMP

(oC) MIN TYP MAX UNITS

CC

RX to TX/TX to RX Switching Speed (Figure 23) PEt B 25 - 2 - µs
Power Down/Up Switching Speed (Figure 23) PEtpd B 25 - 10 - µs
Reference Voltage V
Reference Voltage Variation Over Temperature V
Reference Voltage Variation Over Supply Voltage V
Reference Voltage Minimum Load Resistance V

REF
REFT
REFV

REFRL

A Full 1.87 2.0 2.13 V
B 25 - 800 - µV/oC
B 25 - 1.6 - mV/V
C2510- -kΩ

NOTE:

11. A = Production Tested, B = Based on Characterization, C = By Design

V

AC Electrical Specifications, Demodulator Performance Application Targeting IEEE 802.11, V

= 3V, Figure 23

CC

Unless Otherwise Specified

(NOTE 12)

PARAMETER SYMBOL

TEST

LEVEL

TEMP

o

C) MIN TYP MAX UNITS

(

IF Demodulator 3dB Limiting Sensitivity (Note 13) D3db B 25 - -84 - dBm
IF Demodulator I and Q Outputs Voltage Swing DIQsw A Full 300 460 650 mV
IF Demodulator I and Q Channels Output Drive Capability

(Z

OUT

= 50Ω) C

MAX

= 10pF

Doutz C 25 1.2 2 - kΩ

P-P

IF Demodulator I/Q Amplitude Balance, IFin = -70dbm at 50Ω Dabal A Full -1.0 0 +1.0 dB
IF Demodulator I/Q Phase Balance, IFin = -70dbm at 50Ω Dphbal A Full -4.0 0 +4.0 Degrees
IF Demodulator Output Variation at -70dbm to 0dbm input Dovar A Full -0.5 0 +0.5 dB
IF Demodulator RSSI Noise Induced Offset Voltage (Note 14) Drssio B 25 - 580 - mV
IF Demodulator RSSI Voltage Output Slope (Note 15) Drssis B 25 - 15 - mV/dB

9

DC

HFA3724

AC Electrical Specifications, Demodulator Performance Application Targeting IEEE 802.11, V

Unless Otherwise Specified (Continued)

(NOTE 12)

TEST

PARAMETER SYMBOL

IF Demodulator RSSI DC Level, Pin = -30dBm (Note 15) Drssi_30 A Full 0.90 1.46 1.71 V
IF Demodulator RSSI DC Level, Pin = -70dBm (Note 15) Drssi_70 A Full 0.456 0.86 0.99 V
IF Demodulator RSSI Linear Dynamic Range (Note 16) Drssidr B 25 - 60 - dB
IF Demodulator RSSI Rise and Fall Time from -30dBm to

-50dBm Input at 100pF Load

NOTES:

12. A = Production Tested, B = Based on Characterization, C = By Design

13. 2XLO input = 572MHz, measure IF input level required to drop the I and Q output at 6MHz by 3dB from a reference output generated at IF input
= -30dBm (hard limiting). LPF selected for 8.8MHz. This is a noise limited case with a BW of 47MHz. Please refer to the Overall Device
Description, IF limiter.

14. The residual DC voltage generated by the RSSI circuit due to a noise limited stage at the end of the chain with no IF input. IF port terminated
into 50Ω. Please referred to the Overall Device Description, IF limiter.

15. Both limiter RSSI current outputs are summed by on chip 6KΩ resistors in parallel.

16. Range is defined where the indicated received input strength by the RSSI is ±3dBm accurate.

Drssitr B 25 - 0.3 - µs

LEVEL

TEMP

o

(

C) MIN TYP MAX UNITS

AC Electrical Specifications, Modulator Performance Application Targeting IEEE 802.11, V

Unless Otherwise Specified

(NOTE 17)

TEST

PARAMETER SYMBOL

IF Modulator I/Q Amplitude Balance (Note 18) Mabal B 25 -1.0 0 +1.0 dB
IF Modulator I/Q Phase Balance (Note 18) Mphbal B 25 -4.0 0 +4.0 Degrees
IF modulator SSB Output Power (Note 19) Mssbpw A Full -12 -7 -4 dBm
IF Modulator Side Band Suppression (Note 19) Mssbss A Full 26 33 - dBc
IF Mod Carrier Suppression (LO Buffer Enabled) (Note 19) Mssbcs A Full 28 30 - dBc
IF Mod Carrier Suppression (LO Buffer Disabled) (Note 19) Mssbcs1 B 25 28 36 - dBc
IF Modulator Output Noise Floor (Out of Band) Moutn0 B 25 - -132 - dBm/Hz
IF Modulator I/Q 3dB Cutoff SEL0/1 = 2.2MHz (Note 20) Msel1f A Full 1.8 2.2 2.5 MHz
IF Modulator I/Q 3dB Cutoff SEL0/1 = 4.4MHz (Note 20) Msel2f A Full 3.6 4.4 5.0 MHz
IF Modulator I/Q 3dB Cutoff SEL0/1 = 8.8MHz (Note 20) Msel3f A Full 7.3 8.8 9.8 MHz
IF Modulator I/Q 3dB Cutoff SEL0/1 = 17.6MHz (Note 20) Msel4f A Full 14.6 17.6 19.6 MHz
IF Modulator Spread Spectrum Output Power (Note 21) Mdsspw B 25 -12 -7 -4 dBm
IF Modulator Side Lobe to Main Lobe Ratio, LPF = 8.8MHz

(Note 21)

NOTES:

17. A = Production Tested, B = Based on Characterization, C = By Design

18. Data is characterized by DC levels applied to MOD TXI and Q pins for 4 quadrants with LO output as reference or indirectly by the SSB
characteristics.

19. Power at the fundamental SSB frequency of two 6MHz, 90 degrees apart square waves applied at TXI and TXQ inputs. VIH= 3.0V,
VIL = 0.5V. LPF selected to 8.8MHz cutoff.

20. Cutoff frequencies are specified for both modulator and demodulator as the filter bank is shared and multiplexed for Transmit and Receive. Data
is characterized by observing the attenuation of the fundamental of a square wave digital input swept at each channel separately. The IF output
is down converted by an external wideband mixer with a coherent LO input for each of quadrature signals separately.

21. Typical ratio characterization with R
11M chip/s, 223-1 sequence code signals.

set to 7.7MHz, LPF selected for 8.8MHz. TXI and TXQ Digital Inputs at two independent and aligned

TUNE

Mdsssl B 25 - 35 - dB

LEVEL

TEMP

(oC) MIN TYP MAX UNITS

= 3V, Figure 23

CC

= 3V, Figure 23

CC

DC
DC

10

HFA3724

Typical Performance Curves, Demodulator (See Figure 23 Test Diagram)

10mA/DIV.

90

SUPPLY CURRENT (mA)

10

2.5 5.54.0
V

CC

FIGURE 1. DEMODULATORSUPPLY CURRENT vs V

TEMPERATURE

40mV/DIV.

700

)

P-P

500

CC

85
25

-40

AND

85
25

-40

50mV/DIV.

o
o

o

400

)

P-P

OUTPUT SWING (mV

100

-100 -80 -60 -40 -20 0

INPUT POWER (dBm INTO 50Ω)

VCC = 3V

FIGURE 2. DEMODULATORI/Q OUTPUT SWING vs INPUT

POWER

1dBm/DIV.

o
o

o

-80

-85

-40

o

85

o

25

o

OUTPUT SWING (mV

300

2.5

4.0

V

CC

5.5

FIGURE 3. DEMOD I/Q OUTPUT SWING vs VCCAND

TEMPERATURE

0.2o/DIV.

o

+1

0

PHASE BALANCE VARIATION

-1

o

o

2.5

EXPECTED VARIATION

WINDOW vs V

4.0

V

CC

CC

FIGURE 5. DEMOD I/Q PHASE BALANCE VARIATION vs V

5.5

CC

-3dB SENSITIVITY (dBm INTO 50Ω)

-90

2.5

4.0

V

CC

5.5

FIGURE 4. CASCADED LIMITER -3dB INPUT SENSITIVITY

RESPONSE vs VCC AND TEMPERATURE

0.1dB/DIV.

+0.4dB

EXPECTED VARIATION

WINDOW vs V

V

CC

4.0

CC

AMPLITUDE BALANCE VARIATION

0.0dB

-0.4dB

2.5

FIGURE 6. DEMOD I/Q AMPLITUDE BALANCE VARIATION vs V

5.5

CC

11

HFA3724

Typical Performance Curves, Demodulator (See Figure 23 Test Diagram) (Continued)

0.4dB/DIV.

o

+2

0

PHASE BALANCE VARIATION

-2

o

o

-60

-40

EXPECTED VARIATION

WINDOW vs TEMP

-20 0 20 40 60
TEMPERATURE

80

FIGURE 7. DEMOD I/Q PHASE BALANCE VARIATION vs

TEMPERATURE

100mV/DIV.

1.5V

1.0V

100

0.1dB/DIV.

+0.4dB

EXPECTED VARIATION

WINDOW vs TEMP

-20 0 20 40 60
TEMPERATURE

80

-0.4dB

AMPLITUDE BALANCE VARIATION

0.0dB

-60

-40

FIGURE8. DEMODI/Q AMPLITUDE BALANCE VARIATION vs

TEMPERATURE

100mV/DIV.

1.4V

1.0V

85
25

-40

100

o
o

o

RSSI DC LEVEL

0.5V

-100

-80

INPUT POWER (dBm INTO 50Ω)

-60

-40

VCC = 3V

-20

0

RSSI DC LEVEL

0.6V

2.5
V

4.0

CC

IF INPUT = -50dBM

FIGURE 9. DEMOD RSSI DC LEVEL vs INPUT POWER FIGURE 10. DEMOD RSSI DC LEVEL vs VCC AND

TEMPERATURE

100mV/DIV.

900mV

500mV

DC OFFSET

100mV

2.5

4.0

V

CC

5.5

-40

o

85

o

25

o

5.5

FIGURE 11. DEMODULATOR RSSI DC OFFSET vs VCC AND TEMPERATURE

12

HFA3724

Typical Performance Curves, Modulator (See Figure 23 Test Diagram)

10mA/DIV.

90mA

SUPPLY CURRENT

10mA

85
25

-40

o
o
o

10dB/DIV.

-7dBm

2.5
V

4.0

CC

FIGURE 12. MODULATOR SUPPLYCURRENT vs V

CC

5.5

AND

TEMPERATURE

0.5dB/DIV.

-4

85

25

-40

OUTPUT POWER (dBm AT 50Ω)

-9

2.5

4.0

V

CC

5.5

FIGURE 14. MODULATORSSB OUTPUT POWER vs VCCAND

TEMPERATURE

BW = 100kHz
VBW = 30kHz

274MHz

FREQUENCY

286MHz280MHz

FIGURE 13. TYPICAL SSB MODULA TOR RESPONSE (NOTE3

ON AC ELECTRICAL SPECIFICATIONS,
MODULA TOR PERFORMANCE TABLE, LO
BUFFER ENABLED)

1dB/DIV.

+5dB

o

o
o

0dB

FROM NOMINAL

SIDE BAND SUPPRESSION VARIATION

-5dB

2.5

EXPECTED VARIATION

WINDOW

4.0

V

CC

5.5

FIGURE 15. MODULATOR SSB SIDE BAND SUPPRESSION

VARIATION vs VCC AND TEMPERATURE

1dB/DIV.

+5dB

0dB

FROM NOMINAL

SIDE BAND SUPPRESSION VARIATION

-5dB

2.5

EXPECTED VARIATION

WINDOW

4.0

V

CC

FIGURE 16. MODULATOR LO LEAKAGE VARIATION vs V

AND TEMPERATURE

13

CC

5.5

0.5dB/DIV.

-13

-15.5

LO OUTPUT POWER (dBm AT 50Ω)

-18

2.5

4.0

V

CC

FIGURE 17. MODULATOR LO OUTPUT POWER

(FUNDAMENTAL) vs VCC AND TEMPERATURE

5.5

85

25

-40

o

o

o

HFA3724

Typical Performance Curves, Modulator (See Figure 23 Test Diagram) (Continued)

0dB

-3dB

1dB/DIV.

1MHz 2MHz

10MHz

FIGURE 18. TYPICAL MODULATOR I/Q 3dB CUTOFF

FREQUENCY CURVES

2%/DIV.

+10%

0%

+20%

-20%

PERCENT OF NOMINAL FREQUENCY

-30

-25 -20 -15

-10 -5 0 +5 +10 +15

[(787-R

TUNE

)/R

TUNE

]* 100%

FIGURE 19. LPF CUTOFF FREQUENCY vs R

TA = 25oC

-24dBm

10dB/DIV.

+20

TUNE,VCC

+25

+30

=3V,

PERCENT OF CUTOFF

-10%

-60

-40

-20 0 20 40 60
TEMPERATURE

80

FIGURE 20. LPF CUTOFF FREQUENCY vs TEMPERATURE

AND VCC (NOTE 4 ON AC ELECTRICAL
SPECIFICATIONS, MODULATOR
PERFORMANCE TABLE)

-24dBm

10dB/DIV.

SPAN 50MHz
BW = 300kHz
VBW = 1kHz

FIGURE 22. TYPICAL MODULATOR SPREAD SPECTRUM OUTPUT WITH R

OF 4.4MHz SETTING FOR ILLUSTRATION PURPOSES ONLY

100

SPAN 50MHz
BW = 300kHz
VBW = 1kHz

280MHz

FIGURE 21. TYPICAL MODULATOR SPREAD SPECTRUM

OUTPUT 11M CHIPS/s, QPSK. R

TUNE

8.8MHz SETTING

280MHz

TO +20%

TUNE

TO 7.7MHz,

14

Test Diagram (280MHz IF)

V

CC

0.1
75

(NOTE 22)

IF_IN

100p

2

56

3

0.1

100p

1

100p

4

100p

TABLE 2. POWER MANAGEMENT

TRANSMIT RECEIVE POWER DOWN

LIM1_PE 0 1 0
LIM2_PE 0 1 0
LPF_RX_PE 0 1 0
MOD_RX_PE 0 1 0
MOD_TX_PE 1 0 0
LPF_TX_PE 1 0 0

(NOTE 23)

PE
74

100p

10nH

77

80

79

8 TO 40p

76

100p

47p

RSSI

100p

560

0.1

100p

0.1

62
63

61

100p

LO_IN

LO_OUT

TX_IF_OUT

V

CC

55

64

100p

HFA3724

PE
54

100p

57

100p

56

60

47p

59

(NOTE 24)

3 TO 10p

47p 220

56

100p

(NOTE 25)

0.1

47nH

1K

V

48

49

44

46

CC

316

42

50

V

CC

0.1

45

43 41

MOD_RX_PE

47

0.001

34

0.001

0.001

36

0.001

1K

0.001

38

0.001

0.001

40

0.001

MOD_TX_PE

3033
29

2835
27

18

19

2637
25

2439
23

V

CC

0.1

9

LPF_TX_PE

0.001

14

0.001

15

16

LPF_SEL1

17

LPF_SEL0

10

4.3K

12

680
(NOTE 26)

0.1

11

680

(NOTE 26)

13

4.3K

2122

LPF_RX_PE

RXI_OUT

HI_Z_PROBE

RXQ_OUT

HI_Z_PROBE

2V REF

0.1

TXI

50

TXQ

50

NOTES:

22. Input termination used to provide a 50Ω impedance. Limiter Noise Figure ≅ 9dB for this configuration.

23. Bandpass filter for 280MHz, BW = 47MHz, Q = 6.

24. Network shown for a typical -10dBm input at 50Ω.

25. Matching network from 250Ω to 50Ω at 280MHz.

26. Attenuator is optional if TTL driver can drive 50Ω.

FIGURE 23. TEST DIAGRAM (280MHz IF)

15

HFA3724

Overall Device Description

The HFA3724 is a highly integrated baseband converter for
half duplex wireless data applications. It features all the
necessary blocks for baseband modulation and
demodulation of “I” and “Q” quadrature multiplexing signals.
It targets applications using all phase shift types of
modulation (PSK) due to its hard limiting receiving front end.
Four fully independent blocks adds flexibility for numerous
applications covering a wide range of IF frequencies. A
differential design architecture, device pin out and layout
have been chosen to improve system RF properties like
common mode signal immunity (noise, crosstalk), reduce
relevant parasitics and settling times and optimize dynamic
range for low power requirements. Single power supply
requirements from 2.7V
good choice for portable transceiver designs.

The HFA3724has a two stage integrated limiting IF amplifier
with frequency response to 400MHz. These amplifiers
exhibit a -84dbm, -3db cascaded limiting sensitivity with a
built in Receive Signal Strength Indicator (RSSI) covering
60db of dynamic range with excellent linearity. An up
conversion and down conversion pair of quadrature doubly
balanced mixers are available for “I” and “Q” baseband IF
processing. These converters are driven by an internal
quadrature LO generator which exhibits a broadband
response with excellent quadrature properties. To achieve
broadband operation, the Local Oscillator frequency input is
required to be twice the desired frequency for
modulation/demodulation. Duty cycle and signal purity
requirements for the 2X LO input using this type of
quadrature architecture are less restrictive for the HFA3724.
Ground reference input signals as low as -15dBm and
frequencies up to 900MHz (2XLO) can be used and tailored
by the user. A buffered, divide by 2, LO single ended 50Ω
selectable output is provided for convenience of PLL
designs. The receive channel mixers “I” and “Q” quadrature
outputs have a frequency response up to 30MHz for
baseband signals and the transmit mixers are summed and
amplified to a single ended open collector output with
frequency response up to 400MHz.

Multiplexed or half duplex baseband 5th order Butterworth
low pass filters are also included in the design. The “I” and
“Q” filters address applications requiring low pass and
antialiasing filtering for external baseband threshold
comparison or simple analog to digital conversion in the
receive channel. During transmission, the filter is used for
pulse shaping or control of spectral mask.

Four filter bandwidths are programmable , (2.2MHz, 4.4MHz,

8.8MHz and 17.6MHz) via a two bit digital or hardwired control
interface. These cut off frequencies are selected f or
optimization of spectrum output responses for 2.25M, 5.5M,
11M and 22M chips/sec respectively for spread spectrum
applications (These rates can also be interpreted as symbol
rates for conv entional data tr ansmission). External processing

to 5.5VDC makes the HFA3724 a

DC

correlators in the receive channel as in the Intersil HSP3824
baseband converter, will bring the demodulation to lower
effective data rates . As an e xample , the use of 11M chips/sec ,
11 chip Barker code using the 8.8MHz lowpass filter in a QPSK
type of modulation scheme will bring a post processed effective
data rate to 1M symbol/sec or 2M bits/sec. Likewise, the use of
a 2.4M chips/sec, 16 chip spreading code and the use of

2.2MHz filter can process an effective data rate of 150K
symbols/sec or 300K bits/sec. In addition, these filters are
continuously tunable over a±20% frequency range via one
external resistor. This f eature giv es the user the ability to
reshape the spectrum of a transmitted signal at the antenna
port which takes into account any spectral regrowth along the
transmitter chain. The modulator “I” and “Q” filter inputs accept
digital signal levels data f or modulation and their phase and
gain characteristics, including I / Q matching and group delay
are well suitable for reliab le data transmission. In the Receive
mode and over the full input limiting dynamic range, both lo w
pass filters outputs swing a 500mV

Each block has its own independent power enable control for
power management and half duplex transmit/receive
operation. A stable 2V DC output and a buffered band gap
reference voltage are also provided for an external analog to
digital conversion reference.

baseband signal.

P-P

Detailed Description

(Refer to Block Diagram)

IF Limiter

Two independent limiting amplifiers are available in the
HFA3724. Each one exhibits a broadband response to
400MHz with 45dB of gain. The low frequency response is
limited by external components because the device has no
internal coupling capacitors. The differential limiting output
swing with a 500Ω load is typically 200mV
fundamental frequency and is temperature stable.

Both amplifiers are very stable within their passband and the
cascaded performance also exhibits very good stability for
any input source impedance. Wide bandwidth SAW filters for
spread spectrum applications or any desired source
impedance filter implementation can be used for IF filtering
before the cascaded amplifiers. The stability is remarkable
for such an integrated solution. In fact, in many applications
it is possible to remove the bypass pin capacitors with no
degradation in stability. The cascaded -1dB and -3dB input
limiting sensitivity have been characterized as -79dbm and
84dbm respectively, for a 50Ω single ended input at 280MHz
and with a 47MHz bandwidth interstage bandpass LC filter
(refer to Figure 23, Test Diagram). The input sensitivity is
determined to a large extent by the bandwidth of the
interstage filter and input source impedance.

The noise figure for each stage has been characterized at
6dB for a 250Ω single end input impedance and 9dB for a
50Ω input impedance. These low noise figures combined

P-P

at the

16

HFA3724

with their high gain, eliminate the need for additional IF gain
components. The use of interstage bandpass filtering is
suggested to decrease the noise bandwidth of the signal
driving the second stage. Excessive broadband noise
energy amplified by the first stage will force the last limiting
stage to lose some of its effective gain or “limit on the noise”.
The use of interstage filters with narrower bandwidths will
further improve the sensitivity of the cascaded limiter chain.

The amplifier differential output impedance is 140Ω (70Ω
single ended) which gives the user, the ability to design
simple wide or narrow LC bandwidth interstage filters, or
tailor a desired cascaded gain by using differential
attenuators. The filter can be designed with a desired “Q” by
using the followIng relationship: Q = Rp/X; where Rp is the
parallel combination of 140Ω source resistance and the load
(approximately 500Ω when using 560Ω termination as in
Figure 23, Test Diagram), and X is the reactance of either L
or C at the desired center frequency.

Another independent feature of the limiting amplifier is its
Receive Signal Strength Indicator (RSSI). A Log-Amp
design was developed which resulted in a current output
proportional to the input power. The RSSI output voltage is
set by summing the two stages output currents, which are
full wave rectified signals, to a common resistor to ground.
This full wave rectified voltage can then be converted to DC
by the use of a filter capacitor in parallel with the resistor
(The larger the capacitor value, the less the AC ripple with
the expense of longer RSSI settling times). This
arrangement gives the user the flexibility to set the dynamic
voltage swing to any desired level by an appropriate
resistance choice. Each stage has an availableon chip 6KΩ
low temperature coefficient resistor to ground for current
output termination that can be used for convenience. The
RSSI gives a ±3dBm accurate indication of the receive input
power. This accuracy is across a 60dB input dynamic range.
The cascaded HFA3724 RSSI slope is of 5.0µA/dB.

Quadrature Down Converter

The quadrature down converter mixers are based in a Gilbert
cell design. The input signal is routed to both mixers in parallel.
With full balanced differential architecture, these mix ers are
driven by an accurate internal Local Oscillator (LO) chain as
described later. Phase and gain accuracy of the output
baseband signals are excellent and are a function of the
combination of LO accuracy, balanced device design and
layout characteristics. Mainly used f or do wn con v ersion, its
input frequency response exceeds 400MHz with a differential
voltage gain of 2.5. With a differential input impedance of 1KΩ,
the input compression point exceeds 2V

, which makes it

P-P

suitable for use with the hard limiting output from the limiter
amplifier chain or any low power external AGC application. The
output frequency response is limited to 30MHz for “I” and “Q”
baseband signals driving a 4KΩ differential load.

The HFA3724 down conversion mixers can generate two
10MHz, 90
filtering, and exhibits ±4

o

apart signals, with the use of proper low pass

o

and ±0.5dB of phase and
amplitude match for a input CW IF signal of 400MHz and a
2XLO input of 780MHz.

LO Quadrature Generator

The In Phase and Quadrature reference signals are
generated by a divide by two chain internal to the device
which drives both the up and down conversion mixers. With
a fully balanced approach, the phase relationship between
the two quadrature signals is within 90
400MHz frequency range. The reference signal input
frequency needs to be twice the desired internal reference
frequency. The ground referenced 2XLO input is current
driven, which makes the input power requirement a function
of external components that can be calculated assuming the
input impedance of 130Ω. A typical input current value of
200µA

is the only requirement for reliable LO

RMS

generation. Figure 24 shows a typical 2XLO input network.

o

±4o for a wide 10 to

47p

220

50Ω

56

FIGURE 24. MOD LO IN (2XLO) EQUIVALENT CIRCUIT

44

I RMS = 200µA

EQUIVALENT

130Ω

17

Divide by two flip flop architectures for LO generation often
require tight control of signal purity or duty cycles. The
HFA3724 has an internal duty cycle compensation scheme
which eases the requirements of tight controlled duty cycles.

In addition, a 50Ω LO buffer is availableto the user for PLL’s
design reference. It substitutes a divide by two prescaler
needed to bring the 2X LO frequency reference down. It is
capable to drive 100mV

into 50Ω and its frequency

P-P

response is from 10MHz to 400MHz corresponding to a
2XLO input frequency response of 20MHz to 800MHz. The
LO buffer can be disabled by removing the ground
connection to the pin LO GND. The quadrature generator is
always enabled for either transmit or receive modes.

HFA3724

Quadrature Up Converter

The Quadrature up converter mixers are also based on a
doubly balanced Gilbert Cell design. “I” and “Q” Up converter
signals are summed and bufferedtogether through a single end
open collector stage. As with the demodulators, both modulator
mixers are driven from the same quadrature LO generator. It
featuresa ±4
400MHz which are reflected into its SSB characteristics. For “I”
and “Q” differential inputs of 500mV
feedthrough or LO leakage is typical -30dBc into 250Ω with a
sideband suppression of minimum 26dBc at 400MHz. Carrier
feedthroughcan be furtherimproved by disabling the LO output
port (please refer to pin#50 description) or using a DC bias
network as in Figure 25. Featuring an output compression level
of 1V
typical -10dbm into 250Ω (158mV
inputs of 500mV
referenced lev els from the DC bias quiescent point of the
device input) are applied to both “I” and “Q” inputs. F our
quadrant phase shifts of the carrier output, like in Vector
Modulator applications, can be set by proper choice of “I” and
“Q” DC differential inputs, such that the square root of the sum
of the squares of I and Q is constant.

Although specified to drive a 250Ω load, the HFA3724
modulator open collector output enables user designed
output matching networks to suit any application interface.
The nominal AC current capability of this port is of

1.3mA
and the load for I and Q differential DC inputs of 500mV
as explained above. (Use 70.7% of this AC capability for I
and Q quadrature signals in case of SSB generation).

o

and 0.5dB of phase and amplitude balance up to

, 90o apart, the carrier

P-P

, the modulator output can generate a CW signal of

P-P

(equivalent to applying ±125mV ground

P-P

, which is shared between the termination resistor

RMS

) when differential DC

RMS

P-P

Programmable Low Pass Filters

These filters are implemented using a 5th order Butterworth
architecture. They are multiplexed, i.e., the same filter bank
is used for both transmit and receive modes.

The filter block, in the transmit mode is set to accept digital
(TTL threshold) input data for “I” and “Q” signals and is
programmable with 4 frequency cutoffs: (2.2MHz, 4.4MHz,

8.8MHz and 17.8MHz). Digital control pins are used to
switch all programmed cutoff modes. The user can design a
multi data rate transceiver or simply hardwire these inputs.
An external resistor is used to fine tune the cut off
frequencies for each setting within ±20% of the nominal
value. This feature is often needed to fulfill requirements of
spectral mask compliance at the antenna output.

The “I” and “Q” filter matching is within 2

o

for phase and

0.25dB for amplitude at the passband. Group delay
characteristics follow closely a theoretical 5th order
Butterworth design.

When in the receive mode, the filters exhibit a 0dB of gain
with differential inputs and single ended outputs.

In the transmit mode, the digital ground referenced “I” and
“Q” input signals are level shifted, shaped and buffered with
constant driving differential outputs of 550mV

P-P

.

Baseband Digital Interfacing

Special precautions must be taken when interfacing the
HF A3724 to a digital baseband processor: Large TTL signal
swings, overshoots and current spikes, must be carefully
considered when dealing with the generation of analog
spread spectrum signals which are relatively much smaller in
energy per bandwidth.

MOD_TXQ -

MOD_TXQ +

MOD_TXI -

MOD_TXI +

3837

1K1K

50K

43K

FIGURE 25. CARRIER NULL BIASING

4039

1K

50K

43K

18

In order to avoid distortion or spurious tones on the analog
transmit path, it may be necessary to decrease and/or limit
digital excursions as much as possible without
compromising the specifications. Figure 26 shows a
simplified block diagram of the Transmit digital inputs.

1K

V

IH

TXI

TXQ

LPF_TXI_IN

R1

4.3K

V

IL

V

IH

V

IL

0.1

R1

4.3K

680
R2

LPF_BYP

1.25V
R2

680

LPF TXQ_IN

COMPARATOR

12

11

COMPARATOR

13

1.25V

LEVEL

SHIFTER

LEVEL

SHIFTER

FROM BAND GAP

TO

I FILTER

TO

Q FILTER

FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE

TRANSMIT DIGITAL INPUTS

Because of the input comparators high gain, a small
overdriveof about ±150mV from the reference level of 1.25V
is all what is needed to reliably switch and level shift the “I”
and “Q” digital signals. An external attenuator comprising of
R1 and R2 with termination in the available 1.25V reference
voltage pin (LPF BYP) can be calculated based on expected
V

and VIL inputs from a digital interface. Capacitive

IH

coupling must be avoided which could affect rise and fall
times needed for proper overdrivespeed of the comparators.
Limiting the digital excursion on those pins greatly reduce
the possibility of signal corruption at the transmit chain.

HFA3724

Coupling Capacitors

Capacitor coupling is used to tie all HF A3724blocks together.
Special bias is used to maintain the DC levelson both ends of
coupling pins (capacitors) when the device is changes from
Transmitter to a Receiver and vice versa. The capacitance
values must be chosen as a compromise to maintain proper
frequency response and settling times (when the device is
brought up from sleep mode or power down).

19

HFA3724

AC Electrical Specifications, IF Limiter, Single Stage Individual Performance Full Supply Range, T

= 25oC

A

(NOTE 27)

PARAMETER SYMBOL

TEST LEVEL MIN TYP MAX UNITS

IF Frequency Range (Min Limited by Bypass Capacitors) IFf A - - 400 MHz
IF Voltage Gain IFvG A 39 45 - dB
IF Amp. Noise Figure at 250Ω Source Input IFNF B - - 7 dB
Maximum IF Input, Single Ended IFinmax B - - 500 mV
IF Differential Limiting Output (1st Harmonic at 500Ω Load) IFVpp A 160 200 260 mV
IF Voltage Output Variation at -40dBm to -10dBm Input Range,

IFVppI A -0.5 - +0.5 dB

500Ω Load
RSSI Slope, Current Output IFRSSIsi B 5.7 - µA/dB
RSSI Slope, Voltage Output at 6K Load IFRSSIv A 25 34 45 mV/dB
RSSI Output Voltage Compliance IFRSSIvc B - - VCC-0.7 V
RSSI DC Offset and Noise Induced Voltage at 6K Load IFRSSIof A 200 400 600 mV
RSSI Absolute Accuracy, VIN = -40dBm IFRSSIa A -10 - +10 %
RSSI Rise and Fall Time at 50pF Load (-20dBm to -40dBm

IFRSSIt B - - 1 µs

Input)

NOTE:

27. A = Production Tested, B = Based on Characterization, C = By Design

P-P
P-P

TABLE 3. IF LIMITER S11, S22 PARAMETER

FREQUENCY S11 (SINGLE ENDED) S22 (DIFFERENTIAL)

50MHz 0.96 -4.0
100MHz 0.95 -8.0
200MHz 0.91 -17.0
300MHz 0.84 -26.0
400MHz 0.80 -33.0

o
o

o
o
o

0.45 0.0

0.45 3.0

0.47 7.0

0.50 9.0

0.53 10.0

AC Electrical Specifications, I/Q Down Converter Individual Performance Full Supply Range, T

= 25oC

A

o
o
o
o

o

(NOTE 28)

PARAMETER SYMBOL

TEST LEVEL MIN TYP MAX UNITS

Quadrature Demodulator Input Frequency Range QDf B 10 - 400 MHz
Demodulator Baseband I/Q Frequency Range QDIQf C - - 30 MHz
Demodulator Voltage Gain at Frequency Range QDg A 6 8 9 dB
Demodulator Differential Input Resistance Drin C - 1 - kΩ
Demodulator Differential Input Capacitance Dcin C - 0.5 - pF
Demodulator Differential Output Level at 4K Load,

Input = 200mV

P-P

QDdo A 400 500 560 mV

P-P

Demodulator Amplitude Balance QDab A -0.5 - 0.5 dB
Demodulator Phase Balance at 200MHz QDpb A -1.85 - 1.85 Degrees
Demodulator Phase Balance at 400MHz QDPb1 B -4 - 4 Degrees
Demodulator Output Compression Voltage at 4K Load QDoc B - 1.25 - V

P-P

NOTE:

28. A = Production Tested, B = Based on Characterization, C = By Design

20

HFA3724

AC Electrical Specifications, I/Q Up Converter and LO Individual Performance Full Supply Range, T

= 25oC

A

(NOTE 29)

PARAMETER SYMBOL

TEST LEVEL MIN TYP MAX UNITS

2XLO Input Frequency Range (2 X Input Range) LOinf B 20 - 800 MHz
2XLO Input Current Range LOinz C 50 200 300 µA

RMS

2XLO Input Impedance LOz C - 130 - Ω
Buffered LO Output Voltage, Single Ended BLOout A 80 100 - mV

P-P

Buffered LO Output Impedance BLOoutZ C - 50 - Ω
Quadrature IF Modulator Output Frequency Range QMLOf B 10 - 400 MHz
IF Modulator I/Q Input Frequency Range QMIQf C - - 30 MHz
IF Modulator Differential I/Q Max Input Voltage QMdi C - 2.25 - V

P-P

IF Modulator Differential I/Q Input Impedance QMIQdz C - 4 - kΩ
IF Modulator Differential Input Capacitance Mcin C - 0.5 - pF
IF Modulator I/Q Amplitude Balance QMIQac A -0.5 - 0.5 dB
IF Modulator I/Q Phase Balance at 200MHz QMIQpac A -2 - 2 Degrees
IF Modulator I/Q Phase Balance at 400MHz QMIQp1 B -4 - 4 Degrees
IF Modulator Output at SSB Into 50Ω, I and Q, 500mV

P-P

QMIFo A -22 - -10.0 dBm
IF Modulator Carrier Suppression (LO Buffer Enabled) QMCs A 28 30 - dBc
IF Modulator Carrier Suppression (LO Buffer Disabled) QMCs1 A 28 36 - dBc
IF Modulator SSB Sideband Suppression at 200MHz QMSSBs A 28 - - dBc
IF Modulator SSB Sideband Suppression at 400MHz QMSSBs B 26 - - dBc
IF Output Level Compression Point QMIFP1 C - 1.0 - V

P-P

IF Modulator Intermodulation Suppression QMIMsup B 26 - - dBc

NOTE:

29. A = Production Tested, B = Based on Characterization, C = By Design

TABLE 4. QUADRATURE MODULATOR S22 PARAMETER

FREQUENCY S22

50MHz 0.99 -2.8
100MHz 0.98 -6.5
200MHz 0.96 -12.3
300MHz 0.87 -25.1
400MHz 0.82 -30.8

AC Electrical Specifications, TX Buffer Individual Performance Full Supply Range, T

o
o

o
o
o

= 25oC

A

(NOTE 30)

PARAMETER SYMBOL

TEST LEVEL MIN TYP MAX UNITS

TX LPF Buffer Serial Data Rate TXBrat A - 11 22 MBPS
TX LPF Buffer Digital Input Impedance LPFDz C 10 12.5 - kΩ

NOTE:

30. A = Production Tested, B = Based on Characterization, C = By Design

21

HFA3724

AC Electrical Specifications, RX/TX 5TH Order LPF Individual Performance Full Supply Range, T

(NOTE 31)

PARAMETER SYMBOL

TX/RX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 0 LPF3db0 A 1.8 2.20 2.4 MHz
TX/RX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 0 LPF3db1 A 3.6 4.40 4.8 MHz
TX/RX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 1 LPF3db2 A 7.4 8.80 9.6 MHz
TX/RX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 1 LPF3db3 A 14.8 17.60 19.2 MHz
TX/RX LPF Sel0, Sel1 Tuning Speed LPFsp B - - 1 µs
TX/RX LPF 3dB Bandwidth Tuning LPFtu A -20 - +20 %
LPF Tune Nominal Resistance LPFTr B - 787 - Ω
RX LPF Voltage Gain LPFg A -1.0 0 1.0 dB
RX LPF Single Ended Output Voltage Swing at 2kΩ Load LPFRXar B - 500 - mV
RX LPF Differential Input Impedance LPFRXzi A 4 5 - kΩ
TX LPF Differential Digital Output Voltage Swing at 4kΩ Load LPFTXo A 450 550 670 mV
TX/RX I/Q Channel Amplitude Match LPFIQm A -0.5 - 0.5 dB
TX/RX I/Q Channel Phase Match LPFIQpm A -3 - 3 Degrees
TX/RX LPF Total Harmonic Distortion LPFTHD B - 3 - %

NOTE:

31. A = Production Tested, B = Based on Characterization, C = By Design

TEST LEVEL MIN TYP MAX UNITS

= 25oC

A

P-P

P-P

TABLE 5. LOW PASS FILTER PROGRAMMING AND TUNING INFORMATION

f

MODE LPF SEL1 LPF SEL0

BW0 0 0 2.2MHz
BW1 0 1 4.4MHz
BW2 1 0 8.8MHz
BW3 1 1 17.6MHz

∗

f

TUNED

3dB

f

3dBNOMINAL

--------------------------------------------------- -=

R

787

TUNE

3dB

(NOMINAL R

TUNE

)

22

HFA3724

TYPICAL f3dB vs R

+20%

-20%

PERCENT OF NOMINAL FREQUENCY

-30

-25 -20 -15

-10 -5 0 +5 +10 +15

[(787 - R

TUNE

FREQUENCY R

)/R

TUNE

TUNE

]* 100%

TUNE

20% Low 984Ω
Nominal 787Ω
20% High 656Ω

FIGURE 27.

+20

+25

+30

Typical Performance Curves, Individual Blocks

1dB/DIV.

5.5V

45dB

o

85

o

25

2.7V

40dB

10M 100M 500MHz

FIGURE 28. SINGLE STAGELIMITER GAIN vs FREQUENCY

AND TEMPERATURE, VCC = 2.7V, 5.5V

-40

85
25

-40

o

o
o
o

0.25dB/DIV.
7dB

6dB

5dB

2.5V

4V

V

CC

FIGURE 29. SINGLE STA GELIMITER NOISE FIGURE vs V

AND TEMPERA TURE, RS = 250Ω, FREQUENCY
= 300MHz

5.5V

CC

85

-40

o

o

25

o

23

HFA3724

Thin Plastic Quad Flatpack Packages (LQFP)

E

E1

GAGE

PLANE

0o-7

D

D1

-D-

Q80.14x14 (JEDEC MS-026BEC ISSUE C)

80 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE

SYM-

BOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.062 - 1.60 ­A1 0.002 0.005 0.05 0.15 ­A2 0.054 0.057 1.35 1.45 -

-A-

-B-

b 0.009 0.014 0.22 0.38 6

b1 0.009 0.012 0.22 0.33 -

D 0.626 0.634 15.90 16.10 3

D1 0.547 0.555 13.90 14.10 4, 5

E 0.626 0.634 15.90 16.10 3

e

PIN 1

E1 0.547 0.555 13.90 14.10 4, 5

L 0.018 0.029 0.45 0.75 -

N80 807

e 0.026 BSC 0.65 BSC -

-H-

SEATING

A

-C-

PLANE

0.08

0.003

NOTES:

1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.

2. All dimensions and tolerances per ANSI Y14.5M-1982.

3. Dimensions D and E to be determined at seating plane .

0.13

0.005

o

0.020
MIN

0.008

0o MIN

L

0.25

o

0.010

11o-13

11o-13

A2

A1

o

C

M

0.09/0.16

0.004/0.006

BASE METAL

WITH PLATING

A-B

D

S

b

b1

0.09/0.20

0.004/0.008

S

4. Dimensions D1 and E1 to be determined at datum plane
.

-H-

5. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is 0.25mm (0.010 inch) per side.

6. Dimension b does not include dambar protrusion. Allowable

dambar protrusion shall not cause the lead width to exceed
themaximum b dimension bymore than 0.08mm (0.003 inch).

7. “N” is the number of terminal positions.

Rev. 2 4/99

-C-

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reservesthe right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

24

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]