Intersil Corporation HFA3724 Datasheet

HFA3724

Data Sheet November 1999 File Number 4067.7

400MHz Quadrature IF
Modulator/Demodulator

™

The Intersil 2.4GHz PRISM™ chip set is a
highly integrated five-chip solution for RF
modems employing Direct Sequence
Spread Spectrum (DSSS) signaling. The

HF A3724 400MHz Quadrature IF
Modulator/Demodulator is one of the five chips in the PRISM™
chip set (see the Typical Application Diagram).

The HF A3724 is a highly integr ated baseband con v erter for
quadrature modulation applications. It features all the necessary
blocks for baseband modulation and demodulation of I and Q
signals. It has a two stage integrated limiting IF amplifier with 84db
of gain with a built in Receive Signal Strength Indicator (RSSI).
Baseband antialiasing and shaping filters are integrated in the
design. Four filter bandwidths are programmable via a tw o bit
digital control interface. In addition, these filters are continuously
tunableovera±20%frequencyrangeviaoneexternalresistor .The
modulator channel receives digital I and Q data for processing. To
achieve broadband operation, the Local Oscillator frequency input
is required to be twice the desired frequency of
modulation/demodulation. A selectable buffered divide b y 2 LO
output and a stable reference voltage are provided for convenience
of the user. The de vice is housed in a thin 80 lead TQFP pac kage
well suited for PCMCIA board applications.

Ordering Information

TEMP. RANGE

PART NUMBER

HFA3724IN -40 to 85 80 Ld TQFP Q80.14x14
HFA3724IN96 -40 to 85 Tape and Reel

(oC) PACKAGE PKG. NO.

Features

• Integrates all IF Transmit and Receive Functions

• Broad Frequency Range . . . . . . . . . . .10MHz to 400MHz

• I/Q Amplitude and Phase Balance . . . . . . . . . . . 0.2dB, 2

• 5th Order Programmable

Low Pass Filter. . . . . . . . . . . . . . . . . . .2.2MHz - 17.6MHz

• 400MHz Limiting IF Gain Strip with RSSI. . . . . . . . . .84dB

• Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm

• Fast Transmit-Receive Switching . . . . . . . . . . . . . . . . .1µs

• Power Management/Standby Mode

• Single Supply 2.7V to 5.5V Operation

Applications

• Systems Targeting IEEE 802.11 Standard

• TDD Quadrature-Modulated Communication Systems

• Wireless Local Area Networks

• PCMCIA Wireless Transceivers

• ISM Systems

• TDMA Packet Protocol Radios

• PCS/Wireless PBX

• Wireless Local Loop

o

Simplified Block Diagram

LIM1_IN

MOD_LO_IN

MOD_LO_OUT

LO_GND

MOD_TX_IF_OUT

1

RSSI1
RSSI2

LIM1_OUT

LIM2_IN

LIM2_OUT

MOD_IF_IN

IFIF

÷2

∑

2V

REF

2V REF

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

MOD_RX_I

MOD_RX_Q

LPF_RX_Q

M

o

0o/90

U
X

LPF_TX_I

MOD_TX_I

MOD_TX_Q

1-888-INTERSIL or 321-724-7143

LPF_RX_I

I

Q

LPF_TX_Q

LPF_TUNE_1

LPF_SEL0

LPF_SEL1

LPF_TUNE_0

M
U
X

LPF_RXI_OUT

LPF_RXQ _OUT

LPF_TXI_IN

LPF_TXQ_IN

| Copyright © Intersil Corporation 1999

Pinout

LIM1_RSSI

RSSI_RL1

GND

LIM1_OUT+

80 LEAD TQFP

LIM1_OUT-

LIM1_VCCLIM1_PE

HFA3724

TOP VIEW

GND

GND

GND

GND

GND

GND

GND

GND

GND

LIM2_BYP-

LIM2_IN-

LIM2_IN+

LIM2_BYP+

LIM1_BYP+

LIM1_IN+

LIM1_IN-

LIM1_BYP-

GND
GND
GND

GND

LPF_V

CC

2V REF

LPF_BYP

LPF_TXI_IN

LPF_TXQ_IN

LPF_RXI_OUT

LPF_RXQ_OUT

LPF_SEL1

LPF_SEL0
LPF_TUNE1
LPF_TUNE0

GND

80

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

2122 23 24 2526 27 28 2930 31 32 3334 35 36

GND

GND

LPF_TXI+

LPF_RXQ-

LPF_RXQ+

LPF_RXI-

LPF_RXI+

LPF_TXQ-

LPF_TXQ+

LPF_TX_PE

LPF_RX_PE

LPF_TXI-

MOD_RXI-

MOD_RXI+

MOD_RXQ-

MOD_RXQ+

64656667686970717273747576777879

6362 61

3738 39 40

MOD_TXI-

MOD_TXI+

MOD_TXQ+

LIM2_RSSI

60

RSSI_RL2

59

GND

58

LIM2_OUT+

57

LIM2_OUT-

56

LIM2_V

55
54

LIM2_PE

53

GND

52

GND

51

GND
LO_GND

50
49

MOD_IF_IN-

48

MOD IF_IN+

47

MOD_V

46

MOD_LO_OUT

45

MOD_V

44

MOD_LO_IN
MOD_RX_PE

43

MOD_TX_IF_OUT

42
41

MOD_TX_PE

MOD_TXQ-

CC

CC

CC

2

Block Diagram

HFA3724

LPF_TUNE0

LPF_TUNE1

LPF_RX PE

LPF_RX I -

LPF_RX I +

LPF_RX Q +

LPF_RX Q -

MOD_RX Q -

MOD_RX Q +

MOD_RX I -

MOD_RX I +

MOD_RX PE

MOD_IF_IN +

MOD_IF_IN -

LIM2_OUT -

LIM2_OUT +

LIM2_PE

LIM2_IN+

LIM2_IN-

LIM1_OUT -

LIM1_OUT +

LIM1_PE

LPF_SEL1
LPF_SEL0

DOWN CONV

LPF_RXI_OUT

IF

IF

LPF_RXQ_OUT

I

IF LIMITERS

MUX

MUX

o

/90

o

0

÷2

LPF_TXI_IN

Q

UP CONVERTER

LPF_TXQ_IN

∑

2V

REF

MUX_LPF

LPF_TX_PE

LPF_TX_Q ­LPF_TX_Q +

LPF_TX_I ­LPF_TX_I +

MOD TX I +
MOD TX I -

MOD TX Q +
MOD TX Q -

MOD_TX_PE

2V REF

LIM1_IN+

SAW

IF

LIM1_IN-

LIM1_RSSI

IN

NOTE: VCC, GND and Bypass capacitors not shown.

3

RSSI_RL1

RSSI_RL2

LIM2_RSSI

RSSI

LO_GND

(2XLO)

MOD_LO_IN

CC

V

50Ω

MOD_LO_OUT

IF_OUT

MOD_TX

LPF_BYP

1.25V

Typical Application Diagram

HFA3724

HFA3724

(FILE# 4067)

HF A3424 (NOTE)

(FILE# 4131)

HF A3624

RF/IF

CONVERTER

(FILE# 4066)

RFPA

HF A3925

VCO

VCO

(FILE# 4132)

DUAL SYNTHESIZER

HFA3524

(FILE# 4062)

TYPICAL TRANSCEIVER APPLICATION USING THE HFA3724

NOTE: Required for systems targeting 802.11 specifications.

For additional information on the PRISM™ chip set, call
[phone] to access Intersil’ AnswerFAX system. When
prompted, key in the four-digit document number (File #) of
the datasheets you wish to receive.

÷2

0o/90

QUAD IF MODULATOR

TUNE/SELECT

I

M

o

U

X

Q

HSP3824

(FILE# 4064)

RXI

RXQ

RSSI

M
U
X

A/D

DE-

SPREAD

A/D

CCA

A/D

TXI

SPREAD

TXQ

DSSS BASEBAND PROCESSOR

PRISM™ CHIP SET FILE #4063

DPSK

DEMOD

802.11

MAC-PHY

INTERFACE

DPSK

MOD.

DATA TO MACCTRL

The four-digit file numbers are shown in Typical Application
Diagram, and correspond to the appropriate circuit.

4

HFA3724

Typical Application Diagram (Targeting IEEE 802.11 Standard)

RF/IFIF/RF

HFA3624IA

CONVERTER

TOYOCOM

TQS 432

(NOTE 1)

100p

56n

0.1

V

0.1

2

260

3

1

100p

100p

TOYOCOM

TQS 432

CC

75

4

100p

V

CC

1K

47

(NOTE 4)

NC

V

316

42

50

CC

0.1

45

48

49

44

46

43

47

0.01

34

0.01

0.01

36

0.01

(NOTE 5)

0.01

38

0.01

0.01

40

0.01

V

(NOTE 2)

PE

74

77

76

80

79

VCO

100p

100p

47p

8 TO 40p

100p

10nH

560

0.1

100p

CC

0.1
55

62
63

64

61

100p

100p

LO_IN

(NOTE 6)

TX_IF_OUT

560MHz
VCO (AUXILIARY)

59

PE

54

57

56

60

100p

0.1

47nH

100p

100p

100p

47p

(NOTE 3)

47p 220

56

900

V

CC

0.1

9

3033
29

2835
27

18

19

2637
25

2439
23

RXI_OUT

14

RXQ_OUT

15
20

16

17

10
2V REF

12

680

11
680

13

212241

0.01

0.01

LPF_SEL1

V

CC

LPF_SEL0

0.1

TXI

4.3K

0.1

TXQ

4.3K

RSSI

HSP3824VI

BASEBAND PROCESSOR

DUAL SYNTHESIZER

HFA3524IA

MOD_TX_PE

MOD_RX_PE

LPF_TX_PE

LPF_RX_PE

TYPICAL APPLICATION DIAGRAM (TARGETING IEEE 802.11 STANDARD)

NOTES:

1. Input termination used to match a SAW filter.

2. Typical bandpass filter for 280MHz, BW = 47MHz, Q = 6. Can also be used if desired after the second stage.

3. Network shown for a typical -10dBm input at 50Ω.

4. Output termination used to match a SAW filter.

5. R

value for a 7.7MHz cutoff frequency setting.

TUNE

6. LO buffer output termination is needed only when the buffer is enabled by pin 50 connected to GND, otherwise tie pin 46 to pin 47.

5

HFA3724

Pin Description

PIN SYMBOL DESCRIPTION

1 LIM1_BYP+ DC feedback pin for Limiter amplifier 1. Requires good decoupling and minimum wire length to a solid signal

ground.
2 LIM1_In+ Non inverting analog input of Limiter amplifier 1.
3 LIM1_In- Inverting input of Limiter amplifier 1.
4 LIM1_BYP- DC feedback pin for Limiter amplifier 1. Requires good decoupling and minimum wire length to a solid signal

ground.

5, 6,

7, 8

9 LPF_V

10 2V REF Stable 2V reference voltage output for external applications. Loading must be higher than 10kΩ. A bypass

11 LPF_BYP Internal reference bypass pin. This is the common voltage (VCM) used for the LPF digital thresholds. Requires

12 LPF_TXI_In Low pass filter in phase (I) channel transmit input. Conventionalor attenuated direct coupling is required for digital

13 LPF_TXQ_In Low pass filter quadrature (Q) channel transmit input. Conventional or attenuated direct coupling is required for

14 LPF_RXI_Out Low pass filter in phase (I) channel receive output. Requires AC coupling. (Note 8)
15 LPF_RXQ_Out Low pass filter quadrature (Q) channel receive output. Requires AC coupling. (Note 8)
16 LPF_Sel1 Digitalcontrol input pins. Selects fourprogramed cut off frequencies for both receive and transmit channels. Tuning
17 LPF_Sel0

18 LPF_Tune1 These two pins are used to fine tune the Low pass filter cutoff frequency. A resistor connected between the two
19 LPF_Tune0

20 GND Ground. Connect to a solid ground plane.
21 LPF_RX_PE Digital input control pin to enable the LPF receive mode of operation. Enable logic level is High.
22 LPF_TX_PE Digital input control pin to enable the LPF transmit mode of operation. Enable logic level is High.
23 LPF_TXQ- Negativeoutput of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to

24 LPF_TXQ+ Positive output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to

25 LPF_TXI- Negative output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to

26 LPF_TXI+ Positiveoutput of the transmit Low pass filter,in phase channel. AC coupling is required. Normally connects to the

27 LPF_RXQ- Low pass filter inverting input of the receive quadrature channel. AC coupling is required. This input is normally

28 LPF_RXQ+ Lowpass filternon inverting input of the receive quadrature channel. ACcoupling is required. Thisinput is normally

29 LPF_RXI- Low pass filter inverting input of the receive in phase channel. AC coupling is required. This input is normally

30 LPF_RXI+ Low pass filter non inverting input of the receive in phase channel. AC coupling is required. This input is normally

31, 32 GND Ground. Connect to a solid ground plane.

GND Ground. Connect to a solid ground plane.

CC

Supply pin for the Low pass filter. Use high quality decoupling capacitors right at the pin.

capacitor of at least 0.1µF is required.

0.1µF decoupling capacitor.

inputs. (Note 7)

digital inputs. (Note 7)

speed from one cutoff to another is less than 1µs.

SEL1 SEL0 Cutoff Frequency SEL1 SEL0 Cutoff Frequency

LO LO 2.2MHz HI LO 8.8MHz

LO HI 4.4MHz HI HI 17.6MHz

pins (R

specifications.

the inverting input of the quadrature Modulator (Mod_TXQ-), pin 40.

the non inverting input of the quadrature Modulator (Mod_TXQ+), pin 39.

the inverting input of the in phase Modulator (Mod_TXI-), pin 38.

non inverting input of the in phase Modulator (Mod_TXI+), pin 37.

coupled to the negative output of the quadrature demodulator (Mod_RXQ-), pin 36.

coupled to the positive output of the quadrature demodulator (Mod_RXQ+), pin 35.

coupled to the negative output of the in phase demodulator (Mod_RXI-), pin 34.

coupled to the positive output of the in phase demodulator (Mod_RXI-), pin 33.

) will fine tune both transmit and receive filters. Refer to the tuning equation in the LPF AC

TUNE

6

HFA3724

Pin Description (Continued)

PIN SYMBOL DESCRIPTION

33 Mod_RXI+ In phase demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the

Low pass filter (LPF_RXI+), pin 30.

34 Mod_RXI- In phase demodulator negativeoutput. AC coupling is required. Normally connects to the inverting input of the Low

pass filter (LPF_RXI-), pin 29.

35 Mod_RXQ+ Quadrature demodulator positive output. AC coupling is required. Normally connects to the non inverting input of

the Low pass filter (LPF_RXQ+), pin 28.

36 Mod_RXQ- Quadrature demodulator negative output. AC coupling is required. Normally connects to the inverting input of the

Low pass filter (LPF_RXQ+), pin 27.

37 Mod_TXI+ In phase modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass

filter positive output (LPF_TXI+), pin 26.

38 Mod_TXI- In phase modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter

negative output (LPF_TXI-), pin 25.

39 Mod_TXQ+ Quadraturemodulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass

filter positive output (LPF_TXQ+), pin 24.

40 Mod_TXQ- Quadrature modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter

negative output (LPF_TXQ-), pin 23.

41 Mod_TX_PE Digital input control to enable the Modulator section. Enable logic level is High for transmit.
42 Mod_TX_IF_Out Modulator open collector output, single ended. Termination resistor to VCC with a typical value of 316Ω.
43 Mod_RX_PE Digital input control to enable the demodulator section. Enable logic level is High for receive.
44 Mod_LO_In

(2XLO)

45 Mod_V
46 Mod_LO_Out Divide by 2 buffered output reference from “Mod_LO_in” input. Used for external applications where the modulating

47 Mod_V
48 Mod_IF_In+ Demodulator non inverting input. Requires AC coupling.
49 Mod_IF In- Demodulator inverting input. Requires AC coupling.
50 LO_GND When grounded, this pin enables the LO buffer (Mod_LO_Out). When open (NC) it disables the LO buffer.

51, 52,

53
54 LIM2_PE Digital input control to enable the limiter amplifier 2. Enable logic level is High.
55 LIM2_V
56 LIM2_Out- Positive output of limiter amplifier 2. Requires AC coupling.
57 LIM2_Out+ Negative output of limiter amplifier 2. Requires AC coupling.
58 GND Ground. Connect to a solid ground plane.
59 RSSI_RL2 Load resistor to ground. Nominal value is 6kΩ. This load is used to terminate the LIM RSSI current output and

60 LIM2_RSSI Current output of RSSI for the limiter amplifier 2. Connect in parallel with the RSSI output of the amplifier limiter 1

61 LIM2_BYP+ DC feedback pin for Limiter amplifier 2. Requires good decoupling and minimum wire length to a solid signal

62 LIM2_In+ Non inverting analog input of Limiter amplifier 2.

CC

CC

GND Ground. Connect to a solid ground plane.

CC

Single ended local oscillator current input. Frequency of input signal must be twice the required modulator carrier

and demodulator LO frequency. Input current is optimum at 200µA

be designed for a wide range of power and impedances at this port. Typical input impedance is 130Ω.This pin

requires AC coupling. (Note 9)

NOTE: High second harmonic content input waveforms may degrade I/Q phase accuracy.

Modulator/Demodulator supply pin. Use high quality decoupling capacitors right at the pin.

and demodulating carrier reference frequency is required. 50Ω single end driving capability.This output can be

disabled by use of pin 50. AC coupling is required, otherwise tie to pin 47 (VCC).

Modulator/Demodulator supply pin. Use high quality decoupling capacitors right at the pin.

Limiter amplifier 2 supply pin. Use high quality decoupling capacitors right at the pin.

maintain temperature and process variation to a minimum.

for cascaded response.

ground.

. Input matching networks and filters can

RMS

7

HFA3724

Pin Description (Continued)

PIN SYMBOL DESCRIPTION

63 LIM2_In- Inverting input of Limiter amplifier 2.
64 LIM2_BYP- DC feedback pin for Limiter amplifier 2. Requires good decoupling and minimum wire length to a solid signal

ground.

65, 66,
67, 68,
69, 70,
71, 72,

73
74 LIM1_PE Digital input control to enable the limiter amplifier 1. Enable logic level is High.
75 LIM1_V
76 LIM1_Out- Negative output of limiter amplifier 1. Requires AC coupling.
77 LIM1_Out+ Positive output of limiter amplifier 1. Requires AC coupling.
78 GND Ground. Connect to a solid ground plane.
79 RSSI_RL1 Load resistor to ground. Nominal value is 6kΩ. This load is used to terminate the LIM RSSI current output and

80 LIM1_RSSI Current output of RSSI for the limiter amplifier 1. Connect in parallel with the RSSI output of the amplifier limiter 2

NOTES:

7. The HFA3724 generates a lower sideband signal when the “I” input leads the “Q” input by 90 degrees.

8. For a reference LO frequency higher than a CW IF signal input, the “I” channel leads the “Q” channel by 90 degrees.

9. The in-phase reference LO transitions occur at the rising edges of the 2XLO clock signal. Quadrature LO transitions occur at the falling edges.
180 degrees phase ambiguity is expected for carrier locked systems without differential encoding.

GND Ground. Connect to a solid ground plane.

CC

Limiter amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin.

maintain temperature and process variation to a minimum.

for cascaded response.

TABLE 1. POWER MANAGEMENT

TRANSMIT RECEIVE POWER DOWN

LIM1_PE 0 1 0
LIM2_PE 0 1 0
LPF_RX_PE 0 1 0
MOD_RX_PE 0 1 0
MOD_TX_PE 1 0 0
LPF_TX_PE 1 0 0

8