Intersil Corporation HFA3524 Datasheet

TM

HFA3524

Data Sheet March 2000

2.5GHz/600MHz Dual Frequency
Synthesizer

The Intersil 2.4GHz PRISM® chip set is
a highly integrated six-chip solution for
RF modems employing Direct
Sequence Spread Spectrum (DSSS)

signaling. The HFA3524 600MHz Dual
Frequency Synthesizer is one of the six chips in the PRISM
chip set (see the Typical Application Diagram).

The HFA3524 is a monolithic, integrated dual frequency
synthesizer, including prescaler, is to be used as a local
oscillator for RF and first IF of a dual conversion transceiver.

The HF A3524 contains a dual modulus prescaler. A 32/33 or
64/65 prescaler can be selected for the RF synthesizer and a
8/9 or a 16/17 prescaler can be selected for the IF
synthesizer. Using a digital phase locked loop technique, the
HF A3524 can gener ate a very stable, low noise signal for the
RF and IF local oscillator. Serial data is transf erred into the
HF A3524 via a three wire interface (Data, Enable, Cloc k).
Supply voltage can range from 2.7V to 5.5V. The HF A3524
features very low current consumption of 13mA at 3V.

File Number 4062.8

Features

• 2.7V to 5.5V Operation

• Low Current Consumption

• Selectable Powerdown Mode I

= 1µA Typical at 3V

CC

• Dual Modulus Prescaler, 32/33 or 64/65

• Selectable Charge Pump High Z State Mode

Applications

• Systems Targeting IEEE 802.11 Standard

• PCMCIA Wireless Transceiver

• Wireless Local Area Network Modems

• TDMA Packet Protocol Radios

• Part 15 Compliant Radio Links

• Portable Battery Powered Equipment

Ordering Information

PART

NUMBER

HFA3524IA -40 to 85 20 Ld TSSOP M20.173
HFA3524IA96 -40 to 85 Tape and Reel

TEMP.

RANGE (oC) PACKAGE PKG. NO.

Functional Block Diagram

fIN IF

OSC

fIN RF

CLOCK

DAT A

LE

IN

IF

PRESCALER

OSC

RF

PRESCALER

15-BIT IF

N COUNTER

15-BIT IF

R COUNTER

15-BIT RF

R COUNTER

18-BIT RF

N COUNTER

22-BIT DATA

REGISTER

PHASE

COMP

PHASE

COMP

LD

RF
LD

CHARGE

PUMP

IF

f

OUT

LOCK
DETECT
FASTLOCK
MUX

CHARGE

PUMP

DO IF

FO/LD

DO RF

1

1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

Typical Application Diagram

HFA3524

HF A3424 (NOTE)

(FILE# 4131)

HF A3624

UP/DOWN

CONVERTER

(FILE# 4066)

RFPA

HF A3925

(FILE# 4132)

HFA3524

NOTE: Required for systems targeting 802.11 specifications.

TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA352

VCO

VCO

DUAL SYNTHESIZER

(FILE# 4062)

HFA3724

(FILE# 4067)

÷2

QUAD IF MODULATOR

0o/90

TUNE/SELECT

I

M

o

U
X

Q

HSP3824

(FILE# 4064)

RXI

RXQ

RSSI

M
U
X

A/D

DE-

SPREAD

A/D

CCA

A/D

TXI

SPREAD

TXQ

DSSS BASEBAND PROCESSOR

PRISM CHIP SET FILE #4063

DPSK

DEMOD

802.11

MAC-PHY

INTERFACE

DPSK

MOD.

DATA TO MACCTRL

For additional information on the PRISM chip set, see us on
the web http://www.intersil.com/prism or call [phone]
to access Intersil’ AnswerFAX system. When prompted, key
in the four-digit document number (File #) of the datasheets
you wish to receive.

The four-digit file numbers are shown in Typical Application
Diagram, and correspond to the appropriate circuit.

2

Pinout

HFA3524

HFA3524 (TSSOP)

TOP VIEW

V

CC1

V

DO RF

GND

f

RF

IN

fIN RF

GND

OSC

GND

/LD

F

O

1
2

P1

3
4
5
6
7
8

IN

9

10

20
19
18
17
16
15
14
13
12
11

V

CC2

V

P2

DO IF
GND
f

IF

IN

fIN IF
GND
LE
DAT A
CLOCK

Pin Descriptions

PIN

NUMBER PIN NAME I/O DESCRIPTION

1V

CC1

2VP1- Power Supply for RF charge pump. Must be > VCC.
3D

RF O Internal charge pump output. For connection to a loop filter for driving the input of an external VCO.

O

4 GND - Ground.
5f

RF I RF prescaler input. Small signal input from the VCO.

IN

6 fIN RF l RF prescaler complimentary input. A bypass capacitor should be placed as close as possible to this

7 GND - Ground.
8 OSC

IN

9 GND - Ground.

10 FO/LD O Multiplexed output of the RF/lF programmable or reference dividers, RF/lF lock detect signals and

11 Clock I High impedance CMOS Clock input. Data for the various counters is clocked in on the rising edge,

12 Data l Binary serial data input. Data entered MSB first. The last two bits are the control bits. High

13 LE l Load enable CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one

14 GND - Ground.
15 fIN IF I IF prescaler complimentary input. A bypass capacitor should be placed as close as possible to

16 fIN IF I IF prescaler input. Small signal input from the VCO.
17 GND - Ground.
18 DO IF O IF charge pump output. For connection to a loop filter for driving the input of an external VCO.
19 V
20 V

P2

CC2

- Power supply voltage input. Input may range from 2.7V to 5.5V. V

must equal V

CC1

capacitors should be placed as close aspossibletothispin and be connected directly to the ground
plane.

pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity.

I Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS

or TTL logic gate.

Fastlock mode. CMOS output (see Programmable Modes).

into the 22-bit shift register.

impedance CMOS input.

of the 4 appropriate latches (control bit dependent).

this pin and be connected directly to the ground plane. Capacitor is optional with some loss of
sensitivity.

- Power Supply for IF charge pump. Must be >VCC.

- Power supply voltage input Input may range from 2.7V to 5.5V. V

must equal V

CC2

capacitors should be placed as close as possible to this pin and be connected directly to the ground
plane.

CC2

CC1

. Bypass

. Bypass

3

Block Diagram

HFA3524

V

CC1

V

DORF

GND

fIN RF
fIN RF

GND

1

2

P1

3

4

5

+

6

-

7

1X 4X

RF CHARGE PUMP

SWALLOW

CONTROL

32/33 OR 64/65

RF PRESCALER

1-BIT RF

PWDN

1-BIT P1

LATCH

RF

LOCK

DETECT

PU

RF

PHASE

PD

DETECTOR

PROGRAMMABLE

18-BIT (RF)

N-COUNTER

(RF) 18-BIT N-LATCH

15-BIT R1 LATCH5-BIT MODE LATCH

LOCK DETECT/

MULTIPLEXER

FR 1
FP 1

/

f

OUT

FASTLOCK

IF

LOCK

DETECT

FR 2
FP 2

(IF) 15-BIT N-LATCH

IF

PHASE

DETECTOR

PROGRAMMABLE

15-BIT (IF)

N-COUNTER

PU

PD

IF PRESCALER

1-BIT P2

LATCH

4X1X

IF CHARGE PUMP

SWALLOW

CONTROL

8/9 OR 16/17

1-BIT IF

PWDN

20

V

CC2

19

V

P2

18

DOIF

17

GND

16

fIN IF

+

15

-

fIN IF

14

GND

OSC

GND

F

O

8

IN

9

10

LD

PROGRAMMABLE 15-BIT

(R1) REFERENCE COUNTER

PROGRAMMABLE 15-BIT

(R2) REFERENCE COUNTER

15-BIT R2 LATCH5-BIT MODE LATCH

NOTES:

1. V

suppliespowerto the RF prescaler,N-counterand phase detector. V

CC1

RF and IF R-counters along with the OSCIN buffer and all digital circuitry. V
same voltage level.

2. VP1 and VP2 can be run independently as long as VP≥ VCC.

LATCH

DECODE

2-BIT

CONTROL

20-BIT SHIFT REGISTER

suppliespowerto the IF prescaler,N-counterand phase detector,

CC2

CC1

and V

are separated by a diode and must be run at the

CC2

LATCH

13

12

11

LE

DAT A

CLOCK

4

HFA3524

Absolute Maximum Ratings Thermal Information

Power Supply Voltage

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

VP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

Voltage on Any Pin with GND = 0V (VI). . . . . . . . . . . -0.3V to +6.5V

Operating Conditions

Power Supply Voltage

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 5.5V

VP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC to +5.5V

Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 3) θJA (oC/W)

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Maximum Storage Temperature Range (TS). . . . . . -55oC to 150oC

Maximum Lead Temperature (Soldering 4s) (TL) . . . . . . . . . .260oC

(TSSOP - Lead Tips Only)

Electrical Specifications V

= 3.0V, VP = 3.0V, -40oC < TA < 85oC, Unless Otherwise Specified

CC

HFA3524

PARAMETER SYMBOL TEST CONDITIONS

Power Supply Current I

CC

UNITSMIN TYP MAX

RF + IF VCC = 2.7V to 5.5V - 13 - mA
RF Only VCC = 2.7V to 5.5V - 10 - mA

Powerdown Current I

CC-PWDNVCC

= 3.0V - 1 25 µA
Operating Frequency fIN RF 0.5 - 2.5 GHz
Operating Frequency fIN IF 45 - 600 MHz
Oscillator Frequency f
Maximum Phase Detector

Frequency

OSC

f

φ

5 - 44 MHz

10 - - MHz

RF Input Sensitivity PfIN RF VCC = 3.0V -15 - +4 dBm

VCC = 5.0V -10 - +4 dBm
IF Input Sensitivity PfIN IF VCC = 2.7V to 5.5V -10 - +4 dBm
Oscillator Sensitivity V
High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current I
Low Level Input Current I
Oscillator Input Current I
Oscillator Input Current I
High Level Output Voltage V
High Level Output Voltage V
Low Level Output Voltage V
Low Level Output Voltage V
Data to Clock Set Up Time t
Data to Clock Hold Time t
Clock Pulse Width High t
Clock Pulse Width Low t
Clock to Load Enable Set Up Time t
Load Enable Pulse Width t

OSC

IH

IL
IH
IL
IH
IL

OH
OH

OL
OL

CS

CH
CWH
CWL

ES

EW

OSC

IN

(Note) 0.8V
(Note) - - 0.2V

0.5 - - V

CC

-- V

CC

VIH = VCC = 5.5V (Note) -1.0 - 1.0 µA
VIL = 0V, VCC = 5.5V (Note) -1.0 - 1.0 µA
VIH = VCC = 5.5V - - 100 µA
VIL = 0V, VCC = 5.5V -100 - - µA
IOH = -500µAV

-0.4 - - V

CC

IOH = -1mA - - - V
IOL = 500µA - - 0.4 V
IOL = 1mA - - - V
See Data Input Timing 50 - - ns
See Data Input Timing 10 - - ns
See Data Input Timing 50 - - ns
See Data Input Timing 50 - - ns
See Data Input Timing 50 - - ns
See Data Input Timing 50 - - ns

NOTE: Clock, Data and LE does not include fIN RF, fIN IF and OSCIN.

P-P

V

5