Intersil Corporation HFA3102 Datasheet
HFA3102
Data Sheet August 1996 File Number 3635.2
Dual Long-Tailed Pair Transistor Array
The HFA3102 is an all NPN transistor array configured as
dual differential amplifiers with tail transistors. Based on
Intersil bonded wafer UHF-1 SOI process, this array
achieves very high f
h
and VBE matching characteristics over temperature.
FE
(10GHz) while maintaining excellent
T
Collector leakage currents are maintained to under 0.01nA.
Ordering Information
TEMP.
PART NUMBER
HFA3102B -40 to 85 14 Ld SOIC M14.15
HFA3102B96 -40 to 85 14 Ld SOIC Tape
RANGE (oC) PACKAGE
and Reel
PKG.
NO.
M14.15
Pinout/Functional Diagram
HFA3102
(SOIC)
TOP VIEW
14 13 12 11 10 9 8
Q
Q
Q
1
2
6
Features
• High Gain-Bandwidth Product (fT) . . . . . . . . . . . . . 10GHz
• High Power Gain-Bandwidth Product. . . . . . . . . . . . 5GHz
• High Current Gain (h
) . . . . . . . . . . . . . . . . . . . . . . . 70
FE
• Noise Figure (Transistor) . . . . . . . . . . . . . . . . . . . . . 3.5dB
• Low Collector Leakage Current . . . . . . . . . . . . . <0.01nA
• Excellent h
and VBE Matching
FE
• Pin-to-Pin to UPA102G
Applications
• Single Balanced Mixers
• Wide Band Amplification Stages
• Differential Amplifiers
• Multipliers
• Automatic Gain Control Circuits
• Frequency Doublers, Tripplers
• Oscillators
• Constant Current Sources
• Wireless Communication Systems
Q
Q
4
Q
3
1234567
5
• Radio and Satellite Communications
• Fiber Optic Signal Processing
• High Performance Instrumentation
3-449
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Copyright © Intersil Corporation 1999
HFA3102
Absolute Maximum Ratings T
V
Collector to Emitter Voltage. . . . . . . . . . . . . . . . . . . . . . . 8.0V
CEO
V
Collector to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . 12.0V
CBO
V
Emitterr to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . . 12.0V
EBO
IC, Collector Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
=25oC Thermal Information
A
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Maximum Power Dissipation at 75oC
Any One Transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.25W
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . .175oC
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications T
= 25oC
A
(NOTE 2)
ALL GRADES
TEST
SYMBOLS PARAMETER TEST CONDITIONS
V
(BR)CBO
Collector-to-Base Breakdown Voltage
IC = 100µA, IE = 0 A 12 18 - V
LEVEL
UNITSMIN TYP MAX
(Q1, Q2, Q4, and Q5)
V
(BR)CEO
Collector-to-Emitter Breakdown
IC = 100µA, IB = 0 A 8 12 - V
Voltage (Q1 thru Q6)
V
(BR)EBO
Emitter-to-Base Breakdown Voltage (Q
IE = 50µA, IC = 0 A 5.5 6 - V
3
and Q6)
I
CBO
I
EBO
h
FE
C
CB
C
EB
f
T
f
MAX
G
NFMIN
NF
MIN
NF
50Ω
h
FE1/hFE2
V
OS
Collector Cutoff Current
VCB = 5V, IE = 0 A - 0.1 10 nA
(Q1, Q2, Q4, and Q5)
Emitter Cutoff Current (Q3 and Q6)V
DC Current Gain (Q1 thru Q6)I
= 1V, IC = 0 A - - 100 nA
EB
= 10mA, VCE = 3V A 40 70 - -
C
Collector-to-Base Capacitance VCB = 5V, f = 1MHz B - 300 - fF
Emitter-to-Base Capacitance VEB = 0, f = 1MHz B - 200 - fF
Current Gain-Bandwidth Product IC = 10mA, VCE = 5V C - 10 - GHz
Power Gain-Bandwidth Product IC = 10mA, VCE = 5V C - 5 - GHz
Availab le Gain at Minimum Noise Figure IC = 3mA,
f = 0.5GHz C - 17.5 - dB
VCE = 3V
f = 1.0GHz C - 12.4 - dB
Minimum Noise Figure IC = 3mA,
f = 0.5GHz C - 1.8 - dB
VCE = 3V
f = 1.0GHz C - 2.1 - dB
50Ω Noise Figure IC = 3mA,
f = 0.5GHz C - 3.3 - dB
VCE = 3V
f = 1.0GHz C - 3.5 - dB
DC Current Gain Matching
IC = 10mA, VCE = 3V A 0.9 1.0 1.1 -
(Q1 and Q2, Q4 and Q5)
Input Offset Voltage (Q1 and Q2),
IC = 10mA, VCE = 3V A - 1.5 5 mV
(Q4 and Q5)
I
OS
Input Offset Current (Q1 and Q2),
IC = 10mA, VCE = 3V A - 5 25 µA
(Q4 and Q5)
3-450
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