The HFA3101 is an all NPN transistor array configured as a
Multiplier Cell. Based on Intersil’s bonded wafer UHF-1 SOI
process, this array achieves very high f
maintaining excellent h
and VBE matching characteristics
FE
(10GHz) while
T
that have been maximized through careful attention to circuit
design and layout, making this product ideal for
communication circuits. For use in mixer applications, the
cell provides high gain and good cancellation of 2nd order
distortion terms.
Ordering Information
PART NUMBER
(BRAND)
HFA3101B
(H3101B)
HFA3101BZ
(H3101B) (Note)
HFA3101B96
(H3101B)
HFA3101BZ96
(H3101B) (Note)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
TEMP.
RANGE (°C)
-40 to 858 Ld SOICM8.15
-40 to 858 Ld SOIC
-40 to 858 Ld SOIC Tape
-40 to 858 Ld SOIC Tape
PACKAGE
M8.15
(Pb-free)
M8.15
and Reel
M8.15
and Reel (Pb-free)
PKG.
DWG. #
FN3663.5
Features
• Pb-free Available as an Option
• High Gain Bandwidth Product (fT) . . . . . . . . . . . . . 10GHz
• High Power Gain Bandwidth Product. . . . . . . . . . . . 5GHz
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Electrical SpecificationsT
= 25oC
A
(NOTE 2)
TEST
PARAMETERTEST CONDITIONS
Collector to Base Breakdown V oltage, V
Collector to Emitter Breakdown Voltage, V
Q5 and Q
Emitter to Base Breakdown Voltage, V
Collector Cutoff Current, I
Emitter Cutoff Current, I
DC Current Gain, hFE, Q1 thru Q
Collector to Base Capacitance, C
6
(BR)EBO
, Q1 thru Q
CBO
, Q5 and Q
EBO
6
6
CB
, Q1 thru Q6IC = 100µA, IE = 0A1218-V
(BR)CBO
,
(BR)CEO
, Q1 thru Q6IE = 10µA, IC = 0A5.56-V
4
Q1 thru Q
Q5 and Q
Emitter to Base Capacitance, C
EB
Q1 thru Q
Q5 and Q
Current Gain-Bandwidth Product, f
T
Q1 thru Q
Q5 and Q
Power Gain-Bandwidth Product, f
MAX
Q1 thru Q
Q5 and Q
Available Gain at Minimum Noise Figure, G
Q5 and Q
Minimum Noise Figure, NF
50Ω Noise Figure, NF
DC Current Gain Matching, h
Q3 and Q4, and Q5 and Q
6
, Q5 and Q
MIN
, Q5 and Q
50Ω
6
FE1/hFE2
6
, Q1 and Q2,
NFMIN
6
,
Input Offset Voltage, VOS, (Q1 and Q2), (Q3 and Q4),
IC = 100µA, IB = 0A812-V
VCB = 8V, IE = 0A-0.110nA
VEB = 1V, IC = 0A--200nA
IC = 10mA, VCE = 3VA4070VCB = 5V, f = 1MHzC-0.300-pF
4
6
VEB = 0, f = 1MHzB-0.200-pF
4
6
= 10mA, VCE = 5VC-10-GHz
4IC
= 20mA, VCE = 5VC-10-GHz
6IC
= 10mA, VCE = 5VC-5-GHz
4IC
= 20mA, VCE = 5VC-5-GHz
6IC
IC = 5mA,
V
= 3V
CE
IC = 5mA,
V
= 3V
CE
IC = 5mA,
V
= 3V
CE
f = 0.5GHzC-17.5-dB
f = 1.0GHzC-11.9-dB
f = 0.5GHzC-1.7-dB
f = 1.0GHzC-2.0-dB
f = 0.5GHzC-2.25-dB
f = 1.0GHzC-2.5-dB
IC = 10mA, VCE = 3VA0.91.01.1
IC = 10mA, VCE = 3VA-1.55mV
LEVEL
MINTYPMAXUNITS
-0.600-pF
-0.400-pF
(Q5 and Q6)
Input Offset Current, IC, (Q1 and Q2), (Q3 and Q4),
IC = 10mA, VCE = 3VA-525µA
(Q5 and Q6)
Input Offset Voltage TC, dVOS/dT, (Q1 and Q2, Q3 and Q4,
Q
and Q6)
5
Collector to Collector Leakage, I
TRENCH-LEAKAGE
IC = 10mA, VCE = 3VC-0.5-µV/oC
∆V
= 5VB-0.01-nA
TEST
NOTE:
2. Test Level: A. Production Tested, B. Typical or Guaranteed Limit Based on Characterization, C. Design Typical for Information Only.