The HFA3046, HFA3096, HFA3127 and the HFA3128 are
Ultra High Frequency Transistor Arrays that are fabricated
from Intersil Corporation’s complementary bipolar UHF-1
process. Each array consists of five dielectrically isolated
transistors on a common monolithic substrate. The NPN
transistors exhibit a f
provide a f
of 5.5GHz. Both types exhibit low noise (3.5dB),
T
making them ideal for high frequency amplifier and mixer
applications.
The HFA3046 and HFA3127 are all NPN arrays while the
HFA3128 has all PNP transistors. The HFA3096 is an
NPN-PNP combination. Access is provided to each of the
terminals for the individual transistors for maximum
application flexibility. Monolithic construction of these
transistor arrays provides close electrical and thermal
matching of the five transistors.
Intersil provides an Application Note illustrating the use of
these devices as RF amplifiers. For more information, visit
our website at www.intersil.com.
• Pin Compatible with Industry Standard 3XXX Series
Arrays
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• VHF/UHF Amplifiers
•VHF/UHF Mixers
• IF Converters
• Synchronous Detectors
Ordering Information
PART NUMBER*PART MARKINGTEMP. RANGE (°C)PACKAGEPKG. DWG. #
HFA3046BHFA3046B-55 to 12514 Ld SOICM14.15
HFA3046BZ (Note)HFA3046BZ-55 to 12514 Ld SOIC (Pb-free)M14.15
HFA3096BHFA3096B-55 to 12516 Ld SOICM16.15
HFA3096BZ (Note)HFA3096BZ-55 to 12516 Ld SOIC (Pb-free)M16.15
HFA3127BHFA3127B-55 to 12516 Ld SOICM16.15
HFA3127BZ (Note)HFA3127BZ-55 to 12516 Ld SOIC (Pb-free)M16.15
HFA3127R127-55 to 12516 Ld 3x3 QFNL16.3x3
HFA3127RZ (Note)127Z-55 to 12516 Ld 3x3 QFN (Pb-free)L16.3x3
HFA3128BHFA3128B-55 to 12516 Ld SOICM16.15
HFA3128BZ (Note)HFA3128BZ-55 to 12516 Ld SOIC (Pb-free)M16.15
HFA3128R128-55 to 12516 Ld 3x3 QFNL16.3x3
HFA3128RZ (Note)128Z-55 to 12516 Ld 3x3 QFN (Pb-free)L16.3x3
*Add “96” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
is measured with the component mounted on an evaluation PC board in free air.
1. θ
JA
2. For θ
3. θ
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Thermal Resistance (Typical)θ
(°C/W) θJC (°C/W)
JA
14 Ld SOIC Package (Note 1) . . . . . . .120N/A
16 Ld SOIC Package (Note 1) . . . . . . .115N/A
QFN Package (Notes 2, 3). . . . . . . . . .5710
Maximum Power Dissipation (Any One Transistor) . . . . . . . . 0.15W
FIGURE 3. NPN DC CURRENT GAIN vs COLLECTOR CURRENTFIGURE 4. NPN G AI N BANDWIDT H PRODUCT vs C OL LE C T O R
CURRENT (UHF 3 x 50 WITH BOND P A DS)
-25
-20
-15
-10
-5
COLLECTOR CURRENT (mA)
I
= -400µA
B
I
= -320µA
B
I
= -240µA
B
I
= -160µA
B
I
= -80µA
B
0
0
-1-2-3-4-5
COLLECTOR TO EMITTER VOLTAGE (V)
FIGURE 5. PNP COLLECTOR CURRENT vs COLLECTOR TO
EMITTER VOLTAGE
FIGURE 7. PNP DC CURRENT GAIN vs COLLECTOR
CURRENT
FIGURE 6. PNP COLLECTOR CURRENT AND BASE
CURRENT vs BASE TO EMITTER VOLTAGE
FIGU RE 8. P NP GAIN BANDWIDTH PRODUCT vs COLLECTOR
CURRENT (UHF 3 x 50 WITH BOND P A DS)
9
FN3076.13
December 21, 2005
Die Characteristics
HFA3046, HFA3096, HFA3127, HFA3128
DIE DIMENSIONS:
53 mils x 52 mils x 19 mils
1340µm x 1320µm x 483µm
METALLIZATION:
Type: Metal 1: AlCu(2%)/TiW
Thickness: Metal 1: 8kű0.4kÅ
Type: Metal 2: AlCu(2%)
Thickness: Metal 2: 16k
Å ±0.8kÅ
Metallization Mask Layout
1340µm
(53 mils)
PAS S I VATI O N:
Type: Nitride
Thickness: 4kű0.5kÅ
PROCESS:
UHF-1
SUBSTRATE POTENTIAL: (POWERED UP)
Unbiased
HFA3096, HFA3127, HFA3128
12
3
4
5
6
78 910
1516
14
13
12
11
1320µm
(52 mils)
HFA3046
1340µm
(53 mils)
3
4
5
6
12
78
1320µm
(52 mils)
1314
9
Pad numbers correspond to SOIC pinout.
12
11
10
10
FN3076.13
December 21, 2005
HFA3046, HFA3096, HFA3127, HFA3128
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010)BMM
H
L
h x 45
o
α
e
B
0.25(0.010)C AMBS
M
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
A1
C
0.10(0.004)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHESMILLIMETERS
SYMBOL
A0.05320.06881.351.75-
A10.00400.00980.100.25-
B0.0130.0200.330.519
C0.00750.00980.190.25-
D0.33670.34448.558.753
E0.14970.15743.804.004
e0.050 BSC1.27 BSC-
H0.22840.24405.806.20-
h0.00990.01960.250.505
L0.0160.0500.401.276
N14147
α
0°8°0°8°-
NOTESMINMAXMINMAX
Rev. 0 12/93
11
FN3076.13
December 21, 2005
HFA3046, HFA3096, HFA3127, HFA3128
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010)BM
123
SEATING PLANE
-A-
D
e
B
0.25(0.010)C AMBS
M
A
-C-
A1
0.10(0.004)
L
h x 45°
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2
and D2 MAX dimension.
NOTESMINNOMINALMAX
Rev. 1 6/04
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN3076.13
December 21, 2005
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