Intersil Corporation HFA1135 Datasheet

HFA1135

Data Sheet June 2000

360MHz, Low Power, Video Operational Ampliﬁer with Output Limiting

The HFA1135 is a high speed, low power current feedback ampliﬁer build with Intersil’s proprietary complementary bipolar UHF-1 process. This ampliﬁer features user programmable output limiting, via the V

The HFA1135 is the ideal choice for high speed, low power applications requiring output limiting (e.g. ﬂash A/D drivers), especially those requiring fast overdriverecovery times. The limiting function allows thedesignertosetthemaximum and minimum output levels to protect downstream stages from damage or input saturation. The sub-nanosecond overdrive recovery time ensures a quick return to linear operation following an overdrive condition.

Component and composite video systems also beneﬁt from this operational ampliﬁer’s performance, as indicated by the gain ﬂatness, and differential gain and phase speciﬁcations.

The HFA1135 is a low power, high performance upgrade for the CLC501 and CLC502.

and VL pins.

File Number 3653.5

Features

• User Programmable Output Voltage Limiting

• Fast Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . .<1ns

• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . 6.8mA

• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 2MΩ

• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 360MHz

• Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 1200V/µs

• Gain Flatness (to 50MHz) . . . . . . . . . . . . . . . . . . ±0.07dB

• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02%

• Differential Phase. . . . . . . . . . . . . . . . . . . . 0.04 Degrees

• Pin Compatible Upgrade to CLC501 and CLC502

Applications

• Flash A/D Drivers

• High Resolution Monitors

• Professional Video Processing

Ordering Information

PART NUMBER

(BRAND)

HFA1135IB (H1135I)

HFA1135IB96 (H1135I)

HFA11XXEVAL DIP Evaluation Board for High Speed

TEMP.

RANGE (oC) PACKAGE

-40 to 85 8 Ld SOIC M8.15

-40 to 85 8 Ld SOIC Tape and Reel

Op Amps

PKG.

NO.

M8.15

• Video Digitizing Boards/Systems

• Multimedia Systems

• RGB Preamps

• Medical Imaging

• Hand Held and Miniaturized RF Equipment

• Battery Powered Communications

Pinout

HFA1135

(SOIC)

TOP VIEW

-IN

+IN

1 2

3 4

V-

V+

OUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

HFA1135

Absolute Maximum Ratings T

Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V

Output Current (Note 1). . . . . . . . . . . . . . . . .Short Circuit Protected

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >600V

= 25oC Thermal Information

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SUPPLY

30mA Continuous

60mA ≤ 50% Duty Cycle

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Maximum Junction Temperature (Die Only). . . . . . . . . . . . . . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Speciﬁcations V

PARAMETER TEST CONDITIONS

INPUT CHARACTERISTICS

Input Offset Voltage A 25 - 2 5 mV

Average Input Offset Voltage Drift B Full - 1 10 µV/oC Input Offset Voltage

Common-Mode Rejection Ratio

Input Offset Voltage Power Supply Rejection Ratio

Non-Inverting Input Bias Current A 25 - 6 15 µA

Non-Inverting Input Bias Current Drift B Full - 5 60 nA/oC Non-Inverting Input Bias Current

Power Supply Sensitivity

Non-Inverting Input Resistance ∆VCM = ±1.8V A 25 0.8 2 - MΩ

Inverting Input Bias Current A 25 - 0.1 4 µA

Inverting Input Bias Current Drift B Full - 60 200 nA/oC Inverting Input Bias Current

Common-Mode Sensitivity

Inverting Input Bias Current Power Supply Sensitivity

Inverting Input Resistance C 25 - 40 - Ω Input Capacitance (Either Input) C 25 - 1.6 - pF

= ±5V, AV = +1, RF = 510Ω (Note 3), RL = 100Ω, Unless Otherwise Speciﬁed

SUPPLY

(NOTE 2)

TEST

LEVEL

∆VCM = ±1.8V A 25 47 50 - dB ∆VCM= ±1.8V A 85 45 48 - dB ∆VCM= ±1.2V A -40 45 48 - dB ∆VPS = ±1.8V A 25 50 54 - dB ∆VPS = ±1.8V A 85 47 50 - dB ∆VPS = ±1.2V A -40 47 50 - dB

∆VPS = ±1.8V A 25 - 0.5 1 µA/V ∆VPS = ±1.8V A 85 - 0.8 3 µA/V ∆VPS = ±1.2V A -40 - 0.8 3 µA/V

∆VCM = ±1.8V A 85 0.5 1.3 - MΩ ∆VCM = ±1.2V A -40 0.5 1.3 - MΩ

∆VCM = ±1.8V A 25 - 3 6 µA/V ∆VCM = ±1.8V A 85 - 4 8 µA/V ∆VCM = ±1.2V A -40 - 4 8 µA/V ∆VPS = ±1.8V A 25 - 2 5 µA/V ∆VPS = ±1.8V A 85 - 4 8 µA/V ∆VPS = ±1.2V A -40 - 4 8 µA/V

TEMP.

(oC) MIN TYP MAX UNITS

A Full - 3 8 mV

A Full - 10 25 µA

A Full - 3 8 µA

HFA1135

Electrical Speciﬁcations V

= ±5V, AV = +1, RF = 510Ω (Note 3), RL = 100Ω, Unless Otherwise Speciﬁed (Continued)

SUPPLY

(NOTE 2)

PARAMETER TEST CONDITIONS

Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -I

CMS tests)

BIAS

TEST

LEVEL

TEMP.

(oC) MIN TYP MAX UNITS

A 25, 85 ±1.8 ±2.4 - V

A -40 ±1.2 ±1.7 - V Input Noise Voltage Density (Note 5) f = 100kHz B 25 - 3.5 - nV/√Hz Non-Inverting Input Noise Current Density (Note 5) f = 100kHz B 25 - 2.5 - pA/√Hz Inverting Input Noise Current Density (Note 5) f = 100kHz B 25 - 20 - pA/√Hz

TRANSFER CHARACTERISTICS

Open Loop Transimpedance Gain (Note 5) AV = -1 C 25 - 500 - kΩ AC CHARACTERISTICS AV = +2, RF = 250Ω, Unless Otherwise Speciﬁed

-3dB Bandwidth (V

= 0.2V

OUT

P-P

, Note 5)

AV = +1, RF = 1.5kΩ B 25 - 660 - MHz AV = +2, RF = 250Ω B 25 - 360 - MHz AV = +2, RF = 330Ω B 25 - 315 - MHz AV = -1, RF = 330Ω B 25 - 290 - MHz

Full Power Bandwidth (V

= 5V

OUT

at AV = +1, Note 5)

P-P

at AV = +2/-1,

P-P

Gain Flatness (to 25MHz, V

OUT

= 0.2V

P-P

, Note 5)

AV = +1, RF = 1.5kΩ B 25 - 90 - MHz AV = +2, RF = 250Ω B 25 - 130 - MHz AV = -1, RF = 330Ω B 25 - 170 - MHz AV = +1, RF = 1.5kΩ B25-±0.10 - dB AV = +2, RF = 250Ω B25-±0.02 - dB AV = +2, RF = 330Ω B25-±0.02 - dB

Gain Flatness (to 50MHz, V

OUT

= 0.2V

P-P

, Note 5)

AV = +1, RF = 1.5kΩ B25-±0.22 - dB AV = +2, RF = 250Ω B25-±0.07 - dB

AV = +2, RF = 330Ω B25-±0.03 - dB Minimum Stable Gain A Full - 1 - V/V OUTPUT CHARACTERISTICS RF = 510Ω, Unless Otherwise Speciﬁed Output Voltage Swing (Note 5) AV = -1, RL = 100Ω A25±3 ±3.4 - V

A Full ±2.8 ±3- V

Output Current (Note 5) AV = -1, RL = 50Ω A 25, 85 50 60 - mA

A -40 28 42 - mA Output Short Circuit Current B 25 - 90 - mA Closed Loop Output Resistance (Note 5) DC, AV = +2, RF = 250Ω B 25 - 0.07 - Ω Second Harmonic Distortion

(AV = +2, RF = 250Ω, V

OUT

Third Harmonic Distortion (AV = +2, RF = 250Ω, V

OUT

= 2V

P-P

, Note 5)

10MHz B 25 - -50 - dBc 20MHz B 25 - -45 - dBc 10MHz B 25 - -50 - dBc

20MHz B 25 - -45 - dBc TRANSIENT CHARACTERISTICS AV = +2, RF = 250Ω, Unless Otherwise Speciﬁed Rise and Fall Times

OUT

= 0.5V

P-P

, Note 5)

Overshoot (Note 4) (V

= 0 to 0.5V, VIN t

OUT

Overshoot (Note 4) (V

OUT

= 0.5V

P-P

, VIN t

Slew Rate (V

OUT

= 4V

, AV = +1, RF = 1.5kΩ)

P-P

Slew Rate (V

OUT

= 5V

, AV = +2, RF = 250Ω)

P-P

RISE

= 2.5ns)

Rise Time B 25 - 0.81 - ns

Fall Time B 25 - 1.25 - ns

+OS B 25 - 3 - %

-OS B 25 - 5 - %

+OS B 25 - 2 - %

-OS B 25 - 10 - %

+SR B 25 - 875 - V/µs

-SR (Note 6) B 25 - 510 - V/µs

+SR B 25 - 1530 - V/µs

-SR (Note 6) B 25 - 850 - V/µs

HFA1135

Electrical Speciﬁcations V

PARAMETER TEST CONDITIONS

Slew Rate (V

= 5V

OUT

Settling Time (V

= +2V to 0V step, Note 5)

OUT

VIDEO CHARACTERISTICS AV = +2, RF = 250Ω, Unless Otherwise Speciﬁed Differential Gain (f = 3.58MHz) RL = 150Ω B 25 - 0.02 - %

Differential Phase (f = 3.58MHz) RL = 150Ω B 25 - 0.04 - Degrees

OUTPUT LIMITING CHARACTERISTICS AV = +2, RF = 250Ω, VH = +1V, VL = -1V, Unless Otherwise Speciﬁed Limit Accuracy (Note 5) VIN = ±2V, AV = -1,

Overdrive Recovery Time (Note 5) VIN = ±1V B 25 - 0.8 - ns Negative Limit Range B 25 -5.0 to +2.5 V Positive Limit Range B 25 -2.5 to +5.0 V Limit Input Bias Current A 25 - 50 200 µA

POWER SUPPLY CHARACTERISTICS

Power Supply Range C 25 ±4.5 - ±5.5 V Power Supply Current (Note 5) A Full 6.4 6.9 7.3 mA

NOTES:

2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.

3. The optimum feedback resistor for the HFA1135 at AV= +1 is 1.5kΩ. The Production Tested parameters are tested with RF= 510Ω because the HFA1135 shares test hardware with the HFA1105 amplifier.

4. Undershoot dominates for output signal swings below GND (e.g., 0.5V condition. See the “Application Information” section for details.

5. See Typical Performance Curves for more information.

6. Slew rates are asymmetrical if the output swings below GND (e.g., a bipolar signal). Positive unipolar output signals have symmetric positive and negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details.

, AV = -1, RF = 330Ω)

P-P

= ±5V, AV = +1, RF = 510Ω (Note 3), RL = 100Ω, Unless Otherwise Speciﬁed (Continued)

SUPPLY

(NOTE 2)

TEST

LEVEL

+SR B 25 - 2300 - V/µs

-SR (Note 6) B 25 - 1200 - V/µs To 0.1% B 25 - 23 - ns To 0.05% B 25 - 33 - ns To 0.02% B 25 - 45 - ns

RL = 75Ω B 25 - 0.03 - %

RL = 75Ω B 25 - 0.06 - Degrees

RF = 510Ω

), yielding a higher overshoot limit compared to the V

P-P

TEMP.

(oC) MIN TYP MAX UNITS

A Full -125 25 125 mV

A Full - 80 200 µA

OUT

= 0V to 0.5V

Application Information

Relevant Application Notes

The following Application Notes pertain to the HFA1135:

• AN9653-Use and Application of Output Limiting Ampliﬁers

• AN9752-Sync Stripper and Sync Inserter for Composite Video

• AN9787-An Intuitive Approach to Understanding Current Feedback Ampliﬁers

• AN9420-Current Feedback Ampliﬁer Theory and Applications

• AN9663-Converting from Voltage Feedback to Current Feedback Ampliﬁers

These publications may be obtained from Intersil’s web site (www.intersil.com) or via our AnswerFAX system.

Optimum Feedback Resistor

Although a current feedback ampliﬁer’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback ampliﬁer, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback ampliﬁer’s unique relationship between bandwidth and R All current feedback ampliﬁers require a feedback resistor, even for unity gain applications, and R

, in conjunction with

the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the ampliﬁer’s bandwidth is inversely proportional to R optimized for a 250Ω R

. The HFA1135 design is

at a gain of +2. Decreasing R

decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same

HFA1135

problemsdue to the feedbackimpedance decrease at higher frequencies). At higher gains the ampliﬁer is more stable, so R

can be decreased in a trade-off of stability for bandwidth.

The table below lists recommended RF values, and the expected bandwidth, for various closed loop gains.

TABLE 1. OPTIMUM FEEDBACK RESISTOR

GAIN

-1 330 290 +1 1.5k 660 +2 250

+5 180 200

+10 250 90

(Ω)

330

BANDWIDTH

(MHz)

360 315

Non-inverting Input Source Impedance

For best operation, the DC source impedance seen by the non-inverting input should be ≥50Ω. This is especially important in inverting gain conﬁgurations where the noninverting input would normally be connected directly toGND.

Pulse Undershoot and Asymmetrical Slew Rates

The HFA1135 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (see Figures 9, 13, and 17). This undershoot isn’t present for small bipolar signals, or large positive signals. Another artifact of the composite device is asymmetrical slew rates for output signals with a negative voltage component. Theslew rate degrades as the output signal crosses through 0V (see Figures 9, 13, and

17), resulting in a slower overall negative slew rate. Positive only signals havesymmetrical slew rates as illustrated in the large signal positive pulse response graphs (see Figures 7, 11, and 15).

PC Board Layout

This ampliﬁer’s frequency response depends greatly on the care taken in designing the PC board. The use of low

inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must!

Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases.

Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section.

Care must also be taken to minimize the capacitance to ground at the ampliﬁer’s inverting input (-IN), as this capacitance causes gain peaking, pulse overshoot, and if large enough, instability. To reduce this capacitance, the designer should remove the ground plane under traces connected to -IN, and keep connections to -IN as short as possible.

An example of a good high frequency layout is the Evaluation Board shown in Figure 2.

Driving Capacitive Loads

Capacitive loads, such as an A/D input, or an improperly terminated transmission line degrade the ampliﬁer’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (R prior to the capacitance.

Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the R combinations for the optimum bandwidth, stability, and settling time, but experimental ﬁne tuning is recommended. Picking a point above or to the right of the curve yields an overdampedresponse, while points below or left of the curve indicate areas of underdamped performance.

and CL form a low pass network at the output, thus

limiting system bandwidth well below the ampliﬁer bandwidth of 660MHz (A

= +1). By decreasing RSas CLincreases (as

illustrated by the curves), the maximum bandwidth is obtained without sacriﬁcing stability. In spite of this, bandwidth still decreases as the load capacitance increases. For example, at A

= +1, RS = 50Ω, CL = 20pF, the overall

bandwidth is 170MHz, but the bandwidth drops to 45MHz at A

= +1, RS = 10Ω, CL = 330pF.

50 45 40 35 30

(Ω)

20 15

AV = +1

5 0

0 40 80 120 160 200 240 280 320 360 400

LOAD CAPACITANCE (pF)

FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD

CAPACITANCE

) in series with the output

and C

AV = +1

AV = +2, RF = 250Ω

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