Intersil Corporation HFA1130 Datasheet

HFA1130

September 1998 File Number 3369.2

850MHz, Output Limiting, Low Distortion
Current Feedback Operational Amplifier

The HFA1130 is a high speed wideband current feedback
amplifier featuring programmable output limits. Built with
Intersil’s proprietary complementary bipolar UHF-1 process,
it is the fastest monolithic amplifier available from any
semiconductor manufacturer.

This amplifier is the ideal choice for high frequency
applications requiring outputlimiting,especiallythoseneeding
ultra fastoverdriv ereco very times. The output limiting function
allows the designer to set the maximum positive and negative
output levels, thereby protecting later stages from damage or
input saturation.Thesub-nanosecondo verdriverecov erytime
quickly returns the amplifier to linear operation, following an
overdrive condition.

The HFA1130 offers significant performance improvements
over the CLC500/501/502.

A variety of packages and temperature grades are available.
See the ordering information below for details. For /883
product refer to the HFA1130/883 datasheet.

Ordering Information

PART NUMBER

(BRAND)

HFA1130IP -40 to 85 8 Ld PDIP E8.3
HFA1130IB

(H1130I)
HFA11XXEVAL DIPEvaluationBoard forHigh-Speed Op Amps

TEMP.

RANGE (oC) PACKAGE PKG. NO.

-40 to 85 8 Ld SOIC M8.15

Features

• User Programmable Output Voltage Limits

• Low Distortion (30MHz, HD2). . . . . . . . . . . . . . . . . -56dBc

• -3dB Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 850MHz

• Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . .2300V/µs

• Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . 11ns

• Excellent Gain Flatness

- (100MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.14dB

- (50MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.04dB

- (30MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.01dB

• High Output Current. . . . . . . . . . . . . . . . . . . . . . . . .60mA

• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns

Applications

• Residue Amplifier

• Video Switching and Routing

• Pulse and Video Amplifiers

• Wideband Amplifiers

• RF/IF Signal Processing

• Flash A/D Driver

• Medical Imaging Systems

• Related Literature

- AN9420, Current Feedback Theory

- AN9202, HFA11XX Evaluation Fixture

The Op Amps With Fastest Edges

0ns 25ns

1

Pinout

HFA1130

(PDIP, SOIC)

TOP VIEW

INPUT
220MHz
SIGNAL

OUTPUT

= 2)

(A

V

HFA1130
OP AMP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

NC

-IN

+IN

1
2

-

+

3

V-

4

8

V

H

V+

7

OUT

6

V

5

L

HFA1130

Absolute Maximum Ratings T

Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V

Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications V

PARAMETER

INPUT CHARACTERISTICS

Input Offset Voltage (Note 3) A 25 - 2 6 mV

Input Offset Voltage Drift C Full - 10 - µV/oC
VIO CMRR ∆VCM = ±2V A 25 40 46 - dB

VIO PSRR ∆VS = ±1.25V A 25 45 50 - dB

Non-Inverting Input Bias Current
(Note 3)

+I

Drift C Full - 40 - nA/oC

BIAS

+I

CMS ∆VCM = ±2V A 25 - 20 40 µA/V

BIAS

Inverting Input Bias Current (Note 3) -IN = 0V A 25 - 12 50 µA

-I

Drift C Full - 40 - nA/oC

BIAS

-I

CMS ∆VCM = ±2V A 25 - 1 7 µA/V

BIAS

-I

PSS ∆VS = ±1.25V A 25 - 6 15 µA/V

BIAS

Non-Inverting Input Resistance A 25 25 50 - kΩ
Inverting Input Resistance C 25 - 20 30 Ω
Input Capacitance (Either Input) B 25 - 2 - pF
Input Common Mode Range C Full ±2.5 ±3.0 - V
Input Noise Voltage (Note 3) 100kHz B 25 - 4 - nV/√Hz
+Input Noise Current (Note 3) 100kHz B 25 - 18 - pA/√Hz

-Input Noise Current (Note 3) 100kHz B 25 - 21 - pA/√Hz
TRANSFER CHARACTERISTICS AV = +2, Unless Otherwise Specified
Open Loop Transimpedance (Note 3) B 25 - 300 - kΩ

= 25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

SUPPLY

= ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified

SUPPLY

(NOTE 2)

TEST

CONDITIONS

+IN = 0V A 25 - 25 40 µA

TEST

LEVEL

A Full - - 10 mV

A Full 38 - - dB

A Full 42 - - dB

A Full - - 65 µA

A Full - - 50 µA/V

A Full - - 60 µA

A Full - - 10 µA/V

A Full - - 27 µA/V

PDIP Package . . . . . . . . . . . . . . . . . . . 130 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 170 N/A

Maximum Junction Temperature (Plastic Package). . . . . . . . 150oC

Maximum Storage Temperature Range. . . . . . -65oC to TA to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

TEMP.

(oC) MIN TYP MAX UNITS

2

HFA1130

Electrical Specifications V

= ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued)

SUPPLY

(NOTE 2)

PARAMETER

-3dB Bandwidth (Note 3) V

TEST

CONDITIONS

= 0.2V

OUT

P-P

,

TEST

LEVEL

TEMP.

(oC) MIN TYP MAX UNITS

B 25 530 850 - MHz

AV = +1

-3dB Bandwidth V

OUT

= 0.2V

P-P

,

B 25 - 670 - MHz

AV = +2, RF = 360Ω

Full Power Bandwidth 4V

, AV = -1 B Full - 300 - MHz

P-P

Gain Flatness (Note 3) To 100MHz B 25 - ±0.14 - dB
Gain Flatness To 50MHz B 25 - ±0.04 - dB
Gain Flatness To 30MHz B 25 - ±0.01 - dB
Linear Phase Deviation (Note 3) DC to 100MHz B 25 - 0.6 - Degrees
Differential Gain NTSC, RL = 75Ω B 25 - 0.03 - %
Differential Phase NTSC, RL = 75Ω B 25 - 0.05 - Degrees
Minimum Stable Gain A Full 1 - - V/V
OUTPUT CHARACTERISTICS AV = +2, Unless Otherwise Specified
Output Voltage (Note 3) AV = -1 A 25 ±3.0 ±3.3 - V

A Full ±2.5 ±3.0 - V

Output Current RL = 50Ω, AV = -1 A 25, 85 50 60 - mA

A -40 35 50 - mA

DC Closed Loop Output Impedance

B 25 - 0.07 - Ω

(Note 3)
2nd Harmonic Distortion (Note 3) 30MHz, V
3rd Harmonic Distortion (Note 3) 30MHz, V

OUT
OUT

= 2V
= 2V

P-P
P-P

B 25 - -56 - dBc

B 25 - -80 - dBc
3rd Order Intercept (Note 3) 100MHz B 25 20 30 - dBm
1dB Compression 100MHz B 25 15 20 - dBm
TRANSIENT RESPONSE AV = +2, Unless Otherwise Specified
Rise Time V
Overshoot (Note 3) V
Slew Rate AV = +1,

0.1% Settling Time (Note 3) V

0.2% Settling Time (Note 3) V

= 2.0V Step B 25 - 900 - ps

OUT

= 2.0V Step B 25 - 10 - %

OUT

B 25 - 1400 - V/µs

V

= 5V

OUT

AV = +2,
V

OUT
OUT
OUT

P-P

B 25 1850 2300 - V/µs

= 5V

P-P

= 2V to 0V B 25 - 11 - ns
= 2V to 0V B 25 - 7 - ns

POWER SUPPLY CHARACTERISTICS

Supply Voltage Range B Full ±4.5 - ±5.5 V
Supply Current (Note 3) A 25 - 21 26 mA

A Full - - 33 mA
LIMITING CHARACTERISTICS AV = +2, VH = +1V, VL = -1V, Unless Otherwise Specified
Clamp Accuracy VIN = ±2V, AV = -1 A 25 - 60 ±125 mV
Clamped Overshoot VIN = ±1V,

B25-4-%

Input tR/tF = 2ns

Overdrive Recovery Time VIN = ±1V B 25 - 0.75 1.5 ns

3

HFA1130

Electrical Specifications V

PARAMETER

Negative Clamp Range B 25 - -5.0 to +2.0 - V
Positive Clamp Range B 25 - -2.0 to +5.0 - V
Clamp Input Bias Current A 25 - 50 200 µA
Clamp Input Bandwidth VH or VL = 100mV

NOTES:

2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.

3. See Typical Performance Curves for more information.

Application Information

= ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued)

SUPPLY

(NOTE 2)

TEST

CONDITIONS

P-P

TEST

LEVEL

TEMP.

(oC) MIN TYP MAX UNITS

B 25 - 500 - MHz

output voltage at V

or VL (± the clamp accuracy),

H

respectively. The low input bias currents of the clamp pins

Optimum Feedback Resistor (RF)

The enclosed plots of inverting and non-inverting frequency
response detail the performance of the HFA1100/1120 in
various gains. Although the bandwidth dependency on A
isn’t as severe as that of a voltage feedback amplifier, there is
an appreciable decrease in bandwidth at higher gains. This
decrease can be minimized by taking advantage of the
current feedback amplifier’s unique relationship between
bandwidth and R

. All current feedback amplifiers require a

F

feedbackresistor, evenfor unity gain applications, and the R
in conjunction with the internal compensation capacitor, sets
the dominant pole of the frequency response. Thus, the
amplifier’s bandwidth is inversely proportional to R
HF A1100, 1120 designs are optimized for a 510Ω R
gain of +1. Decreasing R

in a unity gain application

F

decreases stability, resulting in excessive peaking and
overshoot (Note: Capacitive feedback causes the same
problems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplifier is more stable, so
R

can be decreased in a trade-off of stability for bandwidth.

F

The table below lists recommended R

values for v arious

F

gains, and the expected bandwidth.

A

CL

+1 510 850

-1 430 580
+2 360 670
+5 150 520

[phone]
[phone]

RF(Ω) BW (MHz)

. The

F

F

CL

, at a

,

F

allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.

Clamp Circuitry

Figure 1 shows a simplified schematic of the HF A1130 input
stage, and the high clamp (V
feedback amplifiers, there is a unity gain b uff er (Q
betweenthe positiveand negative inputs.This bufferforces-IN to
track +IN, and sets up a slewing current of (V
This current is mirrored onto the high impedance node (Z) by
Q

, where it is converted to a voltageand fed to the output

X3-QX4

via another unity gain buffer . If no clamping is utiliz ed, the high
impedance node may swing within the limits defined by Q
Q

. Note that when the output reaches it’squiescent value,the

N4

current flowing through -IN is reduced to only that small current
(-I

) required to keep the output at the final voltage.

BIAS

Q

P3

Q

N2

Q

P1

I

N1

CLAMP

Q

P2

Q

N3

+IN

V­V+

Q

) circuitry. As with all current

H

V+

Q

P4

Z

Q

N4

+1

Q

N5

Q

P5

- QX2)

X1

-IN-VOUT

50K

(30K

FOR VL)

Q

N6

200Ω

Q

P6

)/RF.

P4

V

R

H

and

1

Clamp Operation

General

The HFA1130 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the V

5) of the amplifier. V

sets the upper output limit, while V

H

sets the lower clamp level. If the amplifier tries to drive the
output above V

, or below VL, the clamp circuitry limits the

H

and VL terminals (pins 8 and

H

4

L

V-

R

F

-IN V

FIGURE 1. HFA1130 SIMPLIFIED VH CLAMP CIRCUITRY

Tracing the path from V

to Z illustrates the effect of the

H

clamp voltage on the high impedance node. V
by 2V

BE(QN6

Q

begins to conduct whenever the high impedance node

P5

and QP6) to set up the base voltage on QP5.

(EXTERNAL)

decreases

H

OUT