Intersil Corporation HFA1113 Datasheet

HFA1113

Data Sheet February 1999 File Number 1342.5

850MHz, Low Distortion, Output Limiting,
Programmable Gain, Buffer Amplifier

The HFA1113 is a high speed Buffer featuring user
programmable gain and output limiting coupled with ultra
high speed performance. This buffer is the ideal choice for
high frequency applications requiring output limiting,
especially those needing ultra fast overload recovery times.
The output limiting function allows the designer to set the
maximum positive and negative output levels, thereby
protecting later stages from damage or input saturation. The
sub-nanosecond overdrive recovery time quickly returns the
amplifier to linear operation following an overdrive condition.

A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components, as described in the “Application Information”
section. Compatibility with existing op amp pinouts provides
flexibility to upgrade low gain amplifiers, while decreasing
component count. Unlike most buffers, the standard pinout
provides an upgrade path should a higher closed loop gain
be needed at a future date.

Component and composite video systems will also benefit
from this buffer’s performance, as indicated by the excellent
gain flatness, and 0.02%/0.04 Degree Differential
Gain/Phase specifications (R

= 150Ω).

L

For Military product, refer to the HFA1113/883 data sheet.

Ordering Information

PART NUMBER

(BRAND)

HFA1113IB
(H1113I)

HFA11XXEVAL DIPEvaluation Board For High Speed Op Amps

TEMP.

RANGE (oC) PACKAGE

-40 to 85 8 Ld SOIC M8.15

PKG.

NO.

Pinout

HFA1113

(SOIC)

TOP VIEW

NC

-IN

+IN

1

2

3

V-

4

300

300

-

+

8

V

H

7

V+

OUT

6

V

5

L

Features

• User Programmable Output Voltage Limiting

• User Programmable For Closed-Loop Gains of +1, -1 or
+2 Without Use of External Resistors

• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . .850MHz

• Excellent Gain Flatness (to 100MHz). . . . . . . . . . ±0.07dB

• Low Differential Gain and Phase . . . 0.02%/0.04 Degrees

• Low Distortion (HD3, 30MHz). . . . . . . . . . . . . . . . . -73dBc

• Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . 2400V/µs

• Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . 13ns

• High Output Current. . . . . . . . . . . . . . . . . . . . . . . . .60mA

• Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V

• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns

• Standard Operational Amplifier Pinout

Applications

• RF/IF Processors

• Driving Flash A/D Converters

• High-Speed Communications

• Impedance Transformation

• Line Driving

• Video Switching and Routing

• Radar Systems

• Medical Imaging Systems

Pin Descriptions

PIN

NAME

NC 1 No Connection

-IN 2 Inverting Input
+IN 3 Non-Inverting Input

V- 4 Negative Supply

V

L

OUT 6 Output

V+ 7 Positive Supply

V

H

NUMBER DESCRIPTION

5 Lower Output Limit

8 Upper Output Limit

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 1999

HFA1113

Absolute Maximum Ratings Thermal Information

Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Voltage at VH or VL Terminal. . . . . . . . . . . . . . (V+) + 2V to (V-) - 2V

Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA

SUPPLY

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications V

PARAMETER TEST CONDITIONS

INPUT CHARACTERISTICS

Output Offset Voltage 25 - 8 25 mV

Output Offset Voltage Drift Full - 10 - µV/
PSRR 25 39 45 - dB

Input Noise Voltage (Note 3) 100kHz 25 - 9 - nV/√
+Input Noise Current (Note 3) 100kHz 25 - 37 - pA/√
Non-Inverting Input Bias Current 25 - 25 40 µA

Non-Inverting Input Resistance 25 25 50 - kΩ
Inverting Input Resistance (Note 2) 25 240 300 360 Ω
Input Capacitance 25 - 2 - pF
Input Common Mode Range Full ±2.5 ±2.8 - V

TRANSFER CHARACTERISTICS

Gain A

DC Non-Linearity (Note 3) A

OUTPUT CHARACTERISTICS

Output Voltage (Note 3) A

Output Current (Note 3) R

Closed Loop Output Impedance DC, AV = +2 25 - 0.3 - Ω

POWER SUPPLY CHARACTERISTICS

Supply Voltage Range Full ±4.5 - ±5.5 V
Supply Current (Note 3) 25 - 21 26 mA

= ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified

SUPPLY

= +1, VIN = +2V 25 0.980 0.990 1.020 V/V

V

AV = +2, VIN = +1V 25 1.96 1.98 2.04 V/V

= +2, ±2V Full Scale 25 - 0.02 - %

V

= -1 25 ±3.0 ±3.3 - V

V

= 50Ω 25, 85 50 60 - mA

L

TEMP.

(oC) MIN TYP MAX UNITS

Full - - 35 mV

Full 35 - - dB

Full - - 65 µA

Full 0.975 - 1.025 V/V

Full 1.95 - 2.05 V/V

Full ±2.5 ±3.0 - V

-40 35 50 - mA

Full - - 33 mA

o

C

Hz
Hz

2

HFA1113

Electrical Specifications V

PARAMETER TEST CONDITIONS

AC CHARACTERISTICS

-3dB Bandwidth
= 0.2V

(V

OUT

Slew Rate

= 5V

(V

OUT

Full Power Bandwidth

= 5V

(V

OUT

Gain Flatness
(to 30MHz, Notes 2, 3)

Gain Flatness
(to 50MHz, Notes 2, 3)

Gain Flatness
(to 100MHz, Notes 2, 3)

Linear Phase Deviation
(to 100MHz, Note 3)

2nd Harmonic Distortion
(30MHz, V

3rd Harmonic Distortion
(30MHz, V

2nd Harmonic Distortion
(50MHz, V

3rd Harmonic Distortion
(50MHz, V

2nd Harmonic Distortion
(100MHz, V

3rd Harmonic Distortion
(100MHz, V

P-P

P-P

P-P

OUT

OUT

OUT

OUT

OUT

OUT

, Notes 2, 3)

, Note 2)

, Note 3)

= 2V

P-P

= 2V

P-P

= 2V

P-P

= 2V

P-P

= 2V

P-P

= 2V

P-P

, Notes 2, 3)

, Notes 2, 3)

, Notes 2, 3)

, Notes 2, 3)

, Notes 2, 3)

, Notes 2, 3)

= ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Continued)

SUPPLY

TEMP.

(oC) MIN TYP MAX UNITS

AV = -1 25 450 800 - MHz

= [phone] - MHz

A

V

= [phone] - MHz

A

V

AV = -1 25 1500 2400 - V/µs

= [phone] - V/µs

A

V

= [phone] - V/µs

A

V

AV = -1 25 - 300 - MHz

= +1 25 - 150 - MHz

A

V

= +2 25 - 220 - MHz

A

V

= -1 25 - ±0.02 - dB

A

V

A

= +1 25 - ±0.1 - dB

V

= +2 25 - ±0.015 ±0.04 dB

A

V

= -1 25 - ±0.05 - dB

A

V

= +1 25 - ±0.2 - dB

A

V

= +2 25 - ±0.036 ±0.08 dB

A

V

= -1 25 - ±0.10 - dB

A

V

= +2 25 - ±0.07 ±0.22 dB

A

V

= -1 25 - ±0.13 - Degrees

A

V

= +1 25 - ±0.83 - Degrees

A

V

= +2 25 - ±0.05 - Degrees

A

V

AV = -1 25 - -52 - dBc

= +1 25 - -57 - dBc

A

V

A

= +2 25 - -52 -45 dBc

V

AV = -1 25 - -71 - dBc

= +1 25 - -73 - dBc

A

V

= +2 25 - -72 -65 dBc

A

V

AV = -1 25 - -47 - dBc

= +1 25 - -53 - dBc

A

V

= +2 25 - -47 -40 dBc

A

V

AV = -1 25 - -63 - dBc

= +1 25 - -68 - dBc

A

V

= +2 25 - -65 -55 dBc

A

V

AV = -1 25 - -41 - dBc
A

= +1 25 - -50 - dBc

V

= +2 25 - -42 -35 dBc

A

V

AV = -1 25 - -55 - dBc

= +1 25 - -49 - dBc

A

V

= +2 25 - -62 -45 dBc

A

V

3

HFA1113

Electrical Specifications V

= ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Continued)

SUPPLY

TEMP.

PARAMETER TEST CONDITIONS

3rd Order Intercept
(AV = +2, Note 3)

1dB Compression

= +2, Note 3)

(A

V

Reverse Isolation

, Note 3)

(S

12

100MHz 25 - 28 - dBm
300MHz 25 - 13 - dBm
100MHz 25 - 19 - dBm
300MHz 25 - 12 - dBm
40MHz 25 - -70 - dB
100MHz 25 - -60 - dB

(oC) MIN TYP MAX UNITS

600MHz 25 - -32 - dB

TRANSIENT CHARACTERISTICS

Rise Time

= 0.5V Step, Note 2)

(V

OUT

Rise Time
(V

= 2V Step)

OUT

Overshoot

= 0.5V Step,

(V

OUT

Input tR/tF = 200ps, Notes 2, 3, 4)

0.1% Settling Time (Note 3) V

0.05% Settling Time V

Differential Gain A

Differential Phase A

OUTPUT LIMITING CHARACTERISTICS A
Clamp Accuracy (Note 3) V

AV = -1 25 - 500 800 ps

= +1 25 - 480 750 ps

A

V

= +2 25 - 700 1000 ps

A

V

AV = -1 25 - 0.82 - ns

= +1 25 - 1.06 - ns

A

V

= +2 25 - 1.00 - ns

A

V

AV = -1 25 - 12 30 %

= +1 25 - 45 65 %

A

V

= +2 25 - 6 20 %

A

V

= 2V to 0V 25 - 13 20 ns

OUT

= 2V to 0V 25 - 20 33 ns

OUT

= +1, 3.58MHz, RL = 150Ω 25 - 0.03 - %

V

= +2, 3.58MHz, RL = 150Ω 25 - 0.02 - %

A

V

= +1, 3.58MHz, RL = 150Ω 25 - 0.05 - Degrees

V

= +2, 3.58MHz, RL = 150Ω 25 - 0.04 - Degrees

A

V

= +2, VH = +1V, VL = -1V, Unless Otherwise Specified

V

= ±1.6V, AV = -1 25 - ±100 ±150 mV

IN

Full - - ±200 mV
Clamp Overshoot V
Overdrive Recovery Time (Note 3) V
Negative Clamp Range 25 - -5.0 to

= ±1V, Input tR/tF = 500ps 25 - 7 - %

IN

= ±1V 25 - 0.75 1.5 ns

IN

-V

+2.0

Positive Clamp Range 25 - -2.0 to

-V

+5.0

Clamp Input Bias Current (Note 3) 25 - 50 200 µA

Full - - 300 µA
Clamp Input Bandwidth (Note 3) V

or VL = 100mV

H

P-P

25 - 500 - MHz

NOTES:

2. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-lot variation.

3. See Typical Performance Curves for more information.

4. Overshoot decreases as input transition times increase, especially for A

= +1. Please refer to Typical Performance Curves.

V

4

HFA1113

Application Information

Closed Loop Gain Selection

The HFA1113features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewerpart
types in inventory, and more efficient use of board space.

This “buffer” operates in closed loop gains of -1, +1, or +2,
and gain selection is accomplished via connections to the
±Inputs. Applying the input signal to +IN and floating -IN
selects a gain of +1, while grounding -IN selects a gain of
+2. A gain of -1 is obtained by applying the input signal to

-IN with +IN grounded.
The table below summarizes these connections:

CONNECTIONS

+INPUT

GAIN (ACL)

-1 GND Input
+1 Input NC (Floating)
+2 Input GND

(PIN 3)

-INPUT
(PIN 2)

PC Board Layout

The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The

use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!

Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
chip (0.1µF) capacitor works well in most cases.

Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.

avoided by placing a resistor (R

) in series with the output

S

prior to the capacitance.
Figure 1 details starting points for the selection of this

resistor. The points on the curve indicate the R

and C

S

L

combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdampedresponse, while points below or left of the curve
indicate areas of underdamped performance.

R

and CLform a low pass network at the output, thus

S

limiting system bandwidth well belowthe amplifier bandwidth
of 850MHz. By decreasing R

as CLincreases (as illustrated

S

in the curves), the maximum bandwidth is obtained without
sacrificing stability. Even so, bandwidth does decrease as
you move to the right along the curve. For example, at
A

= +1, RS = 50Ω, CL = 30pF, the overall bandwidth is

V

limited to 300MHz, and bandwidth drops to 100MHz at
A

= +1, RS = 5Ω, CL = 340pF.

V

50
45
40
35
30
25

(Ω)

S

20

R

15
10

5
0

0 40 80 120 160 200 240 280 320 360 400

FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD

AV = +1

AV = +2

LOAD CAPACITANCE (pF)

CAPACITANCE

For unity gain applications, care must also be taken to
minimize the capacitance to ground seen by the amplifier’s
inverting input. At higher frequencies this capacitance will
tend to short the -INPUT to GND, resulting in a closed loop
gain which increases with frequency. This will cause
excessive high frequency peaking and potentially other
problems as well.

An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.

Driving Capacitive Loads

Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be

5

Evaluation Board

The performance of the HFA1113 may be evaluated using
the HFA11XX Evaluation Board, slightly modified as follows:

1. Remove the 500Ω feedback resistor (R
connection open.

2. a. For A

resistor (R

b. For A

= +1 evaluation, remove the 500Ω gain setting

V

), and leave pin 2 floating.

1

=+2, replace the 500Ω gain setting resistor with

V

a 0Ω resistor to GND.

The modified schematic and layout of the board are shown
in Figures 2 and 3.

To order evaluation boards (part number HFA11XXEVAL),
please contact your local sales office.

NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part Number
08-350000-10.

), and leave the

2

HFA1113

.

∞ (A

= +1)

V

OR 0Ω (A

IN

= +2)

V

V

R

1

1

50Ω

0.1µF0µF

2
3
4

-5V

8
7
6
5

GND

H

50Ω

GND

FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC

TOP LAYOUT

V

H

1

+IN

OUT

V

L

V+

V-

GND

BOTTOM LAYOUT

OUT
V

L

between the positive and negative inputs. This buffer forces

-IN to track +IN, and sets up a slewing current of:

- V

(V

-IN

10µF0.1µF

+5V

This current is mirrored onto the high impedance node (Z) by
Q

X3-QX4

)/RF + V

OUT

-IN/RG

, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by Q

and QN4. Note that when the output reaches its

P4

quiescent value, the current flowing through -IN is reduced to
only that small current (-I

) required to keep the output at

BIAS

the final voltage.
Tracing the path from V

clamp voltage on the high impedance node. V
by 2V

+IN

BE(QN6

and QP6) to set up the base voltage on QP5.

Q

P3

Q

P1

V­V+

Q

N1

to Z illustrates the effect of the

H

V+

Q

P4

Q

N2

I

CLAMP

Q

P2

Z

+1

Q

N5

Q

Q

H

50K
(30K

FOR VL)

N6

P6

decreases

R

1

200Ω

V

H

FIGURE 3. EVALUATION BOARD LAYOUT

Limiting Operation

General

The HFA1113 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the V

5) of the amplifier. V

sets the upper output limit, while V

H

sets the lower clamp level. If the amplifier tries to drive the
output above V
output voltage at V

, or below VL, the clamp circuitry limits the

H

or VL (± the clamp accuracy),

H

respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.

Clamp Circuitry

Figure 4 shows a simplified schematic of the HFA1113 input
stage, and the high clamp (V
feedback amplifiers, there is a unity gain buffer (Q

and VL terminals (pins 8 and

H

) circuitry. As with all current

H

- QX2)

X1

L

Q

Q

N3

V

V-

300Ω

-IN

R
(INTERNAL)

-IN

P5

Q

N4

G

RF= 300Ω

(INTERNAL)

V

OUT

FIGURE 4. HFA1113 SIMPLIFIED VH CLAMP CIRCUITRY

begins to conduct whenever the high impedance node

Q

P5

reaches a voltage equal to Q

’s base voltage + 2VBE(Q

P5

P5

and QN5). Thus, QP5 clamps node Z whenever Z reaches
V

. R1 provides a pull-up network to ensure functionality

H

with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by V

.

L

When the output is clamped, the negative input continues to
source a slewing current (I
output to the quiescent voltage defined by the input. Q

) in an attempt to force the

CLAMP

P5

must sink this current while clamping, because the -IN
current is always mirrored onto the high impedance node.
The clamping current is calculated as:

I

CLAMP

= (V

- V

-IN

OUT CLAMPED

)/300Ω + V

-IN/RG

.

As an example, a unity gain circuit with VIN = 2V, and VH=1V,
would have I
(R

= ∞ because -IN is floated for unity gain applications).

G

Note that I

CLAMP

CC

= (2V - 1V)/300Ω + 2V/∞ = 3.33mA

will increase by I

when the output is

CLAMP

clamp limited.

6