Intersil Corporation HFA1103 Datasheet

HFA1103

Data Sheet March 1999

200MHz, Video Op Amp with High Speed Sync Stripper

The HFA1103 is a high-speed, wideband, fast settling current feedback op amp with a sync stripping function. The HFA1103 is a basic op amp with a modiﬁed output stage that enables it to strip the sync from a component video signal. The output stage has an open emitter NPN transistor that prevents the output from going low during the sync pulse. Removing the sync signal beneﬁts digitizing systems because only the active video information is applied to the A/D converter. This enables the full dynamic range of the A/D converter to be used to process the video signal. The HFA1103 includes inverting input bias current adjust pins (pins 1 and 5) for adjusting the output offset voltage.

Ordering Information

PART NUMBER

(BRAND)

HFA1103IB (H1103I)

TEMP.

RANGE (oC) PACKAGE

-40 to 85 8 Ld SOIC M8.15

PKG.

NO.

File Number 3957.3

Features

• Removes Sync Signal From Component Video

• Low Residual Sync. . . . . . . . . . . . . . . . . . . . . . 8mV (Typ)

• -3dB Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 200MHz

• Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . . 600V/µs

• Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . . 9ns

• Excellent Gain Flatness, 32MHz . . . . . . . . . . . . . . ±0.1dB

• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . <12ns

Applications

• RGB Video Sync Stripping

• RGB Video Distribution Ampliﬁer for Workstations and PC Networks

• Video Conferencing Systems

• RGB Video Monitor Preamp

• Fiberoptic Receivers

Sync Stripper Waveforms

0 TO

+0.7V

0 TO

-0.3V COMPONENT (RGB)

VIDEO INPUT

Application Schematic

+5V

4.7K

HFA1103

750

R 75

HFA1103 OUTPUT

Pinout

HFA1103

(SOIC)

TOP VIEW

V+

OUT

BAL

0 TO +0.7V

BAL

-IN

+IN

V-

OUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

HFA1103

Absolute Maximum Ratings Thermal Information

Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V

Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA

SUPPLY

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Speciﬁcations V

PARAMETER TEST CONDITIONS

DC CHARACTERISTICS

Residual Sync (Note 2) VIN = -300mV, AV = +1 25 - 8 10 mV

Output Offset Voltage (Notes 3, 5) 25 - 10 30 mV

Output Offset Voltage Drift (Note 3) Full - 10 - µV/oC VOS PSRR ∆VS = ±1.25V 25 39 45 - dB

Non-Inverting Input Bias Current +IN = 0V 25 - 5 40 µA

Inverting Input Bias Current -IN = 0V 25 - 5 50 µA

-I

Adjust Range (Notes 4, 6) 25 100 200 - µA

BIAS

Non-Inverting Input Resistance 25 25 50 - kΩ Inverting Input Resistance 25 - 16 30 Ω Input Capacitance 25 - 2 - pF Input Common Mode Range Full ±2.5 ±3.0 - V Input Noise Voltage 100kHz 25 - 4 - nV/√Hz +Input Noise Current 100kHz 25 - 18 - pA/√Hz

-Input Noise Current 100kHz 25 - 21 - pA/√Hz TRANSFER CHARACTERISTICS AV = +2, Unless Otherwise Speciﬁed Open Loop Transimpedance 25 - 500 - kΩ

-3dB Bandwidth V Gain Flatness To ±0.1dB 25 - 32 - MHz Minimum Stable Gain Full 1 - - V/V OUTPUT CHARACTERISTICS AV = +2, Unless Otherwise Speciﬁed Output Voltage (Note 3) 25, 85 2.5 3.0 - V

Output Current 25, 85 50 60 - mA

Linearity Near Zero 25 - 0.01 - % TRANSIENT RESPONSE AV = +2, Unless Otherwise Speciﬁed Rise Time V

= ±5V, AV = +2, RF = 750Ω, RL = 50Ω, Unless Otherwise Speciﬁed

SUPPLY

TEMP

(oC) MIN TYP MAX UNITS

Full - - 12 mV

Full - - 40 mV

Full 35 - - dB

Full - - 65 µA

Full - - 60 µA

= 1.0V

OUT

= 2.0V Step 25 - 2 - ns

OUT

, AV = +2 25 - 200 - MHz

P-P

-40oC 1.75 2.5 - V

-40oC35 50 - mA

HFA1103

Electrical Speciﬁcations V

PARAMETER TEST CONDITIONS

Overshoot V Slew Rate AV = +2, V

0.1% Settling V Overdrive Recovery Time 2X Overdrive 25 - 12 - ns

POWER SUPPLY CHARACTERISTICS

Supply Voltage Range Full ±4.5 - ±5.5 V Supply Current (No Load) 25 - 11 16 mA

NOTES:

2. The residual sync is specified at the output of a doubly terminated circuit (see page 1 of this data sheet).

3. Since the HFA1103 has an open emitter NPN output stage, this measurement is only valid for positive values.

4. The -I is an open emitter NPN transistor.

5. VOS includes the error contribution of I

6. This is the minimum change in inverting input bias current when a BAL pin is connected to V- through a 50Ω resistor.

current can be used to adjust the offset voltage to zero, but -I

BIAS

Test Circuit

50Ω

750Ω

= ±5V, AV = +2, RF = 750Ω, RL = 50Ω, Unless Otherwise Speciﬁed (Continued)

SUPPLY

TEMP

(oC) MIN TYP MAX UNITS

= 2.0V Step 25 - 10 - %

OUT

= 0 to 2V, +2V to 0V 25 - 600 - V/µs

OUT

= 2V to 0V 25 - 9 - ns

OUT

Full - - 23 mA

does not flow bidirectionally because the HFA1103 output stage

BIAS

at RF = 750Ω.

BSN

may cause oscillations. In most cases, the oscillation can be

DUT

OUT

avoided by placing a resistor in series with the output. Care must also be taken to minimize the capacitance to

ground seen by the ampliﬁer’sinverting input. The larger this capacitance, the worse the gain peaking, resulting in pulse

R 50Ω

overshoot and possible instability. To this end, it is recommended that the ground plane be removed under traces connected to pin 2, and connections to pin 2 should

FIGURE 1. TEST CIRCUIT

be kept as short as possible.

Application Information

Offset Adjustment

The HFA1103allowsf oradjustmentof the inverting input bias current to null the output offset voltage. -I R

, so any change in bias current forces a corresponding

change in output voltage. The amount of adjustment is a function of R

. With RF = 750Ω, the typical adjust range is

150mV. F or offset adjustment connect a 10kΩ potentiometer between pins 1 and 5 with the wiper connected to V-.

PC Board Layout

The frequency performance of these ampliﬁers depends a great deal on the amount of care taken in designing the PC board. The use of low inductance components such as

chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must!

Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value chip (0.1µF) capacitor works well in most cases.

Terminated microstrip signal lines are recommended at the input and output of the device. Output capacitance, such as that resulting from an improperly terminated transmission line will degrade the frequency response of the ampliﬁer and

flows through

BIAS

An example of a good high frequency layout is the Evaluation Board shown in Figure 3.

Evaluation Board

The HFA1100 series evaluation board may be used for the HFA1103 with minor modiﬁcations. The evaluation board may be ordered using part number HFA11XXEVAL. Please note that an HFA1103 sample is not included with the evaluation board and must be ordered separately.

The layout and schematic of the board are shown below:

-5V

500Ω

1 2 3 4

8 7 6 5

GND

50Ω

10µF0.1µF

OUT V

GND

500Ω

50Ω

0.1µF10µF

FIGURE 2. EVALUATION BOARD SCHEMATIC

+5V

+ 4 hidden pages