Intersil Corporation HD-6409 Datasheet

HD-6409

March 1997

Features

• Converter or Repeater Mode

• Independent Manchester Encoder and Decoder Operation

• Static to One Megabit/sec Data Rate Guaranteed

• Low Bit Error Rate

• Digital PLL Clock Recovery

• On Chip Oscillator

• Low Operating Power: 50mW Typical at +5V

• Available in 20 Lead Dual-In-Line and 20 Pad LCC Package

Ordering Information

TEMPERATURE

PACKAGE

PDIP -40oC to +85oC HD3-6409-9 E20.3 SOIC -40oC to +85oC HD9P6409-9 M20.3 CERDIP -40oC to +85oC HD1-6409-9 F20.3

DESC -55oC to 125oC 5962-9088801MRA F20.3

CLCC -40oC to +85oC HD4-6409-9 J20.A

DESC -55oC to 125oC 5962-9088801M2A J20.A

RANGE 1 MEGABIT/SEC

PKG.

NO.

CMOS Manchester Encoder-Decoder

Description

The HD-6409 Manchester Encoder-Decoder (MED) is a high speed, low power device man uf actured using self-aligned silicon gate technology. The device is intended for use in serial data communication, and can be operated in either of two modes. In the converter mode, the MED converts Non return-to-Zero code (NRZ) into Manchester code and decodes Manchester code into Nonreturn-to-Zero code. For serial data communication, Manchester code does not have some of the deﬁciencies inherent in Nonreturn-to-Zero code. For instance, use of the MED on a serial line eliminates DC components, provides clock recovery, and gives a relatively high degree of noise immunity. Because the MED converts the most commonly used code (NRZ) to Manchester code, the advantages of using Manchester code are easily realized in a serial data link.

In the Repeater mode, the MED accepts Manchester code input and reconstructs it with a recovered clock. This minimizes the effects of noise on a serial data link. A digital phase lock loop generates the recovered clock. A maximum data rate of 1MHz requires only 50mW of power.

Manchester code is used in magnetic tape recording and in ﬁber optic communication, and generally is used where data accuracy is imperative. Because it frames blocks of data, the HD-6409 easily interfaces to protocol controllers.

Pinouts

HD-6409 (CERDIP, PDIP, SOIC)

TOP VIEW

BZI

BOI

UDI

SD/CDS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207

SDO

SRST

NVM

DCLK

RST

GND

4 5 6 7 8 9

BOO

BZO

ECLK

CTS

13 12

SD/CDS

SDO

SRST

NVM

DCLK

5-1

HD-6409 (CLCC)

TOP VIEW

UDI

BOI

BZI

3212019

10 11 12 139

GND

RST

VCCBOO

BZO

ECLK

CTS

File Number 2951.1

Block Diagram

HD-6409

SDO NVM

BOI

BZI

UDI

RST

SD/CDS

RESET

Logic Symbol

DAT A

INPUT

LOGIC

OSCILLATOR

EDGE

DETECTOR

5-BIT SHIFT

AND DECODER

INPUT/ OUTPUT SELECT

COUNTER

CIRCUITS

COMMAND

SYNC

GENERATOR

MANCHESTER

ENCODER

OUTPUT SELECT

LOGIC

BOO

BZO

CTS

SRST

ECLK DCLK

SD/CDS

ECLK

RST

SDO

DCLK

NVM

SRST

17 11

5 8 7

CLOCK

GENERATOR

ENCODER

CONTROL

DECODER

BOO

BZO

CTS

BOI

BZI

UDI

5-2

HD-6409

Pin Description

NUMBER TYPE SYMBOL NAME DESCRIPTION

1 I BZl Bipolar Zero Input Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II

encoded data to the decoder, BZI and BOl are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high.

2 I BOl Bipolar One Input Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II

encoded data to the decoder, BOI and BZI are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low.

3 I UDI Unipolar Data Input An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input

Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2 (BOl) for data input, UDI must be held low.

4 I/O SD/CDS Serial Data/Com-

mand Data Sync

5 O SDO Serial Data Out The decoded serial NRZ data is transmitted out synchronously with the decoder

6OSRST Serial Reset In the converter mode,SRST followsRST. In the repeater mode, when RST goes

7ONVM Nonvalid Manchester A low on NVM indicates that the decoder has received invalid Manchester data

8 O DCLK Decoder Clock The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchro-

9IRST Reset In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low.

10 I GND Ground Ground 11 O C 12 I I

13 O O

14 I MS Mode Select MS must be held low for operation in the converter mode, and high for operation

15 I CTS Clear to Send In the converter mode, a high disables the encoder, forcing outputsBOO,BZO high

16 O ECLK Encoder Clock In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data

Clock Output Buffered output of clock input IX. May be used as clock signal for other peripherals.

Clock Input IX is the input for an external clock or, if the internal oscillator is used, IX and O

Clock Drive If the internal oscillator is used, OX and IX are used for the connection of the crys-

In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ data is accepted synchronously on the falling edge of encoder clock output (ECLK). In the repeater mode, SD/CDS is an output indicating the status of last valid sync pattern received. A high indicates a command sync and a low indicates a data sync pattern.

clock (DCLK). SDO is forced low when RST is low.

low, SRST goes low and remains low afterRST goes high.SRST goes high only when RST is high, the reset bit is zero, and a valid synchronization sequence is received.

and present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and data were valid and SDO is valid.NVM is set low by a low onRST, and remains low after RST goes high until valid sync pulse followed by two valid Manchester bits is received.

nously output received NRZ data (SDO).

A high on RST enables SDO and DCLK, and forces SRST high. NVM remains low after RST goes high until a valid sync pulse followed by two Manchester bits is received, after which it goes high. In the repeater mode, RST has the same effect on SDO, DCLK and NVM as in the converter mode. When RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero and a valid synchronization sequence is received.

are used for the connection of the crystal.

tal.

in the repeater mode.

and ECLK low. A high to low transition ofCTS initiates transmission of a Command sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode, the function ofCTS is identical to that of the converter mode with the exception that a transition of CTS does not initiate a synchronization sequence.

to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl data by the digital phase locked loop.

5-3

HD-6409

Pin Description

NUMBER TYPE SYMBOL NAME DESCRIPTION

17 I SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock frequency while a

low sets the data rate at 1/16 times the clock frequency.

18 O BZO BipolarZero Output BZO and its logical complement BOO are the Manchester data outputs of the en-

coder. The inactive state for these outputs is in the high state. 19 O BOO Bipolar One Out See pin 18. 20 I V

NOTE: (I) Input (O) Output

VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin-

20) to GND (pin-10) is recommended.

Encoder Operation

The encoder uses free running clocks at 1X and 2X the data rate derived from the system clock l is used to control the encoder outputs, ECLK,

for internal timing. CTS

BOO and BZO. A free running 1X ECLK is transmitted out of the encoder to drive the external circuits which supply the NRZ data to the MED at pin SD/CDS.

A low on

CTS enables encoder outputs ECLK, BOO and BZO, while a high on CTS forces BZO, BOO high and holds ECLK low. When

CTS goes from high to low , a synchro-

nization sequence is transmitted out on

BOO and BZO. A

synchronization sequence consists of eight Manchester “0”

CTS

ECLK

SD/CDS

‘1’ ‘0’ ‘1’

BZO

‘1’ ‘0’ ‘1’

BOO

0000 0000

bits followed by a command sync pulse. A command

sync pulse is a 3-bit wide pulse with the ﬁrst 1 1/2 bits high followed b y 1 1/2 bits low. Serial NRZ data is clocked into

the encoder at SD/CDS on the high to low transition of ECLK during the command sync pulse. The NRZ data received is encoded into Manchester II data and transmitted out on BOO and BZO following the command sync pulse. Fol-

lowing the synchronization sequence, input data is encoded and transmitted out continuously without parity check or word framing. The length of the data block encoded is deﬁned by

DON’T CARE

EIGHT “0’s”

CTS. Manchester data out is inverted.

COMMAND

SYNC

CE6

FIGURE 1. ENCODER OPERATION

Decoder Operation

The decoder requires a single clock with a frequency 16X or 32X the desired data rate. The rate is selected on the speed select with SS low producing a 16X clock and high a 32X clock. For long data links the 32X mode should be used as this permits a wider timing jitter margin. The internal operation of the decoder utilizes a free running clock synchronized with incoming data for its clocking.

The Manchester II encoded data can be presented to the decoder in either of two ways. The Bipolar One and Bipolar

SYNCHRONIZATION SEQUENCE

CE5

Zero inputs will accept data from differential inputs such as a comparator sensed transformer coupled bus. The Unipolar Data input can only accept noninverted Manchester II encoded data i.e.

Bipolar One Out through an inverter to Unipolar Data Input. The decoder continuously monitors this data input for valid sync pattern. Note that while the MED encoder section can generate only a command sync pattern, the decoder can recognize either a command or data sync pattern. A data sync is a logically inverted command sync.

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