Datasheet HD-6408 Datasheet (Intersil Corporation)

March 1997

HD-6408

CMOS Asynchronous Serial

Manchester Adapter (ASMA)

Features

• Low Bit Error Rate

• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1MBit/s

• Sync Identification and Lock-In

• Clock Recovery

• Manchester II Encoder, Decoder

• Separate Encode and Decode

• Low Operating Power . . . . . . . . . . . . . . . . .50mW at 5V

• Single Power Supply

• 24 Lead Package

Ordering Information

PART

PACKAGE TEMP. RANGE

PDIP -40oC to +85oC HD3-6408-9 E24.6
CERDIP -40oC to +85oC HD1-6408-9 E24.6

NUMBER

PKG.

NO.

Pinout

Description

The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder
for creating a very high speed asynchronous serial data bus.
The Encoder converts serial NRZ data (typically from a shift
register) to Manchester II encoded data, adding a sync pulse
and parity bit. The Decoder recognizes this sync pulse and
identifies it as a Command Sync or a Data Sync. The data is
then decoded and shifted out in NRZ code (typically into a
shift register). Finally, the parity bit is checked. If there were
no Manchester or parity errors the Decoder responds with a
valid word signal. The Decoder puts the Manchester code to
full use to provide clock recovery and excellent noise immu­nity at these very high speeds.

The HD-6408 can be used in many commercial applications
such as security systems, environmental control systems,
serial data links and many others. It utilizes a single 12 x
clock and achieves data rates of up to one million bits per
second with a very minimum overhead of only 4 bits out of
20, leaving 16 bits for data.

HD-6408 (DIP)

TOP VIEW

1

VW

2

ESC

3

TD

4

SDO

5

DC

6

BZI

7

BOI

8

UDI

9

DSC

10

CDS

11

DR

12

GND

d

24

V

CC

23

EC

22

SCI

21

SD

20

SS

19

EE

18

SDI

17

BOO

16

OI

15

BZO

14

DBS

13

MR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

5-1

File Number 2952.1

Block Diagrams

23

EC

22

SCI

ESC

SD

SS

SDI

÷ 2

2

21

20

18

SYNC

PARITY

DAT A

HD-6408

ENCODER DECODER

11

BIT COUNTER

RESET

CHARACTER

÷ 6

COUNT

DECODER

FORMER

19

EE

14

DBS

13

MR

15

BZO

16

OI

17

BOO

DR

VW

TD

CDS

DC

DSC

BZI

BOI
UDI

1

3

10

5

SYNCHRO-

9

6
7

TRANSITION

8

VALID
WORD
LATCH

CLOCK

NIZER

FINDER

LATCH

SYNC

BIT COUNTER

VALID

WORD

TEST

CIRCUIT

CHARACTER

IDENTIFIER

PARITY
CHECK

NRZ

OUTPUT

PORT

4

SDO

5-2

HD-6408

Pin Description

PIN TYPE SYMBOL SECTION DESCRIPTION

1 O VW Decoder Output high indicates receipt of a VALID WORD.
2 O ESC Encoder ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The En-

coder samples SDI on the low-to-high transition of ESC.

3 O TD Decoder TAKE DATA output is high during receipt of data after identification of a sync pulse

and two valid Manchester data bits.
4 O SDO Decoder SERIAL DATA OUT delivers received data in correct NRZ format.
5 I DC Decoder DECODER CLOCK input drives the transition finder, and the synchronizer which

in turn supplies the clock to the balance of the Decoder. Input a frequency equal to

12X the data rate.
6 I BZI Decoder A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative

state. This pin must be held high when the Unipolar input is used.
7 I BOI Decoder A high input should be applied to BIPOLAR ONE IN when the bus is in its positive

state, this pin must be held low when the Unipolar input is used.
8 I UDI Decoder With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition

finder circuit. If not used this input must be held low.
9 O DSC Decoder DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK ÷ 12),

synchronized by the recovered serial data stream.

10 O CDS Decoder COMMAND/DATA SYNC output high occurs during output of decoded data which

was preceded by a Command synchronizing character. A low output indicates a

Data synchronizing character.

11 I DR Decoder A high input to DECODER RESET during a rising edge of DECODER SHIFT

CLOCK resets the decoder bit counting logic to a condition ready for a new word.

12 I GND Both GROUND supply pin.
13 I MR Both A high on MASTER RESET clears the 2:1 counters in both the encoder and decod-

er and the ÷ 6 counter.

14 O DBS Encoder DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER

CLOCK.

15 O BZO Encoder BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative

sense of a bipolar line driver.

16 I OI Encoder A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states.
17 O BOO Encoder BIPOLAR ONE OUT is an active low output designed to drive the one or positive

sense of a bipolar line driver.

18 I SDI Encoder SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER

SHIFT CLOCK.

19 I EE Encoder A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preced-

ing cycle being completed).

20 I SS Encoder SYNC SELECT actuates a Command sync for an input high and data sync for an

input low.

21 O SD Encoder SEND DATA is an active high output which enables the external source of serial

data.

22 I SCI Encoder SEND CLOCK IN is 2X the Encoder data rate.
23 I EC Encoder ENCODER CLOCK is the input to the 6:1 divider.
24 I V

CC

Both VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 24)

to GND (pin 12) is recommended.

5-3

Encoder Operation

HD-6408

The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SClock input. An
auxiliary divide by six counter is provided on chip which can
be utilized to produce the SClock by dividing the DClock.

The Encoder’s cycle begins when EE is high during a falling
edge of ESC (1). This cycle lasts for one word length or
twenty ESC periods. At the next low-to-high transition of the
ESC, a high at SS input actuates a Command sync or a low
will produce a Data sync for that word (2). When the Encoder
is ready to accept data, the SD output will go high and
remain high for sixteen ESC periods (3) - (4).

TIMING

SCI

ESC

EE

0 1 2 3 4 5 6 7 15 16 17

DON’T CARE

During these sixteen periods the data should be clocked into
the SD Input with every high-to-low transition of the ESC (3)

- (4). After the sync and Manchester II encoded data are
transmitted through the

BOO and BZO outputs, the Encoder
adds on an additional bit which is the (odd) parity for that
word (5). If ENCODER ENABLE is held high continuously,
consecutive words will be encoded without an interframe
gap. ENCODER ENABLE must go low by time (5) as shown
to prevent a consecutive word from being encoded. At any
time a low on

OI will force both bipolar outputs to a high state

but will not affect the Encoder in any other way.
To Abort the Encoder transmission a positive pulse must be

applied at MR. Any time after or during this pulse, a low-to­high transition on SCI clears the internal counters and initial­izes the Encoder for a new word.

1918

SS

SD

SDI

BOO

BZO

VALID

1ST HALF

DON’T CARE

3 210101112131415

32101112131415 P2ND HALF

32101112131415 PSYNCSYNC

4 52 31

5-4

Decoder Operation

HD-6408

The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DClock input. The
Manchester II coded data can be presented to the Decoder
in one of two ways. The BOI and BZI inputs will accept data
from a differential output comparator. The UDI input can only
accept noninverted Manchester II coded data (e.g. from
BOO of an Encoder through an inverter to UDI).

The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized (1), the type of sync is indicated by the
CDS output. If the sync character was a command, this out­put will go high (2) and remain high for sixteen DSC periods
(3), otherwise it will remain low. The TD output will go high
and remain high (2) - (3) while the Decoder is transmitting
the decoded data through SDO.

TIMING

DSC

0 1 2 3 4 5 6 7 8 16 17 18 19

The decoded data available at SDO is in a NRZ format. The
DSC is provided so that the decoded bits can be shifted into
an external register on every low-to-high transition of this
clock (2) - (3). Note that DECODER SHIFT CLOCK may
adjust its phase up until the time that TAKE DATA goes high.

After all sixteen decoded bits have been transmitted (3) the
data is checked for odd parity. A high on VW output (4) indi­cates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is look­ing for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown (1).

At any time in the above sequence a high input on DR during
a low-to-high transition of DSC will abort transmission and ini­tialize the Decoder to start looking for a new sync character.

BOI

BZI

TD

CDS

SDO

VW

2ND HALF1ST HALF

SYNC SYNC1515 14 13 12 11 10

UNDEFINED

FROM PREVIOUS RECEPTION

14 13 12 11 10

15 14 13 12 4 3 2 1 0

21 3 4

21

0P21

0P

5-5

HD-6408

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC+0.3V

Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Thermal Information

Thermal Resistance (Typical) θ

JA

CERDIP Package . . . . . . . . . . . . . . . . 50oC/W 11oC/W

PDIP Package. . . . . . . . . . . . . . . . . . . 60oC/W N/A

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .456 Gates

θ

JC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range

HD-6408-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC

DC Electrical Specifications V

SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS

V

IH

V

IL

V

IHC

V

ILC

II Input Leakage -1.0 - +1.0 µAVIN = VCC or GND, DIP Pins

V

OH

V

OL

I

CCSB

I

CCOP

NOTE:

1. Guaranteed but not 100% tested.

Logical “1” Input Voltage 70% V
Logical “0” Input Voltage - 20% V
Logical “1” Input Voltage (Clock) VCC -0.5 - - V
Logical “0” Input Voltage (Clock) - GND +0.5 - V

Logical “1” Output Voltage 2.4 - - V IOH = -3mA
Logical “0” Output Voltage - - 0.4 V IOL = 1.8mA
Supply Current Standby - 0.5 2 mA VIN = VCC = 5.5V Outputs Open
Supply Current Operating (Note 1) - 8.0 10.0 mA VCC = 5.5V, f = 15MHz

= 5.0V ±10%, TA = -40oC to +85oC

CC

CC

--V

CC

-V

5-8, 11, 13, 16, 18, 19, 20, 22, 23

AC Electrical Specifications V

= 5.0V ±10%, TA = -40oC to +85oC

CC

SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS

ENCODER TIMING

(1) F

(2) F

(3) T

(4) T

(5) F

(6) T

(7) T

(8) T

(9) T

(10) T

(11) T

EC

ESC

ECR

ECF

ED

MR

E1

E2

E3

E4

E5

Encoder Clock Frequency 0 - 12 MHz CL = 50pF

Send Clock Frequency 0 - 2.0 MHz CL = 50pF

Encoder Clock Rise Time - - 8 ns CL = 50pF

Encoder Clock Fall Time - - 8 ns CL = 50pF

Data Rate 0 - 1.0 MHz CL = 50pF

Master Reset Pulse Width 150 - - ns CL = 50pF

Shift Clock Delay - - 125 ns CL = 50pF

Serial Data Setup 75 - - ns CL = 50pF

Serial Data Hold 75 - - ns CL = 50pF

Enable Setup 90 - - ns CL = 50pF

Enable Pulse Width 100 - - ns CL = 50pF

5-6

HD-6408

AC Electrical Specifications V

= 5.0V ±10%, TA = -40oC to +85oC (Continued)

CC

SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS

(12) T

(13) T

(14) T

(15) T

(16) T

(17) T

E6

E7

E8

E9

E10

E11

Sync Setup 55 - - ns CL = 50pF

Sync Pulse Width 150 - - ns CL = 50pF

Send Data Delay 0 - 50 ns CL = 50pF

Bipolar Output Delay - - 130 ns CL = 50pF

Enable Hold 10 - - ns CL = 50pF

Sync Hold 95 - - ns CL = 50pF

DECODER TIMING

(18) F

(19) T

(20) T

(21) F

(22) T

(23) T

DC

DCR

DCF

DD

DR

DRS

Decoder Clock Frequency 0 - 12 MHz CL = 50pF

Decoder Clock Rise Time - - 8 ns CL = 50pF

Decoder Clock Fall Time - - 8 ns CL = 50pF

Data Rate 0 - 1.0 MHz CL = 50pF

Decoder Reset Pulse Width 150 - - ns CL = 50pF

Decoder Reset Setup Time 75 - - ns CL = 50pF

(24) T

(25) T

(26) T

(27) T

(28) T

(29) T

(30) T

(31) T

(32) T

(33) T

(34) T

(35) T

(36) T

DRH

MR

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

Decoder Reset Hold Time 10 - - ns CL = 50pF

Master Reset Pulse Width 150 - - ns CL = 50pF

Bipolar Data Pulse Width TDC +10 - - ns Note 1, CL = 50pF

Sync Transition Span - 18T

DC

- ns Note 1, CL = 50pF

One Zero Overlap - - TDC -10 ns Note 1, CL = 50pF

Short Data Transition Span - 6T

Long Data Transition Span - 12T

DC

DC

- ns Note 1, CL = 50pF

- ns Note 1, CL = 50pF

Sync Delay (ON) -20 - 110 ns CL = 50pF

Take Data Delay (ON) 0 - 110 ns CL = 50pF

Serial Data Out Delay - - 80 ns CL = 50pF

Sync Delay (OFF) 0 - 110 ns CL = 50pF

Take Data Delay (OFF) 0 - 110 ns CL = 50pF

Valid Word Delay 0 - 110 ns CL = 50pF

NOTE:

1. TDC = Decoder Clock Period =1/FDC. (These parameters are guaranteed but not 100% tested).

Capacitance T

= +25oC

A

SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS

C

IN

Input Capacitance - 15 - pF FREQ = 1MHz, all mea-

surements are referenced

O

Output Capacitance - 15 - pF

to device GNDC

5-7

HD-6408

AC Testing Input, Output Waveform

INPUT

V

IH

V

IL

50%

50%

V

OH

V

OL

NOTE: AC Testing: All input signals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt.

Encoder Timing

SCI

ESC

SDI

SC

ESC

EE

SS

ESC

SD

SC

BOO OR BZO

TE2

(8)

VALID

(7)

TE1

TE3

(7)

TE1

(9)

(14)
TE8

(10)

TE4

(11)
TE5

VALID

TE10 (16)

(17)

TE11

(12)
TE6

VALID

TE7
(13)

(15)
TE9

5-8

Decoder Timing

BOI

BZI

BOI

BZI

T

D1

(26)

T

(26)

D1

HD-6408

NOTE: UI = 0, FOR NEXT DIAGRAMS

BIT PERIOD BIT PERIOD BIT PERIOD

T

D2

(27)

COMMAND SYNC

T

(27)

D2

DATA SYNC

T

D1

(26)

T

(26)

T

D1

T

(28)

D3

D3

(28)

T

D2

(27)

T
(27)

D2

T

T

D3

(28)

D3

(28)

BOI

BZI

T

(26)

D1

T

D3

T

(28)

D3

(28)

T

D4

(30) (30)

T

D5

(29)

T

(26)

D1

(28)

T

(28)

D3

T

D5

T

D3

T

D1

(26)

T

D4

ONEONE ZERO

(29)

T

(28)

D3

NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS

(27)

T

UI

D2

COMMAND SYNC

(27)

UI

UI

T

D4

(29)

T

D2

DATA SYNC

(30)
T

D5

ZERO ONE ONEONE

(30)

(27)
T

D2

(27)
T

D2

(29) (29)

T

D5

T

D4

T

D4

5-9

HD-6408

Decoder Timing

TD

TD

(31)
T

D6

T

D7

(32)

(33)
T

(34)
T

(35)

T

D10

D8

D9

DSC

CDS

DSC

SDO

DSC

CDS

(Continued)

DATA BIT

VW

DSC

DR

(36) T

(23) T

(22) T

(24) T

D11

DRS

DR

DRH

5-10

HD-6408

Decoder Timing

DSC

CDS

TD

DSC

SDO

DSC

CDS

TD

(31)

T

T

(33)

T

(34)

T

(35)

T

D6

D6

(32)

D8

D8

D10

(Continued)

DATA BIT

(34) T

VW

DSC

DR

(34) T

D11

D11

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

5-11