Intersil Corporation HD-6408 Datasheet

March 1997

HD-6408

CMOS Asynchronous Serial

Manchester Adapter (ASMA)

Features

• Low Bit Error Rate

• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1MBit/s

• Sync Identification and Lock-In

• Clock Recovery

• Manchester II Encoder, Decoder

• Separate Encode and Decode

• Low Operating Power . . . . . . . . . . . . . . . . .50mW at 5V

• Single Power Supply

• 24 Lead Package

Ordering Information

PART

PACKAGE TEMP. RANGE

PDIP -40oC to +85oC HD3-6408-9 E24.6
CERDIP -40oC to +85oC HD1-6408-9 E24.6

NUMBER

PKG.

NO.

Pinout

Description

The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder
for creating a very high speed asynchronous serial data bus.
The Encoder converts serial NRZ data (typically from a shift
register) to Manchester II encoded data, adding a sync pulse
and parity bit. The Decoder recognizes this sync pulse and
identifies it as a Command Sync or a Data Sync. The data is
then decoded and shifted out in NRZ code (typically into a
shift register). Finally, the parity bit is checked. If there were
no Manchester or parity errors the Decoder responds with a
valid word signal. The Decoder puts the Manchester code to
full use to provide clock recovery and excellent noise immu­nity at these very high speeds.

The HD-6408 can be used in many commercial applications
such as security systems, environmental control systems,
serial data links and many others. It utilizes a single 12 x
clock and achieves data rates of up to one million bits per
second with a very minimum overhead of only 4 bits out of
20, leaving 16 bits for data.

HD-6408 (DIP)

TOP VIEW

1

VW

2

ESC

3

TD

4

SDO

5

DC

6

BZI

7

BOI

8

UDI

9

DSC

10

CDS

11

DR

12

GND

d

24

V

CC

23

EC

22

SCI

21

SD

20

SS

19

EE

18

SDI

17

BOO

16

OI

15

BZO

14

DBS

13

MR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

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File Number 2952.1

Block Diagrams

23

EC

22

SCI

ESC

SD

SS

SDI

÷ 2

2

21

20

18

SYNC

PARITY

DAT A

HD-6408

ENCODER DECODER

11

BIT COUNTER

RESET

CHARACTER

÷ 6

COUNT

DECODER

FORMER

19

EE

14

DBS

13

MR

15

BZO

16

OI

17

BOO

DR

VW

TD

CDS

DC

DSC

BZI

BOI
UDI

1

3

10

5

SYNCHRO-

9

6
7

TRANSITION

8

VALID
WORD
LATCH

CLOCK

NIZER

FINDER

LATCH

SYNC

BIT COUNTER

VALID

WORD

TEST

CIRCUIT

CHARACTER

IDENTIFIER

PARITY
CHECK

NRZ

OUTPUT

PORT

4

SDO

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HD-6408

Pin Description

PIN TYPE SYMBOL SECTION DESCRIPTION

1 O VW Decoder Output high indicates receipt of a VALID WORD.
2 O ESC Encoder ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The En-

coder samples SDI on the low-to-high transition of ESC.

3 O TD Decoder TAKE DATA output is high during receipt of data after identification of a sync pulse

and two valid Manchester data bits.
4 O SDO Decoder SERIAL DATA OUT delivers received data in correct NRZ format.
5 I DC Decoder DECODER CLOCK input drives the transition finder, and the synchronizer which

in turn supplies the clock to the balance of the Decoder. Input a frequency equal to

12X the data rate.
6 I BZI Decoder A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative

state. This pin must be held high when the Unipolar input is used.
7 I BOI Decoder A high input should be applied to BIPOLAR ONE IN when the bus is in its positive

state, this pin must be held low when the Unipolar input is used.
8 I UDI Decoder With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition

finder circuit. If not used this input must be held low.
9 O DSC Decoder DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK ÷ 12),

synchronized by the recovered serial data stream.

10 O CDS Decoder COMMAND/DATA SYNC output high occurs during output of decoded data which

was preceded by a Command synchronizing character. A low output indicates a

Data synchronizing character.

11 I DR Decoder A high input to DECODER RESET during a rising edge of DECODER SHIFT

CLOCK resets the decoder bit counting logic to a condition ready for a new word.

12 I GND Both GROUND supply pin.
13 I MR Both A high on MASTER RESET clears the 2:1 counters in both the encoder and decod-

er and the ÷ 6 counter.

14 O DBS Encoder DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER

CLOCK.

15 O BZO Encoder BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative

sense of a bipolar line driver.

16 I OI Encoder A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states.
17 O BOO Encoder BIPOLAR ONE OUT is an active low output designed to drive the one or positive

sense of a bipolar line driver.

18 I SDI Encoder SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER

SHIFT CLOCK.

19 I EE Encoder A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preced-

ing cycle being completed).

20 I SS Encoder SYNC SELECT actuates a Command sync for an input high and data sync for an

input low.

21 O SD Encoder SEND DATA is an active high output which enables the external source of serial

data.

22 I SCI Encoder SEND CLOCK IN is 2X the Encoder data rate.
23 I EC Encoder ENCODER CLOCK is the input to the 6:1 divider.
24 I V

CC

Both VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 24)

to GND (pin 12) is recommended.

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Encoder Operation

HD-6408

The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SClock input. An
auxiliary divide by six counter is provided on chip which can
be utilized to produce the SClock by dividing the DClock.

The Encoder’s cycle begins when EE is high during a falling
edge of ESC (1). This cycle lasts for one word length or
twenty ESC periods. At the next low-to-high transition of the
ESC, a high at SS input actuates a Command sync or a low
will produce a Data sync for that word (2). When the Encoder
is ready to accept data, the SD output will go high and
remain high for sixteen ESC periods (3) - (4).

TIMING

SCI

ESC

EE

0 1 2 3 4 5 6 7 15 16 17

DON’T CARE

During these sixteen periods the data should be clocked into
the SD Input with every high-to-low transition of the ESC (3)

- (4). After the sync and Manchester II encoded data are
transmitted through the

BOO and BZO outputs, the Encoder
adds on an additional bit which is the (odd) parity for that
word (5). If ENCODER ENABLE is held high continuously,
consecutive words will be encoded without an interframe
gap. ENCODER ENABLE must go low by time (5) as shown
to prevent a consecutive word from being encoded. At any
time a low on

OI will force both bipolar outputs to a high state

but will not affect the Encoder in any other way.
To Abort the Encoder transmission a positive pulse must be

applied at MR. Any time after or during this pulse, a low-to­high transition on SCI clears the internal counters and initial­izes the Encoder for a new word.

1918

SS

SD

SDI

BOO

BZO

VALID

1ST HALF

DON’T CARE

3 210101112131415

32101112131415 P2ND HALF

32101112131415 PSYNCSYNC

4 52 31

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