Intersil Corporation HD-4702-883 Datasheet

HD-4702/883

June 1998

Features

• This Circuit is Processed in AccordancetoMIL-STD-883
and is Fully Conformant Under the Pro visions of
Paragraph 1. 2. 1.

• HD-4702/883 Provides 13 Commonly Used Bit Rates

• Uses a 2.4576MHz Crystal/Input for Standard
Frequency Output (16 Times Bit Rate)

• Low Power Dissipation

• Conforms to ElA RS-404

• One HD-4702/883 Controls up to Eight Transmission
Channels

• Initialization Circuit Facilitates Diagnostic Fault
Isolation

• On-Chip Input Pull-Up Circuit

Ordering Information

PART

NUMBER

HD1-4702/883 -55 to 125 CERDIP F16.3

TEMPERATURE

RANGE (oC) PACKAGE PKG. NO.

CMOS Programmable Bit Rate Generator

Description

The HD-4702/883 Bit Rate Generator provides the
necessary clock signals for digital data transmission sys­tems, such as a UART. It generates 13 commonly used bit
rates using an on-chip crystal oscillator or an external input.
For conventional operation generating 16 output clock
pulses per bit period, the input clock frequency must be

2.4576MHz (i.e., 9600 Baud x 16 x 16, since there is an
internal ÷ 16 prescaler). A lowerinput frequency will result in
a proportionally lower output frequency.

The HD-4702/883 can provide multi-channel operation with
a minimum of external logic by having the clock frequency
C

and the ÷ 8 prescaler outputs Q0,Q1,Q2available

O

externally. All signals have a 50% duty cycle except 1800
Baud, which has less than 0.39% distortion.

The four rate select inputs (S
the output (Z). See Truth Table for Rate Select Inputs for
select code and output bit rate. Two of the 16 select codes
for the HD-4702/883 do not select an internally generated
frequency, but select an input into which the user can feed
either a different frequency, or a static level (High or Low) to
generate “ZERO BAUD”.

The bit rates most commonly used in modern data terminals
(110,150, 300,1200, 2400 Baud) require that no more than
one input be grounded for the HD-4702/883, which is easily
achieved with a single 5-position switch.

) select which bit rate is at

0-S3

Pinout

The HD-4702/883 has an initialization circuit which
generates a master reset for the scan counter. This signal is
derived from a digital differentiator that senses the first high
level on the C
ECPis high, selecting the crystal input, CPmust be low. A
high level on C
Modes and Initialization below.

HD-4702/883 (CERDIP)

TOP VIEW

1

Q

0

2

Q

1

3

Q

2

4

E

CP

5

C

P

6

O

X

7

I

X

8

GND

input after the ECPinput goes low. When

P

would apply a continuous reset. See Clock

P

16

V

CC

15

I

M

14

S

0

13

S

1

12

S

2

11

S

3

10

Z

9

C

O

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

1

File Number 2955.2

Truth Table

HD-4702/883

TRUTH TABLE FOR RATE SELECT INPUTS

(Using 2.4576MHz Crystal)

S

NOTE:

1. 19200 Baud by connecting Q2 to IM.

S

S

3

2

LLLLMUX Input (lM)
L L L H MUX Input (lM)
L L H L 50 Baud
L L H H 75 Baud
L H L L 134.5 Baud
L H L H 200 Baud
L H H L 600 Baud

L H H H 2400 Baud
H L L L 9600 Baud
H L L H 4800 Baud
H L H L 1800 Baud
H L H H 1200 Baud
H H L L 2400 Baud
H H L H 300 Baud
H H H L 150 Baud
HHHH110 Baud

S

1

0

OUTPUT RATE (Z)

CLOCK MODES AND INITIALIZATION

I

X L Clocked from C

X H H Continuous Reset

X L Reset During First C

NOTE:

2. Actual output frequency is 16 times the indicated output
rate, assuming a clock frequency of 2.4576MHz.

H = HIGH Level
L = LOW Level
X = Don’t Care

E

X

CP

H L Clocked from I

= Clock Pulse
= First HIGH Level Clock Pulse after ECPgoes LOW

C

P

OPERATION

X

P

= High Time

P

2

HD-4702/883

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Typical Derating Factor. . . . . . . . . . . . 1mA/MHz Increase in ICCOP

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range. . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may causepermanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

DC PARAMETER SYMBOL CONDITIONS

Thermal Resistance, (Typical, Note 3) θJA (oC/W) θJC (oC/W)

CERDIP Package . . . . . . . . . . . . . . 78 23

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 175oC

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .720 Gates

GROUP A

SUB-

GROUPS

TEMPERATURE

(oC) MIN MAX UNITS

Input High Voltage V
Input Low Voltage V
Output High Voltage V

Output Low Voltage V

Input High Current I

Input Low Current
(IX Input)

Input Low Current
(All Other Inputs)

Output High Current

I

(OX)

Output High Current

I

(All Other Outputs)

Output High Current

I

(All Other Outputs)

VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 VCC 70% - V

IH

VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - VCC 30% V

IL

OH1IOH

(Note 4)

OL1IOL

(Note 4)
VIN=VCC. AllOther Pins =0V,

IH

VCC = 5.5V

I

VIN= 0V, AllOtherPins = VCC,

ILX

VCC = 5.5V

I

VIN= 0VAllOther Pins = VCC,

lL

VCC = 5.5V (Note 5)

OHX

V
Input at 0V or VCC per Logic
Function or Truth Table

OH1

V
Input at 0V or VCC per Logic
Function or Truth Table

OH2

V
Input at 0V or VCC per Logic
Function or Truth Table

≤ -1µA, VCC = 4.5V,

≤ +1µA, VCC = 4 5V,

OUT=VCC

OUT

OUT

-0.5, VCC= 4.5V

= 2.5V, VCC = 4.5V

= VCC -0.5, VCC = 4.5V

1, 2, 3 -55 ≤ TA ≤ 125 VCC -0.1 - V

1, 2, 3 -55 ≤ TA ≤ 125 - 0.1 V

1, 2, 3 -55 ≤ TA ≤ 125 -1 +1 µA

1, 2, 3 -55 ≤ TA ≤ 125 -1 +1 µA

1, 2, 3 -55 ≤ TA ≤ 125 - -100 µA

1, 2, 3 -55 ≤ TA ≤ 125 -0.1 - mA

1, 2, 3 -55 ≤ TA ≤ 125 -1.0 - mA

1, 2, 3 -55 ≤ TA ≤ 125 -0.3 - mA

Output Low Current
(OX)

Output Low Current
(All Other Outputs)

I

OLX

I

V

= 0.4V, VCC = 4.5V

OUT

Input at 0V or VCC per Logic
Function or Truth Table

V

OL

= 0.4V, VCC = 4.5V

OUT

Input at 0V or VCC per Logic
Function or Truth Table

1, 2, 3 -55 ≤ TA ≤ 125 0.1 - mA

1, 2, 3 -55 ≤ TA ≤ 125 1.6 - mA

3