Intersil Corporation HD-15530 Datasheet
HD-15530
March 1997
Features
• Support of MlL-STD-1553
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . .50mW at 5V
Ordering Information
PACKAGE TEMP. RANGE 1.25 MEGABIT/s PKG. NO.
CERDIP -40oC to +85oC HD1-15530-9 F24.6
-55oC to +125oC HD1-15530-8
SMD# 7802901JA
CLCC -40oC to +85oC HD4-15530-9 J28.A
-55oC to +125oC HD4-15530-8
SMD# 78029013A
PDIP -40oC to +85oC HD3-15530-9 E24.6
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, e xcept f or the
Master Reset functions.
This circuit meets many of the requirements of MIL-STD-
1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmental control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
Pinouts
VALID WORD
ENCODER
SHIFT CLK
TAKE DATA
SERIAL DATA OUT
DECODER CLK
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLK
COMMAND/
DATA SYNC
DECODER RESET
HD-15530 (CERDIP, PDIP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
GND
12
24
V
CC
23
ENCODER CLK
22
SEND CLK IN
SEND DATA
21
SYNC SELECT
20
ENCODER ENABLE
19
SERIAL DATA IN
18
17
BIPOLAR ONE OUT
16
OUTPUT INHIBIT
BIPOLAR
15
ZERO OUT
14
÷ 6 OUT
MASTER RESET
13
DECODER
CLK
NC
NC
BIPOLAR
ZERO IN
BIPOLAR
ONE IN
UNIPOLAR
DATA IN
DECODER
SHIFT CLK
5
6
7
8
9
10
11
HD-15530 (CLCC)
TOP VIEW
TAKE DATA
DATA OUT
3 2 14
DECODER
DATA SYNC
ENCODER
14 15 16 17 1812 13
RESET
SERIAL
COMMAND/
SHIFT CLK
VALID
WORD
GND
RESET
MASTER
CC
V
ENCODER
CLK
28 27 26
÷ 6 OUT
BIPOLAR
ZERO OUT
SEND
CLK IN
25
24
23
22
21
20
19
INHIBIT
OUTPUT
SEND
DAT A
NC
NC
SYNC
SELECT
ENCODER
ENABLE
SERIAL
DATA IN
BIPOLAR
ONE OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
5-142
File Number 2960.1
HD-15530
Block Diagrams
ENCODER DECODER
GND
12
MASTER RESET
13
SEND CLK IN
22
÷ 6 OUT
14
ENCODER
23
CLK
÷ 6
BIT
COUNTER
÷ 2
21
SEND
DAT A
ENCODER
SHIFT CLK
CHARACTER
FORMER
18 19 20
2
SERIAL
DATA IN
ENCODER
ENABLE
SYNC
SELECT
17
15
OUTPUT
INHIBIT
V
CC
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
24
16
UNIPOLAR
DATA IN
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
DECODER
CLK
MASTER
RESET
8
7
TRANSITION
FINDER
6
5
SYNCHRONIZER
13
DECODER
RESET
11
CHARACTER
IDENTIFIER
BIT
PARITY
RATE
CHECK
CLK
BIT
COUNTER
10
4
Pin Description
PIN
NUMBER TYPE NAME SECTION DESCRIPTION
1 O VALID WORD Decoder Output high indicates receipt of a valid word, (valid parity and no Manches-
ter errors).
2 O ENCODER SHIFT
CLOCK
3 O TAKE DATA Decoder Output is high during receipt of data after identification of a sync pulse and
4 O SERIAL DATA OUT Decoder Delivers received data in correct NRZ format.
5 I DECODER CLOCK Decoder Input drives the transition finder, and the synchronizer which in turn
6 I BIPOLAR ZERO IN Decoder A high input should be applied when the bus is in its negative state. This pin
7 I BIPOLAR ONE IN Decoder A high input should be applied when the bus is in its positive state. This pin
8 I UNLPOLAR DATA IN Decoder With pin 6 high and pin 7 low, this pin enters unipolar data into the tr ansition
9 O DECODER SHIFT
CLOCK
10 O COMMAND SYNC Decoder Output of a high from this pin occurs dur ing output of decoded data which
11 I DECODER RESET Decoder A high input to this pin during a rising edge of DECODER SHIFT CLOCK
12 I GROUND Both Ground Supply pin.
13 I MASTER RESET Both A high on this pin clears 2:1 counters in both Encoder and Decoder, and
14 O ÷ 6 OUT Encoder Output from 6:1 divider which is driven by the ENCODER CLOCK.
15 O BIPOLAR ZERO OUT Encoder An active low output designed to drive the zero or negative sense of a
16 I OUTPUT INHIBIT Encoder A low on this pin forces pin 15 and 17 high, the inactive states.
17 O BIPOLAR ONE OUT Encoder An active lo w output designed to drive the one or positiv e sense of a bipolar
Encoder Output for shifting data into the Encoder. The Encoder samples SDI on the
low-to-high transition of Encoder Shift Clock.
two valid Manchester data bits.
supplies the clock to the balance of the decoder, input a frequency equal to
12X the data rate.
must be held high when the Unipolar input is used.
must be held low when the Unipolar input is used.
finder circuit. If not used this input must be held low.
Decoder Output which delivers a frequency (DECODER CLOCK ÷ 12), synchro-
nized by the recovered serial data stream.
was preceded by a Command (or Status) synchronizing character. A low
output indicates a Data synchronizing character.
resets the decoder bit counting logic to a condition ready for a new word.
resets the ÷ 6 circuit.
bipolar line driver.
line driver.
3
TAKE
DAT A
COMMAND/
DATA SYNC
SERIAL
DATA OUT
VALID
WORD
91DECODER
SHIFT
CLK
5-143
HD-15530
Pin Description
PIN
NUMBER TYPE NAME SECTION DESCRIPTION
18 I SERIAL DATA IN Encoder Accepts a serial data stream at a data rate equal to ENCODER SHIFT
19 I ENCODER ENABLE Encoder A high on this pin initiates the encode cycle. (Subject to the preceeding
20 I SYNC SELECT Encoder Actuates a Command sync for an input high and Data sync for an input low.
21 O SEND DATA Encoder An active high output which enables the external source of serial data.
22 I SEND CLOCK IN Encoder Clock input at a frequency equal to the data rate X2, usually driven by ÷ 6
23 I ENCODER CLOCK Encoder Input to the 6:1 divider, a frequency equal to the data rate X12 is usually
24 I V
I = Input O = Output
(Continued)
CC
CLOCK.
cycle being complete.)
output.
input here.
Both VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from V
(pin 24) to GROUND (pin 12) is recommended.
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by dividing the DECODER CLOCK.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK .
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high SYNC SELECT input
actuates a command sync or a low will produce a data sync
for the word . When the Encoder is ready to accept data,
2
the SEND DATA output will go high and remain high for sixteen ENCODER SHIFT CLOCK periods . During these
3
sixteen periods the data should be clocked into the SERIAL
DATA input with every high-to-low transition of the
ENCODER SHIFT CLOCK so it can be sampled on the lowto-high transition - . After the sync and Manchester II
coded data are transmitted through the
3 4
BIPOLAR ONE and
BIPOLAR ZERO outputs, the Encoder adds on an additional
bit which is the parity for that word . If ENCODER
5
ENABLE is held high continuously, consecutive words will be
encoded without an interframe gap. ENCODER ENABLE
1
must go low by time as shown to prevent a consecutive
5
word from being encoded. At any time a low on
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
CC
OUTPUT
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
SYNC SELECT
SEND DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
3210TIMING
DON’T CARE
VALID DON’T CARE
1112131415 10
2ND HALF1ST HALF
SYNCSYNC
1 2 3 4 5
FIGURE 1.
1112131415
1112131415
0123
5-144
1915 16 17 187654
P0123
P0123
Decoder Operation
HD-15530
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The BIPOLAR
ONE and BIPOLAR ZERO inputs will accept data from a
comparator sensed transformer coupled bus as specified in
Military Spec 1553. The UNIPOLAR DATA input can only
accept non-inverted Manchester II coded data. (e.g. from
BIPOLAR ONE OUT of an Encoder through an inverter to
Unipolar Data Input).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized , the type of sync is indicated on
COMMAND/
DATA SYNC output. If the sync character was a
command sync, this output will go high and remain high
for sixteen DECODER SHIFT CLOCK periods , otherwise
1
2
3
it will remain low. The TAKE DATA output will go high and
remain high - while the Decoder is transmitting the
2 3
decoded data through SERIAL DATA OUT. The decoded
3210TIMING
DECODER
SHIFT CLK
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
TAKE DATA
2ND HALF1ST HALF
SYNCSYNC
data available at SERIAL DATA OUT is in NRZ format. The
DECODER SHIFT CLOCK is provided so that the decoded
bits can be shifted into an external register on every low-tohigh transition of this clock - . Note that DECODER
2 3
SHIFT CLOCK may adjust its phase up until the time that
TAKE DATA goes high.
After all sixteen decoded bits have been transmitted the
3
data is checked for odd parity. A high on VALID WORD
output indicates a successful reception of a word without
4
any Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown .
1
At any time in the above sequence a high input on
DECODER RESET during a low-to-high transition of
DECODER SHIFT CLOCK will abort transmission and initialize the Decoder to start looking for a new sync character.
8
1112131415
10
1112131415
10
16 17 18 197654
P012
P012
COMMAND/
DATA SYNC
SERIAL
DATA OUT
UNDEFINED
(FROM PREVIOUS RECEPTION)VALID WORD
1
2
FIGURE 2.
12131415
12340
3 4
5-145
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