Intersil Corporation HCTS75MS Datasheet

September 1995

HCTS75MS

Radiation Hardened

Dual 2-Bit Bistable Transparent Latch

Features

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K RAD (Si)

• SEP Effective LET No Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

/mg

-9

Errors/Bit-Day

(Typ)

• Dose Rate Survivability: >1 x 10

• Dose Rate Upset >10

RAD (Si)/s 20ns Pulse

RAD (Si)/s

• Latch-Up Free Under Any Conditions

• Military Temperature Range: -55

C to +125oC

• Signiﬁcant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• LSTTL Input Compatibility

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil HCTS75MS is a Radiation Hardened dual 2-bit bistable transparent latch. Each of the two latches are controlled by a separate enable input ( the output state.

The HCTS75MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCTS75MS is supplied in a 16 lead Ceramic ﬂatpack (K sufﬁx) or a SBDIP Package (D sufﬁx).

E) which are active low. E low latches

Pinouts

16 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T16, LEAD FINISH C

TOP VIEW

Q0 D0 D1

VCC

D0 D1 Q1

1 2

6 7

2 2

16 15

1 1

GND

2 2

16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C

TOP VIEW

Q0 D0 D1

VCC D0 D1 Q1

1 1 1 2

2 2 2

116 2 3 4 5 6 7 8

15 14 13 12 11 10

1 1 1 1

GND 2 2 2

Functional Diagram

2(6)

13(4)

LATCH 0

LE LE

Q0 Q1 Q1 E

Q0 Q0 Q1

16(1

1(11

Ordering Information

PART

NUMBER

HCTS75DMSR -55oC to +125oC Intersil Class

HCTS75KMSR -55oC to +125oC Intersil Class

HCTS75D/ Sample

HCTS75K/ Sample

HCTS75HMSR +25oC Die Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207

TEMPERATURE

RANGE

SCREENING

LEVEL PACKAGE

16 Lead SBDIP

S Equivalent

16 Lead Ceramic

S Equivalent

Flatpack

+25oC Sample 16 Lead SBDIP

+25oC Sample 16 Lead Ceramic

Flatpack

470

3(7)

VCC

GND

DE Q Q

LH L H HH H L XL Q0 Q0

LE LE

LATCH 1

TRUTH TABLE

INPUTS OUTPUTS

Spec Number

File Number 3189.1

14(

15(

518625

Speciﬁcations HCTS75MS

Absolute Maximum Ratings Reliability Information

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (Soldering 10sec). . . . . . . . . . . . . . . . . . +265oC

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.

Operating Conditions

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . 100ns/V Max

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W

Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W

If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.7mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .8.8mW/oC

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V

Input High Voltage (VIH). . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC

(NOTE 1)

PARAMETER SYMBOL

Quiescent Current ICC VCC = 5.5V,

Output Current (Sink)

Output Current (Source)

Output Voltage Low VOL VCC = 5.5V, VIH = 2.75V,

Output Voltage High VOH VCC = 5.5V, VIH = 2.75V,

Input Leakage Current

IOL VCC = VIH = 4.5V,

IOH VCC = VIH = 4.5V,

IIN VCC = 5.5V, VIN = VCC or

CONDITIONS

VIN = VCC or GND

VOUT = 0.4V, VIL = 0V

VOUT = VCC - 0.4V, VIL = 0V

VIL = 0.8V, IOL = 50µA

VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, IOL = 50µA

VIL = 0.8V, IOH = -50µA

VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, IOH = -50µA

GND

GROUP

A SUB-

GROUPS TEMPERATURE

1 +25oC-20µA

2, 3 +125oC, -55oC - 400 µA

1 +25oC 4.8 - mA

2, 3 +125oC, -55oC 4.0 - mA

1 +25oC -4.8 - mA

2, 3 +125oC, -55oC -4.0 - mA

1, 2, 3 +25oC, +125oC,

-55oC

1, 2, 3 +25oC, +125oC,

-55oC

1, 2, 3 +25oC, +125oC,

-55oC

1, 2, 3 +25oC, +125oC,

-55oC

1 +25oC -0.5 +0.5 µA

2, 3 +125oC, -55oC -5.0 +5.0 µA

LIMITS

- 0.1 V

VCC -0.1 - V

UNITSMIN MAX

Noise Immunity Functional Test

NOTES:

1. All voltages referenced to device GND.

2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

FN VCC = 4.5V, VIH = 2.25V,

VIL = 0.8V (Note 2)

7, 8A, 8B +25oC, +125oC,

-55oC

471

--V

Spec Number 518625

Speciﬁcations HCTS75MS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP

(NOTES 1, 2)

PARAMETER SYMBOL

Propagation Delay D to Q

Propagation Delay E to Q

NOTES:

1. All voltages referenced to device GND.

2. Measurements made with RL = 500Ω, CL = 50pF, Input TR = TF = 3ns.

TPLH VCC = 4.5V, VIH = 3.0V,

TPHL VCC = 4.5V, VIH = 3.0V,

TPLH VCC = 4.5V, VIH = 3.0V,

TPHL VCC = 4.5V, VIH = 3.0V,

TPLH VCC = 4.5V, VIH = 3.0V,

TPHL VCC = 4.5V, VIH = 3.0V,

TPLH VCC = 4.5V, VIH = 3.0V,

TPHL VCC = 4.5V, VIH = 3.0V,

CONDITIONS

VIL = 0V

A SUB-

GROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

9 +25oC 2 19 ns

10, 11 +125oC, -55oC 2 24 ns

9 +25oC 2 27 ns

10, 11 +125oC, -55oC 2 35 ns

9 +25oC 2 23 ns

10, 11 +125oC, -55oC 2 29 ns

9 +25oC 2 19 ns

10, 11 +125oC, -55oC 2 22 ns

9 +25oC 2 21 ns

10, 11 +125oC, -55oC 2 25 ns

9 +25oC 2 20 ns

10, 11 +125oC, -55oC 2 23 ns

9 +25oC 2 24 ns

10, 11 +125oC, -55oC 2 29 ns

9 +25oC 2 28 ns

10, 11 +125oC, -55oC 2 34 ns

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Capacitance Power Dissipation

Input Capacitance CIN VCC = 5.0V, f = 1MHz 1 +25oC - 10 pF

Pulse Width Time TW VCC = 4.5V, VIH = 4.5V,

Setup Time TSU VCC = 4.5V, VIH = 4.5V,

Hold Time TH VCC = 4.5V, VIH = 4.5V,

Output Transition Time

NOTE:

1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.

CPD VCC = 5.0V, f = 1MHz 1 +25oC - 36 pF

1 +125oC, -55oC - 51 pF

1 +125oC, -55oC - 10 pF 1 +25oC - 16 ns

TTHL,

TTLH

VIL = 0.0V

VCC = 4.5V, VIH = 4.5V, VIL = 0.0V

1 +125oC, -55oC - 24 ns 1 +25oC - 12 ns 1 +125oC, -55oC - 18 ns 1 +25oC - 12 ns 1 +125oC, -55oC - 18 ns 1 +25oC15ns 1 +125oC, -55oC22ns

UNITSMIN MAX

472

Spec Number 518625

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