Intersil Corporation HCTS574MS Datasheet
August 1995
HCTS574MS
Radiation Hardened Octal D-Type
Flip-Flop, Three-State, Positive Edge Triggered
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
2
/mg
-9
Errors/Bit-
Day (Typ)
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
12
RAD (Si)/s
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Bus Driver O11utputs - 15 LSTTL Loads
• Military Temperature Range: -55
o
C to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS574MS is a Radiation Hardened non-inverting
octal D-type, positive edge triggered flip-flop with three-stateable
outputs. The HCTS574MS utilizes advanced CMOS/SOS
technology. The eight flip-flops enter data into their registers on
the LOW-to-HIGH transition of the clock (CP). Data is also
transferred to the outputs during this transition. The output
enable (
of the register operation. When the output enable is high, the
outputs are in the high impedance state.
The HCTS574MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
OE) controls the three-state outputs and is independent
Pinouts
OE
D0
D1
D2
Q3
Q4
D5
D6
Q7
GND
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
1
OE
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
8
D6
9
D7
GND
10
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20
TOP VIEW
120
2
3
4
5
6
7
8
9
10
VCC
20
Q0
19
Q1
18
Q2
17
Q3
16
Q4
15
Q5
14
Q6
13
12
Q7
11
CP
19
18
17
16
15
14
13
12
11
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
The HCTS574MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE
HCTS574DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP
HCTS574KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack
HCTS574D/Sample +25oC Sample 20 Lead SBDIP
HCTS574K/Sample +25oC Sample 20 Lead Ceramic Flatpack
HCTS574HMSR +25oC Die Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
694
Spec Number
File Number 2359.2
518629
Functional Diagram
HCTS574MS
1 OF 8
D
COMMON CONTROLS
CP
OE
INPUTS OUTPUTS
OE CP Dn Qn
LHH
LLL
LLXQ0
LHXQ0
FF
DQ
CP
TRUTH TABLE
Q
CE
HXXZ
H = High Level, L = Low Level, X = Immaterial, Z = High Impedance
= Transition from Low to High Level
Q0 = The level of Q before the indicated input conditions were established
695
Spec Number 518629
Specifications HCTS574MS
Absolute Maximum Ratings Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec). . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Rise and Fall Times at 4.5V VCC(TR, TF). . . . . . . . . . . 500ns Max.
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Thermal Resistance θ
SBDIP Package. . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.9mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .9.3mW/oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH). . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
JA
θ
JC
(NOTE 1)
PARAMETER SYMBOL
Quiescent Current ICC VCC = 5.5V,
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low VOL VCC = 4.5V, VIH = 2.25V,
Output Voltage High VOH VCC = 4.5V, VIH = 2.25V,
Input Leakage
Current
IOL VCC = 4.5V, VIH = 4.5V,
IOH VCC = 4.5V, VIH = 4.5V,
IIN VCC = 5.5V, VIN = VCC or
CONDITIONS
VIN = VCC or GND
VOUT = 0.4V, VIL = 0V
VOUT = VCC -0.4V,
VIL = 0V
IOL = 50µA, VIL = 0.8V
VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.8V
IOH = 50µA, VIL = 0.8V
VCC = 5.5V, VIH = 2.75V,
IOH = 50µA, VIL = 0.8V
GND
GROUP
A SUB-
GROUPS TEMPERATURE
1 +25oC-40µA
2, 3 +125oC, -55oC - 750 µA
1 +25oC 7.2 - mA
2, 3 +125oC, -55oC 6.0 - mA
1 +25oC -7.2 - mA
2, 3 +125oC, -55oC -6.0 - mA
1, 2, 3 +25oC, +125oC, -55oC - 0.1 V
1, 2, 3 +25oC, +125oC, -55oC - 0.1 V
1, 2, 3 +25oC, +125oC, -55oC VCC
1, 2, 3 +25oC, +125oC, -55oC VCC
1 +25oC-±0.5 µA
2, 3 +125oC, -55oC-±5.0 µA
LIMITS
-V
-0.1
-V
-0.1
UNITSMIN MAX
Three-State Output
Leakage Current
Noise Immunity
Functional Test
NOTES:
1. All voltages reference to device GND.
2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
IOZ Applied Voltage = 0V or
VCC, VCC = 5.5V
FN VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 2)
1 +25oC-±1 µA
2, 3 +125oC, -55oC-±50 µA
7, 8A, 8B +25oC, +125oC, -55oC---
696
Spec Number 518629
Specifications HCTS574MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
(NOTES 1, 2)
PARAMETER SYMBOL
Clock to Q TPLH,
TPHL
Enable to Ouptput TPZL VCC = 4.5V 9 +25oC 2 32 ns
TPZH VCC = 4.5V 9 +25oC 2 27 ns
Disable to Output TPLZ,
TPHZ
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
CONDITIONS
VCC = 4.5V 9 +25oC 2 29 ns
VCC = 4.5V 9 +25oC 2 23 ns
A SUB-
GROUPS TEMPERATURE
10, 11 +125oC, -55oC 2 36 ns
10, 11 +125oC, -55oC 2 39 ns
10, 11 +125oC, -55oC 2 32 ns
10, 11 +125oC, -55oC 2 28 ns
LIMITS
LIMITS
UNITSMIN MAX
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
Capacitance Power
Dissipation
Input Capacitance CIN VCC = 5.0V, FQ = 1MHz 1 +25oC - 10 pF
Output Transition
Time
Max Operating
Frequency
Setup Time Data to
Clock
Hold Time Data to
Clock
Pulse Width Clocks TW VCC = 4.5V 1 +125oC, -55oC16-ns
CPD VCC = 5.0V, FQ = 1MHz 1 +25oC - 39 pF
1 +125oC, -55oC - 57 pF
1 +125oC - 10 pF
TTHL
TTLH
FMAX VCC = 4.5V 1 +25oC - 30 MHz
TSU VCC = 4.5V 1 +125oC, -55oC12-ns
TH VCC = 4.5V 1 +125oC, -55oC5-ns
VCC = 4.5V 1 +25oC - 12 ns
1 +125oC, -55oC - 18 ns
1 +125oC, -55oC - 20 MHz
1 +125oC, -55oC18-ns
1 +125oC, -55oC5-ns
1 +125oC, -55oC24-ns
UNITSMIN MAX
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number 518629
697
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