Intersil Corporation HCTS374MS Datasheet

August 1995

HCTS374MS

Radiation Hardened Octal D-Type

Flip-Flop, Three-State, Positive Edge Triggered

Features

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K RAD (Si)

2

• SEP Effective LET No Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

/mg

-9

Errors/Bit-

Day (Typ)

12

• Dose Rate Survivability: >1 x 10

10

• Dose Rate Upset >10

RAD (Si)/s 20ns Pulse

RAD (Si)/s

• Latch-Up Free Under Any Conditions

• Fanout (Over Temperature Range)

- Bus Driver Outputs - 15 LSTTL Loads

o

• Military Temperature Range: -55

C to +125oC

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• LSTTL Input Compatibility

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil HCTS374MS is a Radiation Hardened non-inverting
octal D-type, positive edge triggered flip-flop with three-stateable
outputs. The eight flip-flops enter data into their registers on the
LOW-to-HIGH transition of the clock (CP). Data is also trans­ferred to the outputs during this transition. The output enable
(

OE) controls the three-state outputs and is independent of the
register operation. When the output enable is high, the outputs
are in the high impedance state.

The HCTS374MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.

Pinouts

OE

Q0
D0
D1
Q1
Q2
D2
D3
Q3

GND

20 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T20

TOP VIEW

1

OE
Q0

2

D0

3

D1

4

Q1

5

Q2

6

D2

7
8

D3

9

Q3

GND

10

20 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835 CDFP4-F20

TOP VIEW

120
2
3
4
5
6
7
8
9
10

VCC

20

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13
12

Q4

11

CP

19
18
17
16
15
14
13
12
11

VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP

The HCTS374MS is supplied in a 20 lead Ceramic flatpack (K
suffix) or a SBDIP Package (D suffix).

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE

HCTS374DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP
HCTS374KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack
HCTS374D/Sample +25oC Sample 20 Lead SBDIP
HCTS374K/Sample +25oC Sample 20 Lead Ceramic Flatpack
HCTS374HMSR +25oC Die Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

650

Spec Number

File Number 2134.2

DB NA

518635

Functional Diagram

HCTS374MS

(3, 4, 7, 8, 13, 14, 17, 18)

1 OF 8

CP
11

OE
1

OE CP Dn Qn

LHH

LLL

LLX Q0

D

COMMON CONTROLS

INPUTS OUTPUTS

FF

DQ

CP

TRUTH TABLE

OE

Q
(2, 5, 6, 9, 12, 15, 16, 19)

HXX Z

H =High Level (Steady State)
L =Low Level (Steady State)
X =Immaterial
Z =High Impedance

=Transition from Low to High Level

Q0 =The level of Q before the indicated input conditions were established

651

Spec Number 518635

Specifications HCTS374MS

Absolute Maximum Ratings Reliability Information

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (Soldering 10sec). . . . . . . . . . . . . . . . . . +265oC

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.

Operating Conditions

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

Input Rise and Fall Times at 4.5V VCC (TR, TF). . . . . . 500ns Max.

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W

Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.69W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W

If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.9mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .9.3mW/oC

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V

Input High Voltage (VIH). . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC

JA

θ

JC

(NOTE 1)

PARAMETER SYMBOL

Quiescent Current ICC VCC = 5.5V,

Output Current
(Sink)

Output Current
(Source)

Output Voltage Low VOL VCC = 4.5V, VIH = 2.25V,

Output Voltage High VOH VCC = 4.5V, VIH = 2.25V,

Input Leakage
Current

IOL VCC = 4.5V, VIH = 4.5V,

IOH VCC = 4.5V, VIH = 4.5V,

IIN VCC = 5.5V, VIN = VCC or

CONDITIONS

VIN = VCC or GND

VOUT = 0.4V, VIL = 0V

VOUT = VCC -0.4V,
VIL = 0V

IOL = 50µA, VIL = 0.8V

VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.8V

IOH = -50µA, VIL = 0.8V

VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.8V

GND

GROUP

A SUB-

GROUPS TEMPERATURE

1 +25oC-40µA

2, 3 +125oC, -55oC - 750 µA

1 +25oC 7.2 - mA

2, 3 +125oC, -55oC 6.0 - mA

1 +25oC -7.2 - mA

2, 3 +125oC, -55oC -6.0 - mA

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC VCC

1, 2, 3 +25oC, +125oC, -55oC VCC

1 +25oC-±0.5 µA

2, 3 +125oC, -55oC-±5.0 µA

LIMITS

-V

-0.1

-V

-0.1

UNITSMIN MAX

Three-State Output
Leakage Current

Noise Immunity
Functional Test

NOTES:

1. All voltages reference to device GND.

2. For functional tests VO ≥4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

IOZ Applied Voltage = 0V or

VCC, VCC = 5.5V

FN VCC = 4.5V, VIH = 2.25V,

VIL = 0.8V (Note 2)

1 +25oC-±1 µA

2, 3 +125oC, -55oC-±50 µA

7, 8A, 8B +25oC, +125oC, -55oC---

652

Spec Number 518635

Specifications HCTS374MS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP

(NOTES 1, 2)

PARAMETER SYMBOL

Clock to Q TPLH VCC = 4.5V 9 +25oC 2 27 ns

TPHL VCC = 4.5V 9 +25oC 2 31 ns

Enable to Output TPZL VCC = 4.5V 9 +25oC 2 32 ns

TPZH VCC = 4.5V 9 +25oC 2 26 ns

Disable to Output TPLZ,

TPHZ

NOTES:

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

CONDITIONS

VCC = 4.5V 9 +25oC 2 22 ns

A SUB-

GROUPS TEMPERATURE

10, 11 +125oC, -55oC 2 31 ns

10, 11 +125oC, -55oC 2 35 ns

10, 11 +125oC, -55oC 2 36 ns

10, 11 +125oC, -55oC 2 29 ns

10, 11 +125oC, -55oC 2 25 ns

LIMITS

UNITSMIN MAX

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Capacitance Power
Dissipation

Input Capacitance CIN VCC = 5.0V, f = 1MHz 1 +25oC - 10 pF

Output Transition
Time

Max Operating Fre­quency

Setup Time Data to
Clock

Hold Time Data to
Clock

Pulse Width Clock TW VCC = 4.5V 1 +25oC16-ns

CPD VCC = 5.0V, f = 1MHz 1 +25oC - 60 pF

1 +125oC, -55oC - 60 pF

1 +125oC - 10 pF

TTHL
TTLH

FMAX VCC = 4.5V 1 +25oC - 30 MHz

TSU VCC = 4.5V 1 +25oC12-ns

TH VCC = 4.5V 1 +25oC5-ns

VCC = 4.5V 1 +25oC - 12 ns

1 +125oC, -55oC - 18 ns

1 +125oC, -55oC - 20 MHz

1 +125oC, -55oC18-ns

1 +125oC, -55oC5-ns

UNITSMIN MAX

1 +125oC, -55oC24-ns

NOTE:

1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.

Spec Number 518635

653