Intersil Corporation HCTS373MS Datasheet

August 1995

HCTS373MS

Radiation Hardened

Octal Transparent Latch, Three-State

Features

• 3 Micron Radiation Hardened CMOS SOS

• Total Dose 200K RAD (Si)

2

• SEP Effective LET No Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

/mg

-9

Errors/Bit-

Day (Typ)

12

• Dose Rate Survivability: >1 x 10

10

• Dose Rate Upset >10

RAD (Si)/s 20ns Pulse

RAD (Si)/s

• Latch-Up Free Under Any Conditions

• Fanout (Over Temperature Range)

- Bus Driver Outputs - 15 LSTTL Loads

o

• Military Temperature Range: -55

C to +125oC

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• LSTTL Input Compatibility

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil HCTS373MS is a Radiation Hardened octal transpar­ent three-state latch with an active-low output enable. The out­puts are transparent to the inputs when the Latch Enable (
HIGH. When the Latch Enable (
latched. The Output Enable (
When the Output Enable (

OE) is HIGH, the outputs are in the

LE) goes LOW, the data is

OE) controls the three-state outputs.

high impedance state. The latch operation is independent of the
state of the Output Enable.

The HCTS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.

LE) is

Pinouts

OE

Q0
D0
D1
Q1
Q2
D2
D3
Q3

GND

20 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T20

TOP VIEW

1

OE
Q0

2

D0

3

D1

4

Q1

5

Q2

6

D2

7
8

D3

9

Q3

GND

10

20 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835 CDFP4-F20

TOP VIEW

120
2
3
4
5
6
7
8
9
10

VCC

20

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13
12

Q4

11

LE

19
18
17
16
15
14
13
12
11

VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE

The HCTS373MS is supplied in a 20 lead Ceramic flatpack (K
suffix) or a SBDIP Package (D suffix).

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE

HCTS373DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP
HCTS373KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack
HCTS373D/Sample +25oC Sample 20 Lead SBDIP
HCTS373K/Sample +25oC Sample 20 Lead Ceramic Flatpack
HCTS373HMSR +25oC Die Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

638

Spec Number

File Number 2131.2

DB NA

518636

Functional Diagram

HCTS373MS

1 OF 8

(3, 4, 7, 8, 13,

14, 17, 18)

D

COMMON CONTROLS

LE

(11)

OE

(1)

OE LE D Q

LHHH

LHLL

LATCH

DQ

LE

TRUTH TABLE

OE

(2, 5, 6, 9, 12,

Q

15, 16, 19)

LLIL

LLhH

HXXZ

H = High Level, L = Low Level
X = Immaterial, Z = High Impedance
I = Low voltage level prior to the high-to-low latch enable transition
h = High voltage level prior to the high-to-low latch enable transition

639

Spec Number 518636

Specifications HCTS373MS

Absolute Maximum Ratings Reliability Information

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (Soldering 10sec). . . . . . . . . . . . . . . . . . +265oC

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..

Operating Conditions

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . .500ns Max

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W

Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W

If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.9mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .9.3mW/oC

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V

Input High Voltage (VIH). . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC

JA

θ

JC

(NOTE 1)

PARAMETER SYMBOL

Quiescent Current ICC VCC = 5.5V,

Output Current
(Sink)

Output Current
(Source)

Output Voltage Low VOL VCC = 4.5V, VIH = 2.25V,

Output Voltage High VOH VCC = 4.5V, VIH = 2.25V,

Input Leakage
Current

IOL VCC = 4.5V, VIH = 4.5V,

IOH VCC = 4.5V, VIH = 4.5V,

IIN VCC = 5.5V, VIN = VCC or

CONDITIONS

VIN = VCC or GND

VOUT = 0.4V, VIL = 0V

VOUT = VCC - 0.4V,
VIL = 0V

IOL = 50µA, VIL = 0.8V

VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.8V

IOH = -50µA, VIL = 0.8V

VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.8V

GND

GROUP

A SUB-

GROUPS TEMPERATURE

1 +25oC-40µA

2, 3 +125oC, -55oC - 750 µA

1 +25oC 7.2 - mA

2, 3 +125oC, -55oC 6.0 - mA

1 +25oC -7.2 - mA

2, 3 +125oC, -55oC -6.0 - mA

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC VCC

1, 2, 3 +25oC, +125oC, -55oC VCC

1 +25oC-±0.5 µA

2, 3 +125oC, -55oC-±5.0 µA

LIMITS

-V

-0.1

-V

-0.1

UNITSMIN MAX

Output Tri State
Leakage

Noise Immunity
Functional Test

NOTES:

1. All voltages reference to device GND.

2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

IOZ VCC = 5.5V, VO = 0V or

VCC

FN VCC = 4.5V, VIH = 2.25V,

VIL = 0.8V (Note 2)

1 +25oC-±1.0 µA

2, 3 +125oC, -55oC ±50 µA

7, 8A, 8B +25oC, +125oC, -55oC---

640

Spec Number 518636

Specifications HCTS373MS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP

(NOTES 1, 2)

PARAMETER SYMBOL

Data to Qn TPLH VCC = 4.5V 9 +25oC 2 19 ns

TPHL VCC = 4.5V 9 +25oC 2 26 ns

LE to Qn TPLH VCC = 4.5V 9 +25oC 2 27 ns

TPHL VCC = 4.5V 9 +25oC 2 30 ns

Enable to Output TPZL VCC = 4.5V 9 +25oC 2 32 ns

TPZH VCC = 4.5V 9 +25oC 2 26 ns

Disable to Output TPLZ,

TPHZ

CONDITIONS

VCC = 4.5V 9 +25oC 2 22 ns

A SUB-

GROUPS TEMPERATURE

10, 11 +125oC, -55oC 2 24 ns

10, 11 +125oC, -55oC 2 30 ns

10, 11 +125oC, -55oC 2 30 ns

10, 11 +125oC, -55oC 2 34 ns

10, 11 +125oC, -55oC 2 36 ns

10, 11 +125oC, -55oC 2 29 ns

10, 11 +125oC, -55oC 2 25 ns

LIMITS

UNITSMIN MAX

NOTES:

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Capacitance Power
Dissipation

Input Capacitance CIN VCC = 5.0V, f = 1MHz 1 +25oC - 10 pF

Output Transition
Time

Setup Time Data to
LE

Hold Time Data to
LE

CPD VCC = 5.0V, f = 1MHz 1 +25oC - 57 pF

1 +125oC, -55oC - 57 pF

1 +125oC, -55oC - 10 pF

TTHL
TTLH

TSU VCC = 4.5V 1 +25oC13-ns

TH VCC = 4.5V 1 +25oC10-ns

VCC = 4.5V 1 +25oC - 12 ns

1 +125oC, -55oC - 18 ns

1 +125oC, -55oC20-ns

1 +125oC, -55oC15-ns

UNITSMIN MAX

Pulse Width LE TW VCC = 4.5V 1 +25oC16-ns

1 +125oC, -55oC24-ns

NOTE:

1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.

Spec Number 518636

641