Intersil Corporation HCTS112MS Datasheet

September 1995

HCTS112MS

Radiation Hardened

Dual J

K Flip-Flop

Features

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K RAD (Si)

• SEP Effective LET No Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

/mg

-9

Errors/

Bit-Day (Typ)

• Dose Rate Survivability: >1 x 10

• Dose Rate Upset >10

RAD (Si)/s 20ns Pulse

• Cosmic Ray Upset Rate 2 x 10

RAD (Si)/s

-9

Errors/Bit Day (Typ)

• Latch-Up Free Under Any Conditions

• Military Temperature Range: -55

C to +125oC

• Signiﬁcant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• LSTTL Input Compatibility

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil HCTS112MS is a Radiation Hardened dual JK ﬂip-ﬂop with set and reset. The ﬂip-ﬂop changes states with the negative transition of the clock (CP1N or CP2N).

The HCTS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

Pinouts

CP1

J1 S1 Q1 Q1 Q2

GND

16 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T16

TOP VIEW

VCC

CP1

S1 Q1

5 6

GND

16 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835 CDFP4-F16

TOP VIEW

116 2 3 4 5 6 7 8

16 15

CP2 K2

11 10

15 14 13 12 11 10

VCC R1 R2 CP2 K2 J2 S2 Q2

The HCTS112MS is supplied in a 16 lead Ceramic ﬂatpack (K sufﬁx) or a SBDIP Package (D sufﬁx).

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE

HCTS112DMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead SBDIP

HCTS112KMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead Ceramic Flatpack

HCTS112D/Sample +25oC Sample 16 Lead SBDIP

HCTS112K/Sample +25oC Sample 16 Lead Ceramic Flatpack

HCTS112HMSR +25oC Die Die

490

Spec Number

File Number 2467.2

DB NA

518603

Functional Diagram

3(11)

2(12)

4(10)

15(14)

HCTS112MS

P N

5 (9)

P N

6 (7)

1(13)

TRUTH TABLE

INPUTS OUTPUTS

S R CP J K Q Q

LHXXXHL

HLXXXLH

LLXXXH*H*

H H L L No Change

HH HLHL

HH LHLH

H H H H Toggle

H H H X X No Change

H = High Steady State, L = Low Steady State, X = Immaterial,

= High-to-Low Transition

* Output States Unpredictable if S and R Go High Simultaneously after Both being Low at the Same Time

491

Spec Number 518603

Speciﬁcations HCTS112MS

Absolute Maximum Ratings Reliability Information

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC

Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.

Operating Conditions

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . 100ns/V Max

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W

Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W

If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.7mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .8.8mW/oC

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V

Input High Voltage (VIH). . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC

(NOTE 1)

PARAMETER SYMBOL

Quiescent Current ICC VCC = 5.5V,

Output Current (Sink)

Output Current (Source)

Output Voltage Low VOL VCC = 4.5V, VIH = 2.25V,

Output Voltage High VOH VCC = 4.5V, VIH = 2.25V,

Input Leakage Current

IOL VCC = 4.5V, VIH = 4.5V,

IOH VCC = 4.5V, VIH = 4.5V,

IIN VCC = 5.5V, VIN = VCC or

CONDITIONS

VIN = VCC or GND

VOUT = 0.4V, VIL = 0V

VOUT = VCC - 0.4V, VIL = 0V

IOL = 50µA, VIL = 0.8V

VCC = 5.5V, VIH = 2.75V, IOL = 50µA, VIL = 0.8V

IOH = -50µA, VIL = 0.8V

VCC = 5.5V, VIH = 2.75V, IOH = -50µA, VIL = 0.8V

GND

GROUP

A SUB-

GROUPS TEMPERATURE

1 +25oC-20µA

2, 3 +125oC, -55oC - 400 µA

1 +25oC 4.8 - mA

2, 3 +125oC, -55oC 4.0 - mA

1 +25oC -4.8 - mA

2, 3 +125oC, -55oC -4.0 - mA

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC VCC

1 +25oC ±0.5 µA

2, 3 +125oC, -55oC ±5.0 µA

LIMITS

-V

-0.1

-V

-0.1

UNITSMIN MAX

Noise Immunity Functional Test

NOTES:

1. All voltages referenced to device GND.

2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

FN VCC = 4.5V, VIH = 2.25V,

VIL = 0.8V (Note 2)

7, 8A, 8B +25oC, +125oC, -55oC---

492

Spec Number 518603

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