Datasheet HCTS08MS Datasheet (Intersil Corporation)

August 1995

HCTS08MS

Radiation Hardened

Quad 2-Input AND Gate

Features

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K RAD(Si)

2

• SEP Effective LET No Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

/mg

-9

Errors/Bit-Day

(Typ)

• Dose Rate Survivability: >1 x 10

10

• Dose Rate Upset >10

RAD(Si)/s 20ns Pulse

12

Rads (Si)/Sec

• Latch-Up Free Under Any Conditions

o

• Military Temperature Range: -55

C to +125oC

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• LSTTL Input Compatibility

- VIL = 0.8V

- VIH = VCC/2

• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil HCTS08MS is a Radiation Hardened Quad 2-Input
AND Gate. A high on both inputs force the output to a High state.

The HCTS08MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCTS08MS is supplied in a 14 lead Ceramic Flatpack
Package (K suffix) or a 14 lead SBDIP Package (D suffix).

Ordering Information

PART

NUMBER

HCTS08DMSR -55oC to +125oC Intersil Class

HCTS08KMSR -55oC to +125oC Intersil Class

HCTS08D/
Sample

HCTS08K/
Sample

HCTS08HMSR +25oC Die Die

TEMPERATURE

RANGE

+25oC Sample 14 Lead SBDIP

+25oC Sample 14 Lead Ceramic

SCREENING

LEVEL PACKAGE

14 Lead SBDIP

S Equivalent

14 Lead Ceramic

S Equivalent

Flatpack

Flatpack

Pinouts

14 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T14

TOP VIEW

A1

1
2

B1

3

Y1

4

A2

5

B2

6

Y2

7

GND

14 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835 CDFP3-F14

TOP VIEW

1A1
B1
Y1
A2
B2
Y2

GND

An Bn Yn

LLL

LHL
HLL
HHH

NOTE: L = Logic Level Low, H = Logic level High

2
3
4
5
6
7

TRUTH TABLE

INPUTS OUTPUTS

14

VCC

13

B4

12

A4

11

Y4

10

B3

9

A3

8

Y3

14
13

12
11
10

9
8

Functional Diagram

(1, 4, 9, 12)

An

(2, 5, 10, 13)

Bn

VCC
B4
A4
Y4
B3
A3
Y3

(3, 6, 8, 11)

Yn

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

1

DB NA

Spec Number 518842

File Number 2136.2

Specifications HCTS08MS

Absolute Maximum Ratings Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC

Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..

Operating Conditions

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Input Rise and Fall Times at 4.5V VCC (TR, TF). . . . . 100ns/V Max

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 74oC/W 24oC/W

Ceramic Flatpack Package . . . . . . . . . . . 116oC/W 30oC/W

Maximum Package Power Dissipation at +125oC

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.66W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W

If device power e xceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.5mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .8.6mW/oC

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V

Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC

JA

θ

JC

(NOTE 1)

PARAMETERS SYMBOL

Quiescent Current ICC VCC = 5.5V,

Output Current
(Sink)

Output Current
(Source)

Output Voltage Low VOL VCC = 4.5V, VIH = 2.25V,

Output Voltage High VOH VCC = 4.5V, VIH = 2.25V,

Input Leakage
Current

IOL VCC = 4.5V, VIH = 4.5V,

IOH VCC = 4.5V, VIH = 4.5V,

IIN VCC = 5.5V, VIN = VCC or

CONDITIONS

VIN = VCC or GND

VOUT = 0.4V, VIL = 0V

VOUT = VCC -0.4V,
VIL = 0V

IOL = 50µA, VIL = 0.8V

VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.8V

IOH = -50µA, VIL = 0.8V

VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.8V

GND

GROUP

A SUB-

GROUPS TEMPERATURE

1 +25oC-10µA

2, 3 +125oC, -55oC - 200 µA

1 +25oC 4.8 - mA

2, 3 +125oC, -55oC 4.0 - mA

1 +25oC -4.8 - mA

2, 3 +125oC, -55oC -4.0 - mA

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC VCC

1, 2, 3 +25oC, +125oC, -55oC VCC

1 +25oC -0.5 +0.5 µA

2, 3 +125oC, -55oC -5.0 +5.0 µA

LIMITS

-V

-0.1

-V

-0.1

UNITSMIN MAX

Noise Immunity
Functional Test

NOTES:

1. All voltages reference to device GND.

2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

FN VCC = 4.5V,

VIH = 2.25V,
VIL = 0.8V, (Note 2)

7, 8A, 8B +25oC, +125oC, -55oC 4.0 0.5 -

2

Spec Number 518842

Specifications HCTS08MS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP

(NOTES 1, 2)

PARAMETER SYMBOL

Input to Output TPHL VCC = 4.5V 9 +25oC 2 18 ns

TPLH VCC = 4.5V 9 +25oC 2 20 ns

NOTES:

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Capacitance Power
Dissipation

Input Capacitance CIN VCC = 5.0V, f = 1MHz 1 +25oC - 10 pF

CPD VCC = 5.0V, f = 1MHz 1 +25oC - 45 pF

CONDITIONS

A SUB-

GROUPS TEMPERATURE

10, 11 +125oC, -55oC 2 20 ns

10, 11 +125oC, -55oC 2 22 ns

1 +125oC, -55oC - 80 pF

LIMITS

LIMITS

UNITSMIN MAX

UNITSMIN MAX

1 +125oC - 10 pF

Output Transition
Time

NOTE:

1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.

PARAMETERS SYMBOL

Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND +25oC - 0.2 mA

Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND,

Output Current (Source) IOH VCC = 4.5V, VIN = VCC or GND,

Output Voltage Low VOL VCC = 4.5V and 5.5V, VIH = VCC/2,

TTHL
TTLH

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

VCC = 4.5V 1 +25oC - 15 ns

1 +125oC - 22 ns

200K RAD LIMITS

(NOTES 1, 2)

CONDITIONS TEMPERA TURE

+25oC 4.0 - mA

VOUT = 0.4V

+25oC -4.0 - mA

VOUT = VCC -0.4V

+25oC - 0.1 V
VIL = 0.8V at 200K RAD,
IOL = 50µA

UNITSMIN MAX

Output Voltage High VOH VCC = 4.5V and 5.5V, VIH = VCC/2,

VIL = 0.8V at 200K RAD,
IOH = -50µA

Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC -5.0 +5.0 µA

+25oC VCC

-0.1

-V

Spec Number 518842

3

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

PARAMETERS SYMBOL

Specifications HCTS08MS

(NOTES 1, 2)

CONDITIONS TEMPERA TURE

200K RAD LIMITS

UNITSMIN MAX

Noise Immunity
Functional Test

Input to Output TPHL VCC = 4.5V +25oC 2 20 ns

NOTES:

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.

3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

COMFORMANCE GROUP MIL-STD-883 METHOD

Initial Test 100% 5004 1, 7, 9 1 (Note 2)
Interim Test 100% 5004 1, 7, 9, ∆ 1, ∆ (Note 2)
PDA 100% 5004 1, 7, ∆
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A (Note 1) Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆ 1, 2, 3, ∆ (Note 2)
Subgroup B6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 7, 9

NOTES:

1. Alternate Group A testing in accordance with MIL-STD-883 Method 5005 may be exercised.

2. Table 5 parameters only.

FN VCC = 4.5V, VIH = 2.25V,

VIL = 0.8V at 200K RAD, (Note 3)

TPLH VCC = 4.5V +25oC 2 22 ns

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)

GROUP B

PARAMETER

ICC 5 3µA

IOL/IOH 5 -15% of 0 Hour

TABLE 6. APPLICABLE SUBGROUPS

SUBGROUP DELTA LIMIT

+25oC ---

GROUP A SUBGROUPS

TESTED RECORDED

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

CONFORMANCE

GROUPS METHOD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4 (Note 1)

NOTE:

1. Except FN test which will be performed 100% Go/No-Go.

PRE RAD POST RAD PRE RAD POST RAD

Spec Number 518842

4

Specifications HCTS08MS

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS

OSCILLATOR

OPEN GROUND 1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V

STATIC BURN-IN I TEST CONDITIONS (Note 1)

3, 6, 8, 11 1, 2, 4, 5, 7, 9, 10, 12,

13

STATIC BURN-IN II TEST CONNECTIONS (Note 1)

3, 6, 8, 11 7 - 1, 2, 4, 5, 9, 10, 12,

DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)

- 7 3, 6, 8, 11 14 1, 2, 4, 5, 9, 10,

NOTES:

1. Each pin except VCC and GND will have a resistor of 10KΩ± 5% for static burn-in.

2. Each pin except VCC and GND will have a resistor of 1KΩ± 5% for dynamic burn-in.

TABLE 9. IRRADIATION TEST CONNECTIONS

OPEN GROUND VCC = 5V ± 0.5V

3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12, 13, 14

NOTE: Each pin except VCC and GND will have a resistor of 47KΩ± 5% for irradiation testing.

Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.

-14--

13, 14

50kHz 25kHz

--

-

12, 13

Spec Number 518842

5

HCTS08MS

Intersil Space Level Product Flow - ‘MS’

Wafer Lot Acceptance (All Lots) Method 5007

(Includes SEM)

GAMMA Radiation Verification (Each Wafer) Method 1019,

4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Temperature Cycle, Method 1010, Condition C,

10 Cycles
100% Constant Acceleration, Method 2001, Condition per

Method 5004
100% PIND, Method 2020, Condition A
100% External Visual
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,

NOTES:

1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.

2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the

3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.

4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.

5. Data Package Contents:

o

+125

C min., Method 1015

failures from subgroup 7.

• Cover Sheet (Intersil Name and/or Logo, P.O. Number , Customer Part Number, Lot Date Code, Intersil P art Number , Lot Number, Quan­tity).

• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.

• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number , Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.

• X-Ray report and film. Includes penetrometer measurements.

• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).

• Lot Serial Number Sheet (Good units serial number and lot number).

• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.

• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.

100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,

o

C min., Method 1015

+125
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125

o

Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)

C or

Spec Number 518842

6

HCTS08MS

AC Timing Diagrams

VIH

VS

VIL

VOH

VOL

VOH

VOL

PARAMETER HCTS UNITS

VCC 4.50 V

VIH 3.00 V

VS 1.30 V

INPUT

TPLH

VS

TTLH

20%

OUTPUT

80%

OUTPUT

FIGURE 1

AC VOLTAGE LEVELS

TPHL

80%

20%

TTHL

AC Load Circuit

DUT TEST

CL

CL = 50pF
RL = 500Ω

POINT

RL

FIGURE 2

VIL 0 V

GND 0 V

Spec Number 518842

7

Die Characteristics

DIE DIMENSIONS:

87 x 88 mils

2.20 x 2.24mm

METALLIZATION:

Type: SiAl
Metal Thickness: 11k

Å ± 1kÅ

GLASSIVATION:

Type: SiO

2

Thickness: 13kű 2.6kÅ

WORST CASE CURRENT DENSITY:

<2.0 x 10

5

A/cm

2

BOND PAD SIZE:

100µm x 100µm
4 mils x 4 mils

Metallization Mask Layout

HCTS08MS

HCTS08MS

B1 (2)

Y1 (3)

A2 (4)

B2 (5)

A1

(1) (14) (13)

VCC B4

(12) A4

(11) Y4

(10) B3

(9) A3

(6) (7) (8)
Y2 GND Y3

8

Spec Number 518842

HCTS08MS

Packaging

LEAD FINISH

c1

-A-

-B-

S

bbb C A - B

BASE

PLANE

SEATING

PLANE

S1
b2

b

ccc C A - BMD

D

A

A

S S

e

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, andN/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

5. Dimension Q shall be measured from the seating plane to the
base plane.

6. Measure dimension S1 at all four corners.

7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.

8. N is the maximum number of terminal positions.

9. Braze fillets shall be concave.

10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

11. Controlling dimension: INCH.

S S

D

-D-

E

S2

-C-

BASE

METAL

M

SECTION A-A

Q

A

L

eA/2

aaa C A - B

M

b1

M

(b)

eA

S S

c

D

D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)

14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

(c)

SYMBOL

A - 0.200 - 5.08 -

b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 ­b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D - 0.785 - 19.94 -

E 0.220 0.310 5.59 7.87 -

e 0.100 BSC 2.54 BSC ­eA 0.300 BSC 7.62 BSC -

eA/2 0.150 BSC 3.81 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 5
S1 0.005 - 0.13 - 6
S2 0.005 - 0.13 - 7

α

aaa - 0.015 - 0.38 ­bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2

N14 148

INCHES MILLIMETERS

90

o

105

o

90

o

105

NOTESMIN MAX MIN MAX

o

Rev. 0 4/94

-

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

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Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

Spec Number 518842

9

HCTS08MS

Packaging

e

-A- -B-

b

0.004 H A - BMD

A

-C-

SEATING AND
BASE PLANE

Q

(Continued)

S S

L

E3 E3

LEAD FINISH

c1

M

SECTION A-A

PIN NO. 1

ID AREA

E1

E

BASE

METAL

b1

(b)

0.036 H A - BMD

(c)

M

A
A

S1

S S

C

-D-

-H-

LE2

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.

2. If a pin one identification mark is used in addition to a tab, the lim­its of dimension k do not apply.

3. This dimension allows for off-center lid, meniscus, and glass
overrun.

4. Dimensions b1 and c1 apply to lead base metal only . Dimension
M applies to lead plating and finish thickness. The maximum lim­its of lead dimensions b and c or M shall be measured at the cen­troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.

5. N is the maximum number of terminal positions.

6. Measure dimension S1 at all four corners.

7. For bottom-brazed lead pac kages, no organic or polymeric mate­rials shall be molded to the bottom of the package to cover the
leads.

8. Dimension Q shall be measured at the point of exit (bey ond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol­der dip lead finish is applied.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

K14.B

14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

INCHES MILLIMETERS

SYMBOL

D

A 0.045 0.115 1.14 2.92 ­b 0.015 0.022 0.38 0.56 -

b1 0.015 0.019 0.38 0.48 -

c 0.003 0.009 0.08 0.23 -

c1 0.003 0.007 0.08 0.18 -

D - 0.390 - 9.91 3

E 0.235 0.260 5.97 6.60 ­E1 - 0.290 - 7.11 3
E2 0.125 - 3.18 - ­E3 0.030 - 0.76 - 7

e 0.050 BSC 1.27 BSC -

k 0.008 0.015 0.20 0.38 2
L 0.270 0.370 6.86 9.40 ­Q 0.010 0.020 0.25 0.51 8

S1 0.005 - 0.13 - 6

M - 0.0015 - 0.04 ­N14 14-

NOTESMIN MAX MIN MAX

Rev. 0 6/14/94

10

Spec Number 518842