Intersil Corporation HCS74T Datasheet

HCS74T

Data Sheet July 1999 File Number

Radiation Hardened Dual-D Flip-Flop with
Set and Reset

Intersil’sSatellite Applications FlowTM(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.

The Intersil HCS74T is a Radiation Hardened Positive Edge
Triggered Flip-Flop with set and reset.

The HCS74T utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.

Specifications

Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.

Detailed Electrical Specifications for the HCS74T are
contained in SMD 5962-95782. A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/ne wsafc lasst.asp

Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.

www.intersil.com/quality/manuals.asp

Ordering Information

TEMP.

ORDERING

INFORMATION

5962R9578201TCC HCS74DTR -55 to 125
5962R9578201TXC HCS74KTR -55 to 125

NOTE:

Minimumorderquantity for -T is 150 units through

distribution, or 450 units direct.

PART

NUMBER

RANGE

(oC)

4615.1

Features

• QML Class T, Per MIL-PRF-38535

• Radiation Performance

5

- Gamma Dose (γ) 1 x 10

RAD(Si)

- Latch-Up Free Under Any Conditions, SOS Process

- SEP Effective LET No Upsets: >100 MEV-cm

- Single Event Upset (SEU) Immunity < 2 x 10

2

/mg

-9

Errors/Bit-Day (Typ)

• 3 Micron Radiation Hardened SOS CMOS

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

-VIL = 30% of VCC Max

-V

= 70% of VCC Min

IH

• Input Current Levels Ii ≤ 5µA at V

OL

, V

OH

Pinouts

HCS74T (SBDIP), CDIP2-T14

TOP VIEW

R1

D1

CP1

S1
Q1
Q1

GND

1
2

D1

3

CP1

4

S1N

5

Q1

6

Q1N

7

GND

HCS74T (FLATPACK), CDFP3-F14

TOP VIEW

1R1
2
3
4
5
6
7

14

V

CC

R2N

13
12

D2

11

CP2

10

S2N
Q2

9
8

Q2N

14
13

12
11
10

9
8

V
R2
D2
CP2
S2
Q2
Q2

CC

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

www.intersil.com or 407-727-9207

Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.

| Copyright © Intersil Corporation 1999

Functional Diagram

S

D

R

1(13)

4(10)

2(12)

CL

CL

HCS74T

CL

P
N

CL

CL

CL

P
N

CL

P
N

CL

Q

6(8)

Q

P
N

CP

3(11)

CL CL

5(9)

TRUTH TABLE

INPUTS OUTPUTS

SET RESET CP D Q Q

LHXXHL

HLXXLH

LLXXH† H†

HH HHL

HH LLH

HHLXQ0Q0

NOTE: L = Logic Level Low, H = Logic Level High, X = Don’t Care

= Transition from Low to High Level

Q0 = The level of Q before the indicated input conditions were established.
† This configuration is non-stable, that is, it will not persist when set and reset inputs return to their inactive (High) level.

2