Intersil Corporation HCS573MS Datasheet

September 1995

HCS573MS

Radiation Hardened

Octal Transparent Latch, Three-State

Features

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K RAD (Si)

• SEP Effective LET No Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

2

/mg

-9

Errors/Bit-

Day (Typ)

• Dose Rate Survivability: >1 x 10

• Dose Rate Upset >10

10

RAD (Si)/s 20ns Pulse

12

RAD (Si)/s

• Latch-Up Free Under Any Conditions

• Fanout (Over Temperature Range)

- Bus Driver Outputs - 15 LSTTL Loads

• Military Temperature Range: -55

o

C to +125oC

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.3 VCC Max

- VIH = 0.7 VCC Min

• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil HCS573MS is a Radiation Hardened octal transpar­ent three-state latch with an active low output enable. The
HCS573MS utilizes advanced CMOS/SOS technology. The
outputs are transparent to the inputs when the Latch Enable (
is HIGH. When the Latch Enable (
latched. The Output Enable (
When the Output Enable (

OE) is HIGH, the outputs are in the

LE) goes LOW, the data is

OE) controls the tri-state outputs.

high impedance state. The latch operation is independent of the
state of the Output Enable.

The HCS573MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCS573MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).

LE)

Pinouts

MIL-STD-1835 CDIP2-T20, LEAD FINISH C

MIL-STD-1835 CDFP4-F20, LEAD FINISH C

OE

D0
D1
D2
D3
D4
D5
D6
D7

GND

20 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

TOP VIEW

1

OE

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7
8

D6

9

D7

GND

10

20 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

TOP VIEW

120
2
3
4
5
6
7
8
9
10

VCC

20

Q0

19

Q1

18

Q2

17

Q3

16

Q4

15

Q5

14

Q6

13
12

Q7

11

LE

19
18
17
16
15
14
13
12
11

VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE

HCS573DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP

HCS573KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack

HCS573D/Sample +25oC Sample 20 Lead SBDIP

HCS573K/Sample +25oC Sample 20 Lead Ceramic Flatpack

HCS573HMSR +25oC Die Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

324

Spec Number

File Number 4056

518771

Functional Diagram

HCS573MS

OE

LE

LE

LE

Dn Qn

P
N

LE

LE

P
N

LE

OE

LE

A

OE

PP

A

N

OE

N

P

N

P

Qn

N

TRUTH TABLE

OUTPUT ENABLE LATCH ENABLE DATA OUTPUT

LHHH

LHLL

LLIL

LLhH

HXXZ

H = High Level
L = Low Level
X = Immaterial
Z = High Impedance

I = Low voltage level prior to the high-to-low latch enable transition
h = High voltage level prior to the high-to-low latch enable transition

325

Spec Number 518771

Specifications HCS573MS

Absolute Maximum Ratings Reliability Information

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (Soldering 10sec). . . . . . . . . . . . . . . . . . +265oC

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..

Operating Conditions

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . .500ns Max

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W

Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W

If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.9mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .9.3mW/oC

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC

Input High Voltage (VIH). . . . . . . . . . . . . . . . . . 70% of VCC to VCC

JA

θ

JC

(NOTE 1)

PARAMETER SYMBOL

Quiescent Current ICC VCC = 5.5V,

Output Current
(Sink)

Output Current
(Source)

Output Voltage Low VOL VCC = 4.5V, VIH = 3.15V,

Output Voltage High VOH VCC = 4.5V, VIH = 3.15V,

Input Leakage
Current

IOL VCC = 4.5V, VIH = 4.5V,

IOH VCC = 4.5V, VIH = 4.5V,

IIN VCC = 5.5V, VIN = VCC or

CONDITIONS

VIN = VCC or GND

VOUT = 0.4V, VIL = 0V

VOUT = VCC -0.4V,
VIL = 0V

IOL = 50µA, VIL = 1.35V

VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V

IOH = -50µA, VIL = 1.35V

VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V

GND

GROUP

A SUB-

GROUPS TEMPERATURE

1 +25oC-40µA

2, 3 +125oC, -55oC - 750 µA

1 +25oC 7.2 - mA

2, 3 +125oC, -55oC 6.0 - mA

1 +25oC -7.2 - mA

2, 3 +125oC, -55oC -6.0 - mA

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC VCC

1, 2, 3 +25oC, +125oC, -55oC VCC

1 +25oC-±0.5 µA

2, 3 +125oC, -55oC-±5.0 µA

LIMITS

-V

-0.1

-V

-0.1

UNITSMIN MAX

Output Leakage
Current

Noise Immunity
Functional Test

NOTES:

1. All voltages reference to device GND.

2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

IOZ VCC = 5.5V, VIN = 0V or

VCC

FN VCC = 4.5V,

VIH = 0.70(VCC),
VIL = 0.30(VCC) (Note 2)

1 +25oC-±1.0 µA

2, 3 +125oC, -55oC-±50 µA

7, 8A, 8B +25oC, +125oC, -55oC---

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Spec Number 518771