Intersil Corporation HCS166MS Datasheet

September 1995

HCS166MS

Radiation Hardened 8-Bit

Parallel-Input/Serial Output Shift Register

Features

• 3 Micron Radiation Hardened CMOS SOS

• Total Dose 200K RAD (Si)

• SEP Effective LET No Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

2

/mg

-9

Errors/

Bit-Day (Typ)

12

• Dose Rate Survivability: >1 x 10

10

• Dose Rate Upset >10

RAD s(Si)/s 20ns Pulse

RAD (Si)/s

• Latch-Up Free Under Any Conditions

• Fanout (Over Temperature Range)

- Standard Outputs - 10 LSTTL Loads

o

• Military Temperature Range: -55

C to +125oC

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.3 VCC Max

- VIH = 0.7 VCC Min

• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil HCS166MS is an 8-bit shift register that has fully
synchronous serial or parallel data entry selected by an
active LOW Parallel Enable (PE) input. When the PE is LOW
one setup time before the LOW-to-HIGH clock transition,
parallel data is entered into the register. When PE is HIGH,
data is entered into internal bit position Q0 from Serial Data
Input (DS), and the remaining bits are shifted one place to
the right (Q0 → Q1 → Q2m etc.) with each positive-going
clock transition. For expansion of the register in parallel to
serial converters, the Q7 output is connected to the DS input
of the succeeding stage.

Pinouts

16 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T16, LEAD FINISH C

TOP VIEW

DS

1

D0

2

D1

3

D2

4

D3

5

CE

6

CP

7

GND

8

16 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835 CDFP4-F16, LEAD FINISH C

TOP VIEW

DS

D0
D1
D2

D3
CE
CP

GND

116
2
3
4
5
6
7
8

Ordering Information

VCC

16
15

PE
D7

14

Q7

13

D6

12

D5

11

D4

10

9

MR

VCC
15
14
13
12
11
10

9

PE
D7
Q7
D6
D5
D4
MR

The clock input is a gated OR structure which allows one
input to be used as an active LOW Clock Enable (CE) input.

PART

NUMBER

The pin assignment for the CP and CE inputs is arbitrary and
con be reversed for layout convenience. The LOW-to-HIGH

HCS166DMSR -55oC to +125oC Intersil Class S

transition of CE input should only take place while the CP is
HIGH for predictable operation.

HCS166KMSR -55oC to +125oC Intersil Class S

A LOW on the Master Reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all bit
positions to a LOW state.

The HCS166MS utilizes advanced CMOS/SOS technology

HCS166D/
Sample

to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.

HCS166K/
Sample

The HCS166MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).

HCS166HMSR +25oC Die Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

250

TEMPERATURE

RANGE

+25oC Sample 16 Lead

+25oC Sample 16 Lead

SCREENING

LEVEL PACKAGE

Equivalent

Equivalent

Spec Number

File Number 2482.2

16 Lead
SBDIP

16 Lead
Ceramic
Flatpack

SBDIP

Ceramic
Flatpack

518758

Functional Diagram

HCS166MS

CP

CE

DS

PE

MR

MASTER

RESET

PARALLEL

ENABLE

D2D0 D3 D5 D6

TRUTH TABLE

INPUTS

CLOCK

ENABLE CLOCK SERIAL

D4D1

Q7

PARALLEL

D0 - D7 Q0 Q1

INTERNAL Q STATES

D7

OUTPUT

Q7

L X XXX X LLL

H X L L X X Q00 Q10 Q0

H L L X a . . . h a b h

H H L H X H Q0n Q6n

H H L L X L Q0n Q6n

H X H X X Q00 Q10 Q70

H = High Level
L = Low Level
X = Immaterial

= Transition from low to high level

a . . . h = The level of steady state input at inputs D0 thru D7, respectively.
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady

state input conditions were established.

Q0n, Q6n = the level of Q0 or Q6, respectively, before the most recent transition of the

clock.

251

Spec Number 518758

Specifications HCS166MS

Absolute Maximum Ratings Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC

Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.

Operating Conditions

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Input Rise and Fall Times at 4.5V VCC (TR, TF). . . . . . .500ns Max

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W

Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.68W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W

If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.7mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .8.8mW/oC

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC

Input High Voltage (VIH). . . . . . . . . . . . . . . . . . 70% of VCC to VCC

JA

θ

JC

(NOTE 1)

PARAMETER SYMBOL

Quiescent Current ICC VCC = 5.5V,

Output Current
(Sink)

Output Current
(Source)

Output Voltage Low VOL VCC = 4.5V, VIH = 3.15V,

Output Voltage High VOH VCC = 4.5V, VIH = 3.15V,

Input Leakage
Current

IOL VCC = 4.5V, VIH = 4.5V,

IOH VCC = 4.5V, VIH = 4.5V,

IIN VCC = 5.5V, VIN = VCC or

CONDITIONS

VIN = VCC or GND

VOUT = 0.4V, VIL = 0V

VOUT = VCC -0.4V,
VIL = 0V

IOL = 50µA, VIL = 1.35V

VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V

IOH = -50µA, VIL = 1.35V

VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V

GND

GROUP

A SUB-

GROUPS TEMPERATURE

1 +25oC-40µA

2, 3 +125oC, -55oC - 750 µA

1 +25oC 4.8 - mA

2, 3 +125oC, -55oC 4.0 - mA

1 +25oC -4.8 - mA

2, 3 +125oC, -55oC -4.0 - mA

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC VCC

1, 2, 3 +25oC, +125oC, -55oC VCC

1 +25oC-±0.5 µA

2, 3 +125oC, -55oC-±5.0 µA

LIMITS

-V

-0.1

-V

-0.1

UNITSMIN MAX

Noise Immunity
Functional Test

NOTES:

1. All voltages reference to device GND.

2. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

FN VCC = 4.5V,

VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 2)

7, 8A, 8B +25oC, +125oC, -55oC---

252

Spec Number 518758