Intersil Corporation HCA10014 Datasheet

HCA10014

Data Sheet August 1999

15MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output

HCA10014 op amp combines the advantage of both CMOS
and bipolar transistors.

Gate protectedP-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance.The use ofPMOS transistors inthe input stage
results in common mode input voltage capability down to

0.5V below the negative supply terminal, an important
attribute in single supply applications.

A CMOS transistor pair, capable of swinging the output
voltage to within 10mV of either supply voltage terminal (at
very high values of load impedance), is employed as the
output circuit.

The HCA10014 operates at supplyvoltages ranging from5V
to 16V, (±2.5V to ±8V). It can be phase compensated with a
single external capacitor, and have terminals for adjustment
of offset voltage for applications requiring offset null
capability. Terminal provisions are also made to permit
strobing of the output stage.

Pinout

HCA10014

(SOIC)

TOP VIEW

File Number

4769

Features

• MOSFET Input Stage Provides:

- Very High Z

- Very Low I

= 1.5TΩ (1.5 x 1012Ω) (Typ)

I

I

15V Operation. . . . . . . . . . . . . . . . . . . . . . . . . 5pA (Typ)

5V Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ)

• Ideal for Single Supply Applications

• Common Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails

Applications

• Ground Referenced Single Supply Amplifiers

• Fast Sample and Hold Amplifiers

• Long Duration Timers/Monostables

• High Input Impedance Comparators
(Ideal Interface with Digital CMOS)

• High Input Impedance Wideband Amplifiers

• Voltage Followers (e.g., Follower for Single Supply D/A
Converter)

• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)

OFFSET

NULL

INV.

INPUT

NON-INV.

INPUT

1
2

­+

3
4

V-

1

8
7
6
5

STROBE
V+
OUTPUT
OFFSET

NULL

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

• Peak Detectors

• Single Supply Full Wave Precision Rectifiers

• Photo Diode Sensor Amplifiers

Ordering Information

PART NO.

(BRAND)

HCA10014 -55 to 125 8 Ld SOIC

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

TEMP.

RANGE (oC) PACKAGE PKG. NO.

M8.15

Tape and Reel

HCA10014

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . .16V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)

Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Short circuit may be applied to ground or to either supply.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 2) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature (Metal Can Package) . . . . . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

PARAMETER SYMBOL

Input Offset Voltage |VIO|VS = ±7.5V - 8 15 mV
Input Offset Voltage Temperature Drift ∆VIO/∆T - 10 - µV/oC
Input Offset Current |IIO|V
Input Current I
Large Signal Voltage Gain A

Common Mode Rejection Ratio CMRR 70 90 - dB
Common Mode Input Voltage Range V
Power Supply Rejection Ratio ∆VIO/∆V
Maximum Output Voltage VOM+RL = 2kΩ 12 13.3 - V

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

A

TEST

CONDITIONS MIN TYP MAX UNITS

= ±7.5V - 0.5 30 pA

S

I

OL

ICR

VOM-RL = 2kΩ - 0.002 0.01 V

VOM+RL = ∞ 14.99 15 - V

VOM-RL = ∞ - 0 0.01 V

VS = ±7.5V - 5 50 pA
VO = 10V

VS = ±7.5V - 32 320 µV/V

S

, RL = 2kΩ 50 320 - kV/V

P-P

94 110 - dB

0 -0.5 to 12 10 V

Maximum Output Current IOM+ (Source) at VO = 0V 12 22 45 mA

IOM- (Sink) at VO = 15V 12 20 45 mA

Supply Current I+ VO = 7.5V, RL = ∞ -1015mA

I+ VO = 0V, RL = ∞ -23mA

2

HCA10014

Electrical Specifications Typical Values Intended Only for Design Guidance, V

Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS TYP UNITS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or 4 and 1 ±22 mV
Input Resistance R
Input Capacitance C
Equivalent Input Noise Voltage e
Open Loop Unity Gain Crossover Frequency

(for Unity Gain Stability ≥47pF Required)

Slew Rate: SR

Open Loop CC = 0 30 V/µs
Closed Loop CC = 56pF 10 V/µs

Transient Response: CC = 56pF, CL = 25pF, RL = 2kΩ (Voltage Follower)

Rise Time t
Overshoot OS 10 %

Settling Time (To <0.1%, VIN = 4V

NOTE:

3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.

)t

P-P

I

I

N

f

T

r

S

f = 1MHz 4.3 pF
BW = 0.2MHz, RS = 1MΩ (Note 3) 23 µV
CC = 0 15 MHz
CC = 47pF 4 MHz

= ±7.5V, TA = 25oC

SUPPLY

1.5 TΩ

0.09 µs

1.2 µs

3

Typical Performance Curves

HCA10014

150

LOAD RESISTANCE = 2kΩ

140

130

120

110

100

90

OPEN LOOP VOLTAGE GAIN (dB)

80

-100 -50 0 50 100
TEMPERATURE (oC)

120

AOL

100

80

60

40

20

OPEN LOOP VOLTAGE GAIN (dB)

0

1

10

10210310410510610710

= 9pF , CC = 0pF , R

1 - C

L

2 - CL = 30pF , CC = 15pF , RL = 2kΩ

SUPPLY VOLTAGE: V+ = 15V; V- = 0
T

= 25oC

A

1
2

3

4

FREQUENCY (Hz)

= ∞

L

φ OL

3 - CL = 30pF , CC = 47pF , RL = 2kΩ
4 - CL = 30pF , CC = 150pF , RL = 2kΩ

FIGURE 1. OPEN LOOP GAIN vs TEMPERATURE FIGURE 2. OPEN LOOP RESPONSE

17.5
LOAD RESISTANCE =

TA = 25oC

12.5

V- = 0

10

7.5

5

2.5

QUIESCENT SUPPLY CURRENT (mA)

0

4

6 8 10 12 14 16 18

∞

OUTPUT VOLTAGE BALANCED = V+/2

OUTPUT VOLTAGE HIGH = V+
OR LOW = V-

TOTAL SUPPLY VOLTAGE (V)

14

OUTPUT VOLTAGE = V+/2

12

V- = 0

10

8

6

4

2

QUIESCENT SUPPLY CURRENT (mA)

0

0246810121416

TOTAL SUPPLY VOLTAGE (V)

4

3

2

1

TA = -55oC

-100

-200

-300

OPEN LOOP PHASE (DEGREES)

8

25oC

125oC

FIGURE 3. QUIESCENT SUPPLYCURRENT vsSUPPLY

VOLTAGE

50

NEGATIVE SUPPLY VOLTAGE = 0V

TA = 25oC

10

1

0.1

STAGE TRANSISTOR (V)

0.01

VOLTAGE DROP ACROSS PMOS OUTPUT

0.001

0.001 0.01 0.1 1.0 10 100

POSITIVE SUPPLY VOLTAGE = 5V

MAGNITUDE OF LOAD CURRENT (mA)

10V

15V

FIGURE 5. VOLTAGE ACROSS PMOS OUTPUT

TRANSISTOR (Q8) vs LOAD CURRENT

4

FIGURE 4. QUIESCENT SUPPLYCURRENT vsSUPPLY

VOLTAGE

50

NEGATIVE SUPPLY VOLTAGE = 0V

= 25oC

T

A

10

POSITIVE SUPPLY VOLTAGE = 5V

1

0.1

STAGE TRANSISTOR (V)

0.01

VOLTAGE DROP ACROSS NMOS OUTPUT

0.001

0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA)

10V

15V

FIGURE 6. VOLTAGE ACROSS NMOS OUTPUT

TRANSISTOR (Q12) vs LOAD CURRENT

Schematic Diagram

HCA10014

BIAS CIRCUIT

Z

1

8.3V

R

1

40kΩ

R

2

5kΩ

NON-INV.

INPUT

3

+

INV.-INPUT

2

-

Q

D

1

D

2

D

3

D

4

1

INPUT STAGE

D5D

CURRENT SOURCE FOR “CURRENT SOURCE

Q6AND Q

Q

2

Q

4

6

Q

6

R

3

1kΩ

Q

(NOTE 4)

Q

10

9

7

D7D

R
1kΩ

8

Q

7

4

LOAD” FOR Q

Q

3

Q

5

SECOND
STAGE

Q

11

V+

11

OUTPUT
STAGE

7

Q

8

OUTPUT

6

Q

12

R

5

1kΩ

5

R

6

1kΩ

OFFSET NULL

1 8 4

COMPENSATION STROBING

NOTE:

4. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.

Application Information

Circuit Description

Figure 7 is a block diagram of the HCA10014. The input
terminals maybe operated down to 0.5V below the negative
supply rail,and the output can be swung very close to either
supply rail in many applications. Consequently, the
HCA10014 is ideal for single supply operation. Three
Class A amplifier stages, having the individual gain
capability and current consumption shown in Figure 7,
provide the total gain of the HCA10014. A biasing circuit
provides two potentials for common use in the first and
second stages. Terminal 8 can be used both for phase
compensation and to strobe the output stage into
quiescence. When Terminal 8 is tied to the negative supply
rail (Terminal 4) by mechanical or electrical means, the
output potential at Terminal 6 essentially rises to the positive
supply rail potential at Terminal 7. This condition of
essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the

V-

ohmic load resistance presentedto the amplifier is very high
(e.g., when theamplifier output isused to driveCMOS digital
circuits in Comparator applications).

Input Stage

The circuit is shown in the schematic diagram. It consists of
a differential input stage using PMOS field effect transistors
(Q
Q
through R6. The mirror pair transistors also function as a
differential to singleended converter to provide basedrive to
the second stage bipolar transistor (Q
when desired, can be effected by connecting a 100,000Ω
potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascade connected
PMOS transistors Q
the input stage. The biasing circuit for the constant current
source is subsequently described. The small diodes D

) working into a mirror pair of bipolar transistors (Q9,

6,Q7

) functioning as load resistors together with resistors R

10

). Offset nulling,

11

are the constant current sourcefor

2,Q4

5

3

5

HCA10014

through D8provide gate oxide protection against high
voltage transients, including static electricity during handling
for Q

and Q7.

6

HCA10014

200µA 200µA

+
3

INPUT

NOTES:

5. Total supplyvoltage(for indicated voltagegains)= 15V withinput

6. Totalsupply voltage(forindicated voltage gains) = 15V with

AV≈ 5X

2

-

OFFSET

NULL

terminals biased so that Terminal 6 potential is +7.5V above
Terminal 4.

output terminal driven to either supply rail.

FIGURE 7. BLOCK DIAGRAM OF THE HCA10014

1.35mA

BIAS CKT.

AV≈

6000X

C

C

COMPENSATION

(WHEN REQUIRED)

8mA
(NOTE 5)
0mA
(NOTE 6)

A

≈

V

30X

815

STROBE

V+

7

OUTPUT

6

V-

4

Second Stage

Most of the voltage gain is provided by the second amplifier
stage, consisting of bipolar transistor Q

and its cascade

11

connected load resistance provided by PMOStransistors Q
and Q5. The source of bias potentials for these PMOS
transistors is subsequently described. Miller Effect
compensation (roll off) isaccomplished by simply connecting
a small capacitor between Terminals 1 and 8. A 47pF
capacitor provides sufficient compensation for stable unity
gain operation in most applications.

Bias Source Circuit

At total supply voltages, somewhat above 8.3V, resistor R
and zener diode Z1 serve to establish a voltage of 8.3V
across the seriesconnected circuit, consistingof resistor R
diodes D
junction of resistor R
potential of about 4.5V for PMOS transistors Q

through D4, and PMOS transistor Q1. A tap at the

1

and diode D4 provides a gate bias

1

and Q5with

4

respect to Terminal 7. A potential of about 2.2V is developed
across diode connected PMOS transistor Q

with respect to

1

Terminal 7 to provide gate bias forPMOS transistorsQ
Q

. It should be noted that Q1 is “mirror connected (see

3

Note 7)” toboth Q

and Q3. Since transistorsQ1,Q2,Q3are

2

designed to be identical,the approximately200µA current in
Q

establishes a similar current in Q2 and Q3 as constant

1

current sources for both the first and second amplifier
stages, respectively.

2

2

and

At total supply voltages somewhat less than 8.3V, zener
diode Z
developed across series connected R

becomes nonconductive and the potential,

1

, D1-D4, and Q1,

1

varies directly with variations in supply voltage.
Consequently, the gate bias for Q

and Q2,Q3varies in

4,Q5

accordance with supply voltage variations. This variation
results in deterioration of the power supply rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.

Output Stage

The output stage consists of a drain loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 8. Typical op amp
loads are readily driven by the output stage. Because large
signal excursions are nonlinear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As avoltage follower,theamplifier can achieve

0.01% accuracy levels, including the negative supply rail.

NOTE:

7. Forgeneralinformation onthe characteristicsofCMOS transistor
pairs in linear circuit applications, see Document # 619, data
sheet on CA3600E “CMOS Transistor Array”.

17.5
SUPPLY VOLTAGE: V+ = 15, V- = 0V

T

= 25oC

12.5

7.5

2.5

A

15

10

500Ω

5

0

LOAD RESISTANCE = 5kΩ

2kΩ

1kΩ

GATE VOLTAGE (TERMINALS 4 AND 8) (V)

CMOS OUTPUT STAGE

17.5 2012.5 15107.52.5 50

22.5

3

,

1

OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)

FIGURE 8. VOLTAGETRANSFER CHARACTERISTICS OF

Input Current Variation with Common Mode Input
Voltage

As shown in the Table of Electrical Specifications, the input
current for the HCA10014 is typically 5pA at T
Terminals 2 and 3 are at a common mode potential of +7.5V
with respect to negative supply Terminal 4. Figure 9 contains
data showing the variation of input current as a function of

= 25oC when

A

6