Intersil Corporation HC6094 Datasheet

[ /Title (HC60
94) /Sub­ject (ADSL Ana­log Front End Chip) /Autho r () /Key­words (Har­ris Semi­con­ductor, Tele­com, SLICs, SLACs , Tele­phone, Tele­phony, WLL, Wire­less Local Loop, PBX, Pri­vate Branch Exchan ge, NT1+, CO, Cen-
Semiconductor
NO RECOMMENDED REPLACEMENT
February 1999
Call Central Applications 1-800-442-7747
or email: centapp@harris.com
Features
• 14-Bit 5 MSPS DAC
• Programmable Gain Stages
Applications
• FDM DMT ADSL
• CAP ADSL
• EC DMT ADSL
• Communications Receiver
Pinout
D11 D10
D9 D8 D7 D6 D5 D4 D3 D2 D1
OBSOLETE PRODUCT
Description
The HC6094 performs the Analog processing for the ADSL chip set. The transmit chain has a 14 Bit DAC, a third-order Chebyshev reconstruction filter and a programmable attenu­ator (-12 to 0dB) capable of driving a 220differential load. The receiver chain has a high impedance input stage, pro­grammable gain stage (0 to 24dB), additional programmable gain (-9 to 18dB) and a third-order Chebyshev anti-aliasing filter for driving an off-chip A/D.
Laser trimmable thin-film resistors are used to set the filter
cutoff frequency and DAC linearity. The transmit and receive signal chains are specified at 65dB MTPR.
Ordering Information
HC6094 (MQFP)
TOP VIEW
D12
D13 (MSB)
VDDD_TX
CLK
GNDD_TX
CTLIN
44 43 42 41 40
1
2 3 4 5 6 7 8 9
10 11
12 13 14 15 16 17
RXO-
RXO+
D0 (LSB)
39 38 37 36 35 34
PGAI-
VSSA_RX
VDDA_RX
HC6094
ADSL Analog Front End Chip
PART
NUMBER
HC6094IN -40 to 85 44 Ld MQFP Q44.10x10
CTLOUT
GNDA_TX
VDDA_ATT
PGAI+
PGAO-
PGAO+
TEMP.
RANGE (oC) PACKAGE PKG. NO.
TXO-
TXO+
VSSA_ATT VDDA_TX VSSA_TX ARTN VDDD_RX CS SDI RST SCLK GNDD__RX GNDA_RX
2221201918
RXI+
33 32 31 30 29
28 27 26 25 24 23
RXI-
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1999
1
File Number 4260.2
Functional Block Diagram
HC6094
CLK
D0-D13
SCLK
SDI
CS
RST
+
RXO
Typical Setup
14
2ND ORDER
1.1MHz LPF
DAC
LATCH
RECEIVER
TRANSMITTER
1ST ORDER
1.1MHz LPF
SHIFT REGISTER AND LATCHES
1ST ORDER
1.1MHz LPF
PGA2
-9 TO 18dB 0 TO 24dB
2ND ORDER
1.1MHz LPF
PGAO±PGAI±
-12 TO 0dB PGA0
TX O±
RXI±
PGA1
RXO±
D0-D13
CLK
SCLK
SDI
CS
RST
+
-
RL = 2000
VSSA_TX
CTLIN CTLOUT
14
DAC
SHIFT REGISTER AND LATCHES
2ND ORDER
1.1MHz LPF
1ST ORDER
1.1MHz LPF
RECEIVER
1ST ORDER
1.1MHz LPF
-9 TO 18dB 0 TO 24dB PGA2
2ND ORDER
1.1MHz LPF
-12 TO 0dB PGA0
VDDD_TX, RX VDDA_TX, RX
VSSA_TX, RX
GNDD_TX, RX
GNDA_RX, TX
PGA1
PGA OUTPGA IN
+
TX O±
-
= 220
R
L
+5V +5V
-5V
RXI±
2
HC6094
Absolute Maximum Ratings T
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±5.5V
Analog Input Voltage to Ground. . . . . . . . . . . .VDD+0.5, VSS -0.5V
Digital Input Voltage to Ground. . . . . . . . . . . . . . . .VDD+0.5V, -0.5V
=25oC Thermal Information
A
Thermal Resistance (Typical, Note 1) θJA (oC/W)
MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Maximum Pow er Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.18W
Maximum Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . 150oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(Lead Tips Only)
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications V
=5V,VSS= -5V, RLOpen, Over Temperature Range; Unless Otherwise Specified. Designed for ±5%
DD
Power Supply.
TEST
PARAMETER SYMBOL
CONDITIONS MIN TYP MAX UNITS
OVERALL
Supply Currents I
I I
VDD (Note 2) - 66 - mA
DD
VSS (Note 3) - -79 - mA
SS CC
V
CC
-0- µA
Power Dissipation PD Quiescent, No Load - 725 - mW
DIGITAL INTERFACE
Input Voltage Thresholds V
Input Currents I
IL
V
IH
VIN = 0V -10.0 0 10.0 µA
IL
I
VIN = V
IH
DD
- - 0.8 V
2.7 - - V
-10.0 0 10.0 µA Serial Clock Period T1 0.1 - 5.0 µs CS Active Before Shift Edge T2 T1/2 -10 - - ns Write Data Valid After Shift
T3 - - 10 ns
Edge CS Inactive After Latch Edge T4 T1 - 10 - T1 +10 ns Write Data Hold After Latch
T5 T1/2 -5 - T1/2 +5 ns
Edge DAC Setup Time t DAC Hold Time t
S H
- - 100 ns
- - 100 ns
14-BIT DAC
Resolution/Monotonicity 14 - - Bits Integral Linearity I Differential Linearity D
Measured at TX Outputs - ±1.5 - LSB
LE
LE
- ±0.9 - LSB
Max Sample Rate 4.416 - - Ms/s
TRANSMITTER OUTPUT
Output Drive TXOD Sink or Source 30 55 - mA Differential Output Swing TXOS RL= 220 11.7 12.03 12.3 V
PP
Differential Balance TXDB Gain Match Between Outputs - 0.5 - % Transmit Output Offset TXOFF Max Gain Single Ended (Note 4) -200 25 200 mV Multi-Tone Power Ratio TXMTPR RL= 220 -65- dB Power Supply Rejection PSRR Input Referred - V
Input Referred - V
DD SS
40 65 - dB 55 84 - dB
3
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