Intersil Corporation HC-5560 Datasheet

HC-5560

Data Sheet January 1997 File Number

PCM Transcoder

The HC-5560 digital line transcoder provides encoding and
decoding of pseudo ternary line code substitution schemes.
Unlike other industry standard transcoders, the HC-5560
provides four worldwide compatible mode selectable code
substitution schemes, including HDB3 (High Density Bipolar

3), B6ZS, B8ZS (Bipolar with 6 or 8 Zero Substitution) and
AMI (Alternate Mark Inversion).

The HC-5560 is fabricated in CMOS and operates from a
single 5V supply. All inputs and outputs are TTL compatible.

Application Note #573, “The HC-5560 Digital Line
Transcoder,” by D.J. Donovan is available.

Ordering Information

PART

NUMBER

HC3-5560-5 0 to 70 20 Ld PDIP E20.3

TEMP.RANGE

(oC) PACKAGE PKG. NO.

Pinout

HC-5560

(PDIP)

TOP VIEW

FORCE AIS

MODE SELECT 1

NRZ DATA IN

CLK ENC

MODE SELECT 2

NRZ DATA OUT

CLK DEC

RESET AIS

AIS
V

SS

1
2
3
4
5
6
7
8
9

10

V

20

DD

OUTPUT ENABLE

19

RESET

18

OUT1

17

OUT2

16

B

15

IN

LOOP TEST ENABLE

14

A

13

IN

12

CLOCK

11

ERROR

2887.2

Features

• Single 5V Supply . . . . . . . . . . . . . . . . . . . . . . .10mA (Typ)

• Mode Selectable Coding Including:

- AMI (T1, T1C)

- B8ZS (T1)

- HDB3 (PCM30)

• North American and European Compatibility

• Simultaneous Encoding and Decoding

• Asynchronous Operation

• Loop Back Control

• Transmission Error Detection

• Alarm Indication Signal

• Replaces MJ1440, MJ1471 and TCM2201 Transcoders

Applications

• North American and European PCM Transmission Lines
where Pseudo Ternary Line Code Substitution Schemes
are Desired

• Any Equipment that Interfaces T1, T1C, T2 or PCM30
Lines Including Multiplexers, Channel Service Units,
(CSUs) Echo Cancellors, Digital Cross-Connects (DSXs),
T1 Compressors, etc.

• Related Literature

- AN573, The HC-5560 Digital Line Transcoder

Functional Diagram

MODE

SELECT

NRZ DATA IN

CLK ENC

OUTPUT
ENABLE

1
2

TRANSMITTER/

ENCODER

V

DD

V

SS

CLOCK
OUT 1

OUT 2

69

LOOP TEST

ENABLE

A

IN

B

IN

FORCE AIS

RESET

CLK DEC

RESET AIS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

SWITCH

AIS

DETECT

RECEIVER/

DECODER

ERROR

DETECT

NRZ DAT A
OUT

ERROR

AIS

HC-5560

Absolute Maximum Ratings Thermal Information

Voltage at Any Pin . . . . . . . . . . . . . . . . . . . .GND -0.3V to VDD 0.3V

Maximum VDD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V

Operating Conditions

Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Operating VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC

Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC

Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300

Die Characteristics

Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4322

Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . .119 mils x 133 mils

Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAJI CMOS

o

Electrical Specifications Unless Otherwise Specified, Typical parameters at 25

o

C, Min-Max parameters are over operating

temperature range. VDD = 5V

PARAMETER SYMBOL MIN TYP MAX UNITS

STATIC SPECIFICATIONS

Quiescent Device Current l

DD

100 µA
Operating Device Current 10 mA
OUT1, OUT2 Low (Sink) Current

I

OL1

3.2 mA

(VOL = 0.4V)
All Other Outputs Low (Sink) Current

I

OL2

2mA

(VOL = 0.8V)
All Outputs High (Source) Current

I

OH

2mA

(VOH = 4V)
Input Low Current I
Input High Current I
Input Low Voltage V
Input High Voltage V
Input Capacitance C

IL

IH

lL

lH

lN

Electrical Specifications Unless Otherwise Specified, Typical parameters at 25

2.4 V

o

C, Min-Max parameters are over operating

10 µA
10 µA

0.8 V

8pF

temperature range. VDD = 5V

PARAMETER SYMBOL FIGURE MIN TYP MAX UNITS

DYNAMIC SPECIFICATIONS

CLK ENC, CLK DEC Input Frequency f
CLK ENC,CLK DEC Rise Time (1.544MHz) t

Fall Time t
Rise Time (2.048MHz) t
Fall Time t
Rise Time (6.3212MHz) t
Fall Time t
Rise Time (8.448MHz) t
Fall Time t

70

CL
RCL
FCL
RCL
FCL
RCL
FCL
RCL
FCL

8.5 MHz
1, 2 10 60 ns
1, 2 10 60 ns
1, 2 10 40 ns
1, 2 10 40 ns
1, 2 10 30 ns
1, 2 10 30 ns
1, 2 5 10 ns
1, 2 5 10 ns

HC-5560

Electrical Specifications Unless Otherwise Specified, Typical parameters at 25

temperature range. VDD = 5V (Continued)

PARAMETER SYMBOL FIGURE MIN TYP MAX UNITS

NRZ-Data In to CLK ENC Data Setup Time t

Data Hold Time t

AIN, BIN to CLK DEC Data Setup Time t

Data Hold Time t
CLK ENC to OUT1, OUT2 t
OUT1, OUT2 Pulse Width (CLK ENC Duty Cycle = 50%)

fCL = 1.544MHz t

fCL = 2.048MHz t

fCL = 6.3212MHz t

f

= 8.448MHz t

CL

CLK DEC to NRZ-Data Out t
Setup Time CLK DEC to Reset AlS t
Hold Time of Reset AlS = ‘0’ t
Setup Time Reset AlS = ‘1’ to CLK DEC t
Reset AlS to AIS output t
CLK DEC to Error output t

S
H
S
H

DD

W
W
W

W
DD
S2
H2
S2

PD5
PD4

o

C, Min-Max parameters are over operating

120--ns
120--ns
215--ns
25--ns
1 - 23 80 ns

1 - 324 - ns
1 - 224 - ns
1 - 79 - ns
1 - 58 - ns
2 - 25 54 ns
335--ns
320--ns
30--ns
3--42ns
3--62ns

Pin Descriptions

PIN NUMBER FUNCTION DESCRIPTION

1 Force AIS Pin 19must be at logic ‘0’ to enable this pin. A logic ‘1’ on this pin forces OUT1 and OUT2to all ‘1’s.A logic

‘0’ on this pin allows normal operation.

2, 5 Mode Select 1,

Mode Select 2

3 NRZ Data In Input data to be encoded into ternary form. The data is clocked by the negative going edge of CLK ENC.
4 CLK ENC Clock encoder, clock for encoding data at NRZ Data In.
6 NRZ Data Out Decoded data from ternary inputs AIN and BIN.
7 CLK DEC Clock decoder, clock for decoding ternary data on inputs AIN and BIN.

8, 9 Reset AIS, AlS Logic ‘0’ onReset AIS resetsa decodedzero counter andeither resets AISoutput tozero provided 3or more

10 V

SS

11 Error A logic ‘1’ indicates that a violation of the line coding scheme has been decoded.
12 Clock “OR” function of AIN and BIN for clock regeneration when pin 14 is at logic ‘0’, “OR” function of OUT1 and

13, 15 AIN, B

IN

MS1 MS2 Functions As

0 0 AMI
0 1 B8ZS
1 0 B6ZS
1 1 HDB3

zeros have been decodedin thepreceding Reset AIS period or sets AlSto ‘1’if less than 3 zeros have been
decoded in the preceding two Reset AlS periods. A period of Reset AlS is defined from the bit following the
bit during which Reset AlS makes a high to low transition to the bit during which Reset AIS makes the next
high to low transition.

Ground reference.

OUT2 when pin 14 is at logic ‘1’.
Inputsrepresenting thereceivedPCM signal. AIN=‘1’ representsapositive going ‘1’and BIN=‘1’ represents

a negative going ‘1’. AINand BINare sampled by the positive going edge of CLK DEC. AINand BINmay be
interchanged.

71