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HC-55564/883
October 1999 FN3738.1
Continuously Variable Slope
Delta-Modulator (CVSD)
The HC-55564/883 is a half dupl ex modulator/demodulator
CMOS intergrated ci rcuit used to convert voice signals into
serial NRZ digital data and to reconvert that data into voice.
The conversion is by delta-modulation, using the
Continuousl y Vari able Slope (CVSD) method of
modulation/demodulation.
While the signals are compatible with other CVSD circuits,
the internal design is unique. The analog loop filters have
been replaced by very low power digital filters which require
no external timing components. This approach allows
inclusion of many desirable features which would be difficul t
to implement usi ng other approaches.
The fundamental adva ntages of delta-modu lation, along with
its simplicity and serial data format, provide an efficient (low
data rate/low memory requirements) method for voice
digitizati on. The device may be easily configured with the
National TP3040 PCM/CVSD filter.
The HC-55564/883 is usa ble from 9k bits/sec to above
64kbps. For more applications information, see Application
Notes AN576 and AN607.
Ordering Information
PART
NUMBER
HC1-55564/883 -55
HC4-55564/883 -55
TEMPERATURE
RANGE PACKAGE
o
C to +125oC 14 Lead Cer DI P
o
C to +125oC 20 Lead Ceramic LCC
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Pr ovisions of Paragraph 1.2.1.Requires Few External Parts
• All Digital
• Requires Few External Parts
• Low Power Drain
• Time Constants Determined by Clock Frequency; No Calibration or Drift Probl em s: Aut om atic Offset Adjustment
• Half Duplex Operation Under Digital Control
• Filter Reset Under Digital Cont rol
• Automatic Overload Recovery
• Automatic “Quiet” Pat tern Generation
• AGC Control Signal Availa ble
Applications
• Voice Transmission Over Data Channels (Modem s)
• Voice/Data Multiplexing (Pair Gain)
• Voice Encryptio n/Scrambling
•Voicemail
• Audio Manipulations: Delay Lines, Time Compres sion,
Echo Generation/Suppression, Special Effects, etc.
• Pagers/Satellites
• Data Acquisition Systems
• Voice I/O for Digital Systems and Speech Synthesis
Requiring Small Size, Low Weight, and Ease of Reprogrammability
Pinouts
V
DD
ANALOG GND
A
OUT
AGC
A
NC
NC
HC-55564/883
(CERDIP)
TOP VIEW
1
2
3
4
5
IN
6
7
HC-55564/883
(CLCC)
TOP VIEW
DD
NC
V
DIGITAL
FZ
NC
NC
OUT
18
DIGITA L IN
17
NC
16
APT
15
NC
14
ENCODE
/DECODE
CLOCK
13
DIGITAL
GND
14
DIG OUT
13
FZ
DIG IN
12
11
APT
ENC/DEC
10
9
CLOCK
8
DIG GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
ANALOG GND
A
OUT
NC
AGC
NC
A
220119
3
4
5
6
7
8
IN
9101112
NC
| Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Pin Description
HC-55564/883
PIN NO.
14 LEAD
DIP
12V
2 3 Analog
PIN NO.
20 LEAD
LCC SYMBOL DESCRIPTION
DD
Positive Supply Voltage. Voltage range is +3.2V to +6.0V.
Analog G round connection to D/A ladders and comparator.
GND
34A
OUT
46AGC
58A
6, 7 1, 5, 7, 9,
NC No internal connection is made to these pins.
Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 75kΩ source with DC offset of V
AC coupled.
/2. Within ±2dB of Audio Input. Should be externally
DD
Automati c Gain Control output. A logi c low level will appear at this output when the recove red signal excursion reaches one-half of full scale value. In each half cycle full scale is V
is proportional to the average signal level.
Audio Inpu t to com para tor. Sh ould be ex ter nall y AC cou pled . Pre sen ts ap prox imat ely 200 kΩ in series
IN
with V
DD
/2.
/2. The mark-space ratio
DD
10, 11 , 15 ,
17
812Digital
Logic ground. 0V reference for all logic i nputs and outputs.
GND
9 13 Clock Sampling rate clock. In the decode mode, must be synchronized with the digital input data such that the
data i s va lid a t th e po sit ive cloc k tr ans ition . In the e nco de mod e, the di gita l data is clo cke d out on th e
negative going clock transition. The clock rate equals the data rate.
/
10 14 Encode
Decode
11 16 APT
A single CVSD can provide half-duplex operation. The encode or decode function is selected by the logic
level applied to this input. A low level selects the encode mode, a high level the decode mode.
Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, however;
internally the CVS D is still functional and a signal is still available at the A
port. Active low.
OUT
12 18 Digital In Input for the received digital NRZ data.
13 19 FZ
Force Ze ro i np ut . A ct ivat i ng thi s i n put r e se ts t he i nter n al l og ic an d fo r ces the di gi tal o ut put an d t he r e co vered audio output into the “quieting” condition. An alternating 1-0 pattern ap pears at the dig ital output at
1/2 the c lock rate. When t his is de code d by a r ecei ve CVSD , a 10 mV
output. Active low.
inaudible signal appears at audio
P-P
14 20 Digital Out Output for transmitted digital NRZ data.
NOTE:
1. No active input should be left in a “float ing condition”.
Functional Diagram
V
DD
3V TO 6V
(1)
DIGITAL
IN
V
DD
2
(5)
A
IN
(2)
ANALOG
GND
(3) A
OUT
(SIDE TONE)
(4) AG C
OUT
2
(12)
Z
IN
Z
OUT
ENC
10-BIT
10-BIT
(10)
/DEC
COMPARATOR
DAC
10
10
DAC
(11) (13)
APT
RESET
SIGNAL
ESTIMATE
FILTER 1ms
FORCE
ZERO
RESET
T
D
6
DIGITAL
MODULATOR
±1
F/F
(9)
CLOCK
Q
(8)
DIGITAL
GND
(14)
DIGITAL
OUT
3-BIT
SHIFT
REGISTER
STEP
SIZE
LOGIC
SYLLABIC
FILTER
4ms
RESET
HC-55564/883
Absolute Maximum Ratings Thermal Information
Voltage at Any Pin . . . . . . . . . . . . . . . . . . .GND -0.3V to VDD +0.3V
Maximum V
Minimum V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
DD
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.2V
DD
o
C to +150oC
o
o
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
CAUTION: Stress es abov e thos e lis ted in “ A bsolute Max imum R a tings” ma y cause per manen t dam age to th e de vice. This is a s tress on ly rating and ope rat ion of th e
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC
Operating Supply Voltage (V
Device T ested at: V
SUPPLY
PARAMETER SYMBOL CONDITIONS
Supply Current I
Logic Input High (N ote 2) V
Logic Input Low (N ote 2) V
Logic Output High (Note 3) V
Logic Output Low (Note 3) V
Quietin g Pa tte rn
Amplitude (Note 8)
AGC Thre shold (Note 9) V
Range) . . . . . . . . . . . +3.2V to +6.0V
DD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
= +5V, fclk = 16kHz, Operating Temperature = -55oC ≤ TA ≤ +125oC, Unless Otherwise Specified.
DD
Encode Mode: AIN = 0V 1 +25oC-1.5mA
Input Level: ‘1’ = +3.5V,
IH
‘0’ = +1.5V
Input Level: ‘1’ = +3.5V,
IL
‘0’ = +1.5V
I
= -40µA1+25
LOAD
I
= +0.8mA 1 +25oC-0.4V
LOAD
FZ = 0; Clock Inputs
Switched Statically
Encode Mode 1 +25oC 0.45 0.65 F.S.
V
OH
OL
QP
ATH
Thermal Resistance θ
CerDIP Package . . . . . . . . . . . . . . . . . . . 66oC/W 16oC/W
Ceramic LCC Package . . . . . . . . . . . . . . 65
Package Power Dissipation Limit at +75
C
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.52W
C
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.54W
Packag e P ower Diss i pa tion Dera tin g F a ct or Above +75
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5.2W/
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . 15.4W/
GROUP A
SUBGROUP TEMPERATURE
2, 3 +125oC, -55oC- 1.5mA
1+25
2, 3 +125
1+25
2, 3 +125
o
C3.5-V
o
C, -55oC3.5 - V
o
C-1.5V
o
C, -55oC- 1.5V
o
C4.0-V
2, 3 +125oC, -55oC4.0 - V
2, 3 +125
1+25
o
C, -55oC- 0.4V
o
C-14mV
2, 3 +125oC, -55oC- 14mV
2, 3 +125oC, -55oC 0.45 0.65 F.S.
JA
o
o
C for TJ at ≤ +175oC
C/W 15oC/W
o
C
LIMITS
θ
JC
o
C
o
C
UNITSTYP MAX
P-P
P-P
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank.
TABLE 3. ELECTRICL PERFORMANCE CHARACTERISTICS
Devices Characterized at: V
= +5.0V, TA = +25oC, Operating Temperature, fclk = 16kHz Clock Sampling Rate.
DD
ENC
/DDC = ENC = Encode Mode, Unle ss Otherw ise Specified.
PARAMETER SYMBOL CONDITIONS NOTE TEMPERATURE
Sampling Rate CLK A
CLK Duty Cycle A
3
= 0.775 V
IN
= 0.775 V
IN
100Hz
LIMITS
UNITSTYP MAX
at 20Hz 1, 12 +25oC964kBS
RMS
RMS
at
12 +25oC3070%
o
C, -55oC964kBS
+125
o
C, -55oC3070%
+125
HC-55564/883
TABLE 3. ELECTRICL PERFORMANCE CHARACTERISTICS (Continued)
Devices Characterized at: V
PARAMETER SYMBOL CONDITIONS NOTE TEMPERATURE
Audio Input Voltage A
Audio Output Voltage A
Input Impedance Z
Output Impeda nce Z
Transfer Gain A
Resolution RES A
MIN Step Size MSS 7, 12 +25
Clamping Threshold V
NOTES:
1. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negativ e clock edge. D ata is clocked into the CVSD
on the positive going edge (see Figure 2). Clock may be run at less than 9kbps.
2. Logic inputs are CMOS comp atible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
3. Logic outputs are CMOS compatible at supply voltage and will withstand short-circui ts to V
must not exceed 5% in order to maintain an acceptable current density level. Digital data output is NRZ and changes with negative clock transition s. E ac h outp ut will driv e on e LS TT L loa ds .
4. Recommended v oice input ra nge for best voice performance. Should be externally AC coupled.
5. May be used for side-tone in encode mode. Should be externally AC coupled.
6. Presents series impedance with audio sig nal. Zero signal reference is approximately V
7. The minimum audio output voltage change that can be produced by the internal DAC.
8. The “quieting” pattern or idle-channel audio output steps at 1/2 the bit rate, changing state on negative clock transitions.
9. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e. at V
±25% of V
DD
.
10. The recovered signal will b e clamped, and the computation will be inhibited, when the recovered signal reache s three-quarte rs of full-scale value, and will unclamp when it falls below this value (positive or negative).
11. No load condition measured from audio in to audio out.
12. The parameters listed in this table are c ontrolled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design chan ges which would affect these characteristics.
13. The minimum audio input voltage ab ove which encoding is guaranteed to take place.
= +5.0V, TA = +25oC, Operating Temperature, fclk = 16kHz Clock Sampling Rate.
DD
ENC
/DDC = ENC = Encode Mode, Unle ss Otherw ise Specified. (Continued)
IN
AIN = 100Hz 4, 12 +25oC-1.2V
+125oC, -55oC-1.2V
OUT
AIN = 100Hz 5, 12 +25oC-1.2V
+125oC, -55oC-1.2V
IN
OUT
E-D
CTH
AIN = 100Hz 6, 12 +25oC150500kΩ
o
C, -55oC150500kΩ
+125
AIN = 100Hz 6, 12 +25oC3525kΩ
o
C, -55oC3525kΩ
+125
AIN = 0.775 V
100Hz
at 100Hz. Note 8 12, 13 +25oC0.3-% of
IN
RMS
at
11, 12 +25oC-2+2dB
o
C, +125oC-2+2dB
-55
10, 12 +25oC 0.70 0.90 F.S.
or ground; ho wever, the short circuit duty cycle
DD
/2. Varies with audio input level by ±2dB.
DD
LIMITS
UNITSTYP MAX
Supply
o
C 0.10 0.14 % of
Supply
RMS
RMS
RMS
RMS
DD
/2
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1)
Interim Electrical Parameters (Pre Burn-In) 1
Final Electrical Test Parameters 1 (Note 1), 2, 3
Group A Tes t Re qu ir e m en ts 1, 2, 3
Groups C and D Endpoints 1
NOTE:
1. PDA applies to Subgroup 1 only.
4
Die Characteristics
HC-55564/883
DIE DIMENSIONS:
82 x 147 x 20 ± 1 mils
METALLIZATION:
Type: AlSi
Thickness: 10kÅ ± 1kÅ
Metallization Mask Layout
A
OUT
ANALOG
HC-55564/883
V
DD
GLASSIVATION:
Type: Silane, 3% Phosphorous
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
2.0 x 105A/cm2
TRANSISTOR COUNT: 1896
PROCESS: CMOS; SAJI
DIGITAL
OUTGND
FZ
DIGITAL IN
AGC
A
APT
ENC/DEC
IN
CLOCK
DIGITAL
GND
5
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