intersil HC-55564-883 DATA SHEET

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HC-55564/883

October 1999 FN3738.1

Continuously Variable Slope
Delta-Modulator (CVSD)

The HC-55564/883 is a half dupl ex modulator/demodulator
CMOS intergrated ci rcuit used to convert voice signals into
serial NRZ digital data and to reconvert that data into voice.
The conversion is by delta-modulation, using the
Continuousl y Vari able Slope (CVSD) method of
modulation/demodulation.

While the signals are compatible with other CVSD circuits,
the internal design is unique. The analog loop filters have
been replaced by very low power digital filters which require
no external timing components. This approach allows
inclusion of many desirable features which would be difficul t
to implement usi ng other approaches.

The fundamental adva ntages of delta-modu lation, along with
its simplicity and serial data format, provide an efficient (low
data rate/low memory requirements) method for voice
digitizati on. The device may be easily configured with the
National TP3040 PCM/CVSD filter.

The HC-55564/883 is usa ble from 9k bits/sec to above
64kbps. For more applications information, see Application
Notes AN576 and AN607.

Ordering Information

PART

NUMBER

HC1-55564/883 -55

HC4-55564/883 -55

TEMPERATURE

RANGE PACKAGE

o

C to +125oC 14 Lead Cer DI P

o

C to +125oC 20 Lead Ceramic LCC

Features

• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Pr ovisions of Para­graph 1.2.1.Requires Few External Parts

• All Digital

• Requires Few External Parts

• Low Power Drain

• Time Constants Determined by Clock Frequency; No Cali­bration or Drift Probl em s: Aut om atic Offset Adjustment

• Half Duplex Operation Under Digital Control

• Filter Reset Under Digital Cont rol

• Automatic Overload Recovery

• Automatic “Quiet” Pat tern Generation

• AGC Control Signal Availa ble

Applications

• Voice Transmission Over Data Channels (Modem s)

• Voice/Data Multiplexing (Pair Gain)

• Voice Encryptio n/Scrambling

•Voicemail

• Audio Manipulations: Delay Lines, Time Compres sion,
Echo Generation/Suppression, Special Effects, etc.

• Pagers/Satellites

• Data Acquisition Systems

• Voice I/O for Digital Systems and Speech Synthesis
Requiring Small Size, Low Weight, and Ease of Repro­grammability

Pinouts

V

DD

ANALOG GND

A

OUT

AGC

A

NC
NC

HC-55564/883

(CERDIP)

TOP VIEW

1
2
3
4
5

IN

6
7

HC-55564/883

(CLCC)

TOP VIEW

DD

NC

V

DIGITAL

FZ

NC

NC

OUT

18

DIGITA L IN

17

NC

16

APT

15

NC

14

ENCODE

/DECODE

CLOCK

13

DIGITAL

GND

14

DIG OUT

13

FZ
DIG IN

12
11

APT
ENC/DEC

10

9

CLOCK

8

DIG GND

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

ANALOG GND

A

OUT

NC

AGC

NC

A

220119

3
4
5
6
7

8

IN

9101112

NC

| Intersil (and design) is a trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002. All Rights Reserved

Pin Description

HC-55564/883

PIN NO.

14 LEAD

DIP

12V
2 3 Analog

PIN NO.

20 LEAD

LCC SYMBOL DESCRIPTION

DD

Positive Supply Voltage. Voltage range is +3.2V to +6.0V.
Analog G round connection to D/A ladders and comparator.

GND

34A

OUT

46AGC

58A

6, 7 1, 5, 7, 9,

NC No internal connection is made to these pins.

Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 75kΩ source with DC offset of V
AC coupled.

/2. Within ±2dB of Audio Input. Should be externally

DD

Automati c Gain Control output. A logi c low level will appear at this output when the recove red signal ex­cursion reaches one-half of full scale value. In each half cycle full scale is V
is proportional to the average signal level.

Audio Inpu t to com para tor. Sh ould be ex ter nall y AC cou pled . Pre sen ts ap prox imat ely 200 kΩ in series

IN

with V

DD

/2.

/2. The mark-space ratio

DD

10, 11 , 15 ,

17

812Digital

Logic ground. 0V reference for all logic i nputs and outputs.

GND

9 13 Clock Sampling rate clock. In the decode mode, must be synchronized with the digital input data such that the

data i s va lid a t th e po sit ive cloc k tr ans ition . In the e nco de mod e, the di gita l data is clo cke d out on th e
negative going clock transition. The clock rate equals the data rate.

/

10 14 Encode

Decode

11 16 APT

A single CVSD can provide half-duplex operation. The encode or decode function is selected by the logic
level applied to this input. A low level selects the encode mode, a high level the decode mode.

Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, however;
internally the CVS D is still functional and a signal is still available at the A

port. Active low.

OUT

12 18 Digital In Input for the received digital NRZ data.
13 19 FZ

Force Ze ro i np ut . A ct ivat i ng thi s i n put r e se ts t he i nter n al l og ic an d fo r ces the di gi tal o ut put an d t he r e co v­ered audio output into the “quieting” condition. An alternating 1-0 pattern ap pears at the dig ital output at
1/2 the c lock rate. When t his is de code d by a r ecei ve CVSD , a 10 mV
output. Active low.

inaudible signal appears at audio

P-P

14 20 Digital Out Output for transmitted digital NRZ data.

NOTE:

1. No active input should be left in a “float ing condition”.

Functional Diagram

V

DD

3V TO 6V

(1)

DIGITAL

IN

V

DD

2

(5)

A

IN

(2)

ANALOG

GND

(3) A

OUT

(SIDE TONE)

(4) AG C

OUT

2

(12)

Z

IN

Z

OUT

ENC

10-BIT

10-BIT

(10)

/DEC

COMPARATOR

DAC

10

10

DAC

(11) (13)

APT

RESET

SIGNAL

ESTIMATE

FILTER 1ms

FORCE
ZERO

RESET

T

D

6

DIGITAL

MODULATOR

±1

F/F

(9)

CLOCK

Q

(8)

DIGITAL
GND

(14)
DIGITAL
OUT

3-BIT

SHIFT

REGISTER

STEP

SIZE

LOGIC

SYLLABIC

FILTER

4ms

RESET