Intersil Corporation HC-55564 Datasheet

Low Bit Rate Voiceband Encoders/Decoder

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j

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Semiconductor

HC-55564

OBSOLETE PRODUCT

[/Title
(HC­55564
)

Sub-

ect
(Con­tinu­ously
Vari­able
Slope
Delta­Modu­lator
(CVS
D))

Autho
r ()

Key­words
(Har­ris
Semi­con­ductor
, Tele­com,
SLICs
,
SLAC
s,
Tele­phone,
Tele­phony,

NO RECOMMENDED REPLACEMENT

February 1999

Call Central Applications 1-800-442-7747

or email: [e-mail]

Features

• All Digital

• Requires Few External Parts

• Low Power Drain: 1.5mW Typical From Single 4.5V
To 6V Supply

• Time Constants Determined by Clock Frequency;
No Calibration or Drift Problems: Automatic Offset
Adjustment

• Half Duplex Operation Under Digital Control

• Filter Reset Under Digital Control

• Automatic Overload Recovery

• Automatic “Quiet” Pattern Generation

• AGC Control Signal Available

Applications

• Voice Transmission Over Data Channels (Modems)

• Voice/Data Multiplexing (Pair Gain)

• Voice Encryption/Scrambling

• Voicemail

• Audio Manipulations: Delay Lines, Time Compression,
Echo Generation/Suppression, Special Effects, etc.

• Pagers/Satellites

• Data Acquisition Systems

• Voice I/O for Digital Systems and Speech Synthesis
Requiring Small Size, Low Weight, and Ease of
Reprogrammability

• Related Literature

- AN607, Delta Modulation for Voice Transmission

Pinouts

HC-55564

(PDIP, CERDIP)

TOP VIEW

V

DD

ANALOG GND

A

OUT

AGC

A

NC
NC

1
2
3
4
5

IN

6
7

14
13
12
11
10

9
8

DIG OUT
FZ
DIG IN
APT
ENC/DEC
CLOCK
DIG GND

Continuously Variable

Slope Delta-Modulator (CVSD)

Description

The HC-55564 is a half duplex modulator/demodulator CMOS
intergrated circuit used to convert voice signals into serial NRZ
digital data and to reconvert that data into voice. The conver­sion is by delta-modulation, using the Continuously Variable
Slope (CVSD) method of modulation/demodulation.

While the signalsare compatible with other CVSD circuits, the inter­nal design is unique. The analog loop filters have been replaced by
very low powerdigital filters which require no external timing compo­nents. This approach allows inclusion of many desirable features
which would be difficult to implement using other approaches.

The fundamental advantages of delta-modulation, along with its
simplicity and serial data format, provide an efficient (low data
rate/low memory requirements) method for voice digitization.

The HC-55564 is usable from 9kbits/s to above 64kbps. See the
Harris Military databook for a MIL-STD-883C compliant CVSD.
Application Note 607.

Ordering Information

PART

NUMBER

HC1-55564-2 -55 to 125 14 Ld CERDIP F14.3
HC1-55564-5 0 to 75 14 Ld CERDIP F14.3
HC1-55564-9 -40 to 85 14 Ld CERDIP F14.3
HC3-55564-5 0 to 75 14 Ld PDIP E14.3
HC9P55564-5 0 to 75 16LdPlasticSOIC (W) M16.3

ANALOG GND

TEMP.

RANGE (oC) PACKAGE PKG. NO.

HC-55564

(SOIC)

TOP VIEW

16
15
14
13
12
11
10

9

DIG OUT
FZ
DIG IN
APT
ENC/DEC
CLOCK
DIG GND
NC

V

A

OUT

AGC

AIN

DD

NC
NC
NC

1
2
3
4
5
6
7
8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1999

1

File Number 2889.5

HC-55564

Absolute Maximum Ratings Thermal Information

Voltage at Any Pin . . . . . . . . . . . . . . . . . . . .GND -0.3V to VDD 0.3V

Maximum VDD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.0V

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

Operating Conditions

Temperature Range

HC-55564-5, -7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 750C

HC-55564-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 850C

HC-55564-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 1250C

Operating VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 6.0V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Unless Otherwise Specified, typical parameters are at 25

ranges. VDD = 5.0V, Sampling Rate = 16Kbps, AG = DG = 0V, AIN = 1.2V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Sampling Rate CLK Note 2 9 16 64 kbps
Supply Current I
Logic ‘1’ Input V
Logic ‘0’ Input V
Logic ‘1’ Output V
Logic ‘0’ Output V
Clock Duty Cycle 30 - 70 %
Audio Input Voltage A
Audio Output Voltage A
Audio Input Impedance Z
Audio Output Impedance Z
Transfer Gain A
Syllabic Filter Time Constant t
Signal Estimate Filter Time

Constant
Enc Threshold AIN at 100Hz (Note 9), (Typ) 0.3% = 15mV
Minimum Step Size MSS Note 10 - 0.1 - %V
Quieting Pattern Amplitude V
AGC Threshold V
Clamping Threshold V

NOTES:

2. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the
CVSD on the positive going edge (see Figure 2). Clock may be run at less than 9kbps and greater than 64kbps.

3. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.

4. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to V
changes with negative clock transitions. Each output will drive one LS TTL load.

5. Recommended voice input range for best voice performance. Should be externally AC coupled.

6. May be used for side-tone in encode mode. Should be externally AC coupled. Varies with audio input level by ±2dB.

7. Presents series impedance with audio signal. Zero signal reference is approximately VDD/2.

8. Note that filter time constants are inversely proportional to clock rate. Both filters approximate single pole responses.

9. The minimum audio input voltage above which encoding takes place.

10. The minimum audio output voltage change that can be produced by the internal DAC.

11. Settled value,the“quieting” pattern or idle-channel audio output steps at one-half the bit rate, changing state on negative clock transitions.

12. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e., at
VDD/2 ±25% of VDD.

13. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of full­scale value, and will unclamp when it falls below this value (positive or negative).

DD

OH
OL

OUT

OUT

E-D

SF

t

SE

QP

ATH

CTH

Note 3 3.5 - - V

IH

Note 3 - - 1.5 V

IL

Note 4 4.0 - - V
Note 4 - - 0.4 V

AC Coupled (Note 5) - 0.5 1.2 V

IN

AC Coupled (Note 6) - 0.5 1.2 V
Note 7 - 280 - kΩ

IN

Note 7 - 150 - kΩ
No Load, Audio In to Audio Out. -2.0 - +2.0 dB
Note 8 - 4.0 - ms
Note 8 1.0 - - ms

FZ = 0V or APT = 0V (Note 11) - 10 - mV
Note 12 - 0.1 - F.S.
Note 13 - 0.75 - F.S.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

Die Characteristics

Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897

Die Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 x 82

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V

Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BiMOSE

o

C, Min-Max are over operating temperature

RMS

- 0.3 1.5 mA

RMS

-6-mV

or ground. Digital data output is NRZ and

DD

DD

RMS
RMS

PEAK

DD

P-P

2

HC-55564

Pin Descriptions

PIN NUMBER

14 LEAD DIP SYMBOL DESCRIPTION

1V

DD

2 Analog GND Analog Ground connection to D/A ladders and comparator.
3A

OUT

4 AGC Automatic Gain Control output. A logic low level will appear at this output when the recovered

5A

IN

6, 7 NC No internal connection is made to these pins.

8 Digital GND Logic ground. 0V reference for all logic inputs and outputs.
9 Clock Sampling rate clock. In the decode mode, must be synchronized with the digital input data such

10 Encode/

Decode

11 APT Alternate Plain T ext input. Activating this input caused a digital quieting pattern to be transmitted, how-

12 Digital In Input for the received digital NRZ data.
13 FZ Force Zero input. Activatingthisinput resets the internal logic andforcesthedigital output and the

14 Digital Out Output for transmitted digital NRZ data.

NOTE:

14. No active input should be left in a “floating condition.”

Positive Supply Voltage. Voltage range is 4.5V to 6.0V.

Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 150kΩ source with DC offset of VDD/2. Within ±2dB of Audio Input. Should be ex­ternally AC coupled.

signal excursion reaches one-half of full scale value. In each half cycle full scale is VDD/2. The
mark-space ratio is proportional to the average signal level.

Audio Input to comparator. Should be externally AC coupled. Presents approximately 280kΩ in
series with VDD/2.

that the data is valid at thepositiveclocktransition. In the encode mode, the digital data is clocked
out on the negative going clock transition. The clock rate equals the data rate.

A single CVSD can provide half-duplex operation. The encode or decode function is selected by the
logic level applied to this input. A low levelselects the encode mode, a high levelthe decode mode.

ever; internally the CVSD is still functional and a signal is still available at the A

recovered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the
digital output at 1/2 the clock rate. When this is decoded by a receive CVSD,a 10mV
signal appears at audio output. Active low.

port. Active low.

OUT

P-P

inaudible

Functional Diagram

(1)

V

DD

3V TO 6V

(SIDE TONE)

(4)

(DIP Pin Numbers Shown)

(12)

DIGITAL

IN

V

DD

2

(5)

A

IN

Z

IN

(2)

ANALOG

GND

(3) A

AGC OUT

OUT

Z

OUT

10 BIT

10 BIT

(10)

ENC/DEC

COMPARATOR

DAC

10

10

DAC

(11) (13)

APT

RESET

SIGNAL

ESTIMATE

FILTER 1msec

3

FORCE
ZERO

RESET

T

D

6

DIGITAL

MODULATOR

±1

F/F

(9)

CLOCK

Q

(8)

DIGITAL
GND

(14)
DIGITAL
OUT

3 BIT

SHIFT

REGISTER

STEP

SIZE

LOGIC

SYLLABIC

FILTER

4ms

RESET