The HC5526 is a subscriber line interface circuit that is
compliant with CCITT standards. Enhancements include
immunity to circuit latch-up during hot plug and absence of
false signaling in the presence of longitudinal currents.
The HC5526 is fabricated in a High Voltage Dielectrically
Isolated (DI) Bipolar Process that eliminates leakage
currents and device latch-up problems normally associated
with Junction Isolated (JI) ICs. The elimination of the leakage
currents results in improved circuit performance for wide
temperature extremes. The latch free benefit of the DI
process guarantees operation under adverse transient
conditions. This process feature makes the HC5526 ideally
suited for use in harsh outdoor environments.
Part Number Information
PART NUMBER
HC5526CM0 to 7028 Ld PLCCN28.45
TEMP.
RANGE (oC)PACKAGE
PKG.
DWG. #
Features
• DI Monolithic High Voltage Process
• Programmable Current Feed . . . . . . . . . . . 20mA to 60mA
• Programmable Loop Current Detector Threshold and
Battery Feed Characteristics
• Ground Key and Ring Trip Detection
• Compatible with Ericsson’s PBL3764
• Thermal Shutdown
• On-Hook Transmission
• Wide Battery Voltage Range . . . . . . . . . . . . .-24V to -58V
• Low Standby Power
• Meets CCITT Transmission Requirements
o
• Ambient Temperature Range . . . . . . . . . . . -40
C to 85oC
Applications
• On-Premises (ONS)
•Key Systems
• PBX
• Related Literature
- AN9537, Operation of the HC5513/26 Evaluation Board
Pinout
HC5526 (PLCC)
TOP VIEW
RINGRLY
V
BAT
R
SG
E1
E0
N/C
DET
VCCN/C
5
6
7
8
9
10
11
12 13 14 15 16 17 18
C2
C1
BGND
1234
DC
R
SENSE
RING
AGND
RINGX
RSN
TIPX
N/C
SENSE
TIP
262728
25
DR
24
N/C
23
DT
22
RD
21
HPT
20
HPR
19
V
EE
V
TX
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
1RING
2BGNDBattery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
4V
5RINGRLYRing relay driver output.
6V
7R
8E1TTL compatible logic input. The logic state of E1 in conjunction with the logic state of C1 determines which detector is
9E0TTL compatible logic input. Enables the DET
11DETDetector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered (see
12C2TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
13C1TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
14R
15AGNDAnalog ground.
16RSNReceive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that flows
18V
19V
20HPRRING side of AC/DC separation capacitor C
21HPTTIP side of AC/DC separation capacitor C
22RDLoop current programming resistor. Resistor RD sets the trigger level for the loop current detect circuit. A filter capacitor
23DTInput to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in
25DRInput to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in
26TIP
27TIPX Output of tip power amplifier.
28RINGXOutput of ring power amplifier.
3, 10, 17,
24
SENSE
CC
BAT
SG
DC
EE
TX
SENSE
N/CNo internal connection.
Internally connected to output of RING power amplifier.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
5V power supply.
Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET
an open collector with an internal pull-up of approximately 15kΩ to V
or Standby) of the SLIC.
or Standby) of the SLIC.
DC feed current programming resistor pin. Constant current feed is programmed by resistors R
connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to AGND
to isolate the AC signal components.
between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into the RSN
pin. The constant current programming resistors and the networks for program receive gain and 2-wire impedance all
connect to this pin.
-5V power supply.
Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming the
2-wire input impedance connects between this pin and RSN.
loop current. The other end of C
current. The other end of C
is also connected between this pin and VEE.
C
D
the SLIC with inputs DT and DR.
the SLIC with inputs DT and DR.
Internally connected to output of tip power amplifier.
output.
is connected to HPT.
HP
is connected to HPR.
HP
HP
output when set to logic level zero and disables DET output when set to
CC.
and R
DC1
. C
HP
. C
is required to properly separate the ring AC current from the DC
HP
is required to properly separate the tip AC current from the DC loop
HP
DC2
output is
2
Block Diagram
www.BDTIC.com/Intersil
HC5526
RINGRLY
DT
DR
TIP
RING
HPT
HPR
V
BAT
V
V
AGND
BGND
CC
EE
RING RELAY
RING TRIP
DETECTOR
INTERFACE
BIAS
DRIVER
2-WIRE
LOOP CURRENT
DETECTOR
GROUND KEY
DETECTOR
4-WIRE
INTERFACE
VF SIGNAL
PATH
DIGITAL
MULTIPLEXER
V
TX
RSN
E0
E1
C1
C2
DET
R
D
R
DC
RSG
3
HC5526
www.BDTIC.com/Intersil
Absolute Maximum RatingsThermal Information
Operating Temperature Range . . . . . . . . . . . . . . . . -40oC to 110oC
Power Supply (-40
Supply Voltage V
Supply Voltage V
Supply Voltage V
C ≤ TA ≤ 85oC)
Tipx or Ringx V oltag e, Contin uous (Referenced to GND) V
Tipx or Ringx, Pulse < 10ms, T
Tipx or Ringx, Pulse < 10µs, T
Tipx or Ringx, Pulse < 250ns, T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ
is measured with the component mounted on an evaluation PC board in free air.
JA
Typical Ope rating Conditions
These represent the conditions under which the part was developed and are suggested as guidelines.
OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE
VOLTAGE GAIN AND HARMONIC DISTORTION
4-WIRE RECEIVE PORT (RSN)
DC VoltageI
R
Sum Node Impedance (Guaranteed by
X
Design)
= 0mA-0-V
RSN
0.3kHz < f < 3.4kHz--20W
Current Gain-RSN to Metallic0.3kHz < f < 3.4kHz (Note 15, Figure 8)98010001020Ratio
FREQUENCY RESPONSE (OFF-HOOK)
2-Wire to 4-Wire0dBm at 1.0kHz, E
0.3kHz < f < 3.4kHz (Note 16, Figure 9)
4-Wire to 2-Wire0dBm at 1.0kHz, E
0.3kHz < f < 3.4kHz (Note 17, Figure 9)
4-Wire to 4-Wire0dBm at 1.0kHz, E
0.3kHz < f < 3.4kHz (Note 18, Figure 9)
RX
G
G
= 0V,
= 0V,
= 0V,
-0.2-0.2dB
-0.2-0.2dB
-0.2-0.2dB
INSERTION LOSS
2-Wire to 4-Wire0dBm, 1kHz (Note 19, Figure 9)-0.2-0.2dB
4-Wire to 2-Wire0dBm, 1kHz (Note 20, Figure 9)-0.2-0.2dB
GAIN TRACKING (Ref = -10dBm, at 1.0kHz)
2-Wire to 4-Wire-40dBm to +3dBm (Note 21, Figure 9)-0.1-0.1dB
2-Wire to 4-Wire-55dBm to -40dBm (Note 21, Figure 9)-±0.03-dB
4-Wire to 2-Wire-40dBm to +3dBm (Note 22, Figure 9)-0.1-0.1dB
6
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