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Data Sheet August 2003
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HC5523
FN4144.6
LSSGR/TR57 CO/Loop Carrier SLIC with
Low Power Standby
The HC5523 is a subscriber line interface circuit which is
interchangeable with Ericsson’s PBL3764A/4 for distributed
central office applications. Enhancements include immunity
to circuit latch-up during hot plug and absence of false
signaling in the presence of longitudinal currents.
The HC5523 is fabricated in a High Voltage Dielectrically
Isolated (DI) Bipolar Process that eliminates leakage
currents and device latch-up problems normally associated
with junction isolated ICs. The elimination of the leakage
currents results in improved circuit performance for wide
temperature extremes. The latch free benefit of the DI
process guarantees operation under adverse transient
conditions. This process feature makes the HC5523 ideally
suited for use in harsh outdoor environments.
Part Number Information
PART NUMBER
HC5523IM -40 to 85 28 Ld PLCC N28.45
HC5523IP -40 to 85 22 Ld PDIP E22.4
TEMP.
RANGE (oC) PACKAGE
PKG.
DWG. #
Features
• DI Monolithic High Voltage Process
• Programmable Current Feed (20mA to 60mA)
• Programmable Loop Current Detector Threshold and
Battery Feed Characteristics
• Ground Key and Ring Trip Detection
• Compatible with Ericsson’s PBL3764A/4
• Thermal Shutdown
• On-Hook Transmission
• Wide Battery Voltage Range (-24V to -58V)
• Low Standby Power
• Meets TR-NWT-000057 Transmission Requirements
o
C to 85oC Ambient Temperature Range
•-40
Applications
• Digital Loop Carrier Systems • Pair Gain
• Fiber-In-The-Loop ONUs • POTS
• Wireless Local Loop • PABX
• Hybrid Fiber Coax
• Related Literature
- AN9632, Operation of the HC5523/15 Evaluation Board
Block Diagram
RINGRLY
DT
DR
TIP
RING
HPT
HPR
V
BAT
V
CC
V
EE
AGND
BGND
1
RING RELAY
DRIVER
RING TRIP
DETECTOR
2-WIRE
INTERFACE
BIAS
LOOP CURRENT
DETECTOR
GROUND KEY
DETECTOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
4-WIRE
INTERFACE
VF SIGNAL
PATH
DIGITAL
MULTIPLEXER
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
V
TX
RSN
E0
E1
C1
C2
DET
R
D
R
DC
RSG
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
HC5523
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
Temperature, Humidity
Storage Temperature Range . . . . . . . . . . . . . . . . -65
Operating Temperature Range . . . . . . . . . . . . . . -40
Operating Junction Temperature Range . . . . . . . -40
Power Supply (-40
Supply Voltage V
Supply Voltage V
Supply Voltage V
Ground
Voltage between AGND and BGND. . . . . . . . . . . . . -0.3V to 0.3V
Relay Driver
Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to 20V
Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Ring Trip Comparator
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 5mA
Digital Inputs, Outputs (C1, C2, E0, E1, DET
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to V
Output Voltage (DET Not Active) . . . . . . . . . . . . . . . . . .0V to V
Output Current (DET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Tipx and Ringx Terminals (-40
Tipx or Ringx Voltage, Continuous (Referenced to GND). . . V
+2V
Tipx or Ringx, Pulse < 10ms, T
Tipx or Ringx, Pulse < 10µs, T
Tipx or Ringx, Pulse < 250ns, T
Tipx or Ringx Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
o
C ≤ TA ≤ 85oC)
to GND . . . . . . . . . . . . . . . . . . . . 0.5V to 7V
CC
to GND . . . . . . . . . . . . . . . . . . . . -7V to 0.5V
EE
to GND . . . . . . . . . . . . . . . . . .-80V to 0.5V
BAT
)
o
C ≤ TA ≤ +85oC)
> 10s . . . . V
REP
> 10s . . . V
REP
> 10s . . V
REP
o
C to 150oC
o
C to 110oC
o
C to 150oC
-20V to +5V
BAT
-40V to +10V
BAT
-70V to +15V
BAT
BAT
to 0V
CC
CC
BAT
to
Thermal Resistance (Typical, Note 1) θ
22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . 53
28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . 53
Continuous Power Dissipation at 70
22 Lead PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
Package Power Dissipation at 70
22 Lead PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
Derate above. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/
Maximum Junction Temperature Range . . . . . . . . . -40
Maximum Storage Temperature Range . . . . . . . . . -65
Maximum Lead Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .300
(Soldering 10s, PLCC Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . 543 Transistors, 51 Diodes
o
C
o
C, t < 100ms, t
REP
JA
> 1s
o
C to 150oC
o
C to 150oC
(oC/W)
o
o
o
o
C
C
C
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
is measured with the component mounted on an evaluation PC board in free air.
1. θ
JA
Typical Operating Conditions
These represent the conditions under which the part was developed and are suggested as guidelines.
PARAMETER CONDITIONS MIN TYP MAX UNITS
o
DC2
C
= 41.2kΩ,
PEAK
Case Temperature -40 - 100
with Respect to AGND -40oC to 85oC 4.75 - 5.25 V
V
CC
with Respect to AGND -40oC to 85oC -5.25 - -4.75 V
V
EE
with Respect to BGND -40oC to 85oC -58 - -24 V
V
BAT
Electrical Specifications T
PARAMETER CONDITIONS MIN TYP MAX UNITS
Overload Level 1% THD, Z
Longitudinal Impedance (Tip/Ring) 0 < f < 100Hz (Note 3, Figure 2) - 20 35 Ω/Wire
= -40oC to 85oC, VCC = +5V ±5%, V
A
= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin
R
D
number references in the figures refer to the 28 lead PLCC package.
= 600Ω, (Note 2, Figure 1) 3.1 - - V
L
= -5V ±5%, V
EE
= -48V, AGND = BGND = 0V, R
BAT
DC1
= R
2
HC5523
www.BDTIC.com/Intersil
Electrical Specifications T
= -40oC to 85oC, VCC = +5V ±5%, V
A
= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin
R
D
number references in the figures refer to the 28 lead PLCC package.
= -5V ±5%, V
EE
PARAMETER CONDITIONS MIN TYP MAX UNITS
1V
0 < f < 100Hz
E
R
600Ω
I
DCMET
23mA
V
TIP
27
L
V
TRO
RING28RSN
TX
19
R
T
600kΩ
E
R
RX
16
300kΩ
RX
FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT) FIGURE 2. LONGITUDINAL IMPEDANCE
LONGITUDINAL CURRENT LIMIT (TIP/RING)
Off-Hook (Active) No False Detections, (Loop Current),
LB > 45dB (Note 4, Figure 3A)
On-Hook (Standby), R
E
C
L
2.16µF
= ∞ No False Detections (Loop Current)
368Ω
368Ω
L
TIP
A
27
39kΩ
R
D
-5V
RING28R
A
DET
(Note 5, Figure 3B)
RSN
16
R
DC2
DC
14
41.2kΩ
R
DC1
41.2kΩ
C
DC
1.5µF
E
L
RMS
L
= -48V, AGND = BGND = 0V, R
BAT
(Continued)
A
T
C
2.16µF
300Ω
300Ω
368Ω
C2.16µF
C2.16µF
368Ω
V
T
V
R
A
R
LZT = VT/A
27 - - mA
8.5 - - mA
TIP
A
27
39kΩ
R
D
-5V
RING
A
28
TIP
27
RING28RSN
T
RSN
16
R
DC
14
DET
DC1
V
TX
19
16
R
DC2
41.2kΩ
= R
DC2
R
T
600kΩ
R
RX
300kΩ
LZR = VR/A
R
DC1
41.2kΩ
C
DC
1.5µF
= 41.2kΩ,
R
PEAK
Wire
PEAK
Wire
/
/
FIGURE 3A. OFF-HOOK FIGURE 3B. ON-HOOK
FIGURE 3. LONGITUDINAL CURRENT LIMIT
OFF-HOOK LONGITUDINAL BALANCE
Longitudinal to Metallic IEEE 455 - 1985, R
, RLT = 368Ω
LR
58 70 - dB
0.2kHz < f < 4.0kHz (Note 6, Figure 4)
Longitudinal to Metallic R
Metallic to Longitudinal FCC Part 68, Para 68.310
, RLT = 300Ω, 0.2kHz < f < 4.0kHz (Note
LR
6, Figure 4)
58 70 - dB
50 55 - dB
0.2kHz < f < 1.0kHz
1.0kHz < f < 4.0kHz (Note 7) 50 55 - dB
Longitudinal to 4-Wire 0.2kHz < f < 4.0kHz (Note 8, Figure 4) 58 70 - dB
Metallic to Longitudinal R
, RLT = 300Ω, 0.2kHz < f < 4.0kHz (Note
LR
9, Figure 5)
50 55 - dB
4-Wire to Longitudinal 0.2kHz < f < 4.0kHz (Note 10, Figure 5) 50 55 - dB
3
HC5523
www.BDTIC.com/Intersil
Electrical Specifications T
= -40oC to 85oC, VCC = +5V ±5%, V
A
= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin
R
D
number references in the figures refer to the 28 lead PLCC package.
PARAMETER CONDITIONS MIN TYP MAX UNITS
R
E
L
C
2.16µF
LT
R
LR
TIP
27
V
TR
RING
28
V
RSN
TX
19
16
FIGURE 4. LONGITUDINAL TO METALLIC AND
LONGITUDINAL TO 4-WIRE BALANCE
2-Wire Return Loss
= 20nF
C
HP
= -5V ±5%, V
EE
= -48V, AGND = BGND = 0V, R
BAT
DC1
= R
DC2
= 41.2kΩ,
(Continued)
R
R
T
600kΩ
R
RX
300kΩ
LT
300Ω
2.16µF
V
TX
C
V
L
R
LR
300Ω
E
TR
TIP
27
RING28RSN
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO
LONGITUDINAL BALANCE
0.2kHz to 0.5kHz (Note 11, Figure 6) 25 - - dB
0.5kHz to 1.0kHz (Note 11, Figure 6) 27 - - dB
1.0kHz to 3.4kHz (Note 11, Figure 6) 23 - - dB
V
TX
19
R
T
600kΩ
E
R
RX
16
300kΩ
RX
4
HC5523
www.BDTIC.com/Intersil
Electrical Specifications T
= -40oC to 85oC, VCC = +5V ±5%, V
A
= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin
R
D
number references in the figures refer to the 28 lead PLCC package.
= -5V ±5%, V
EE
= -48V, AGND = BGND = 0V, R
BAT
(Continued)
DC1
= R
DC2
= 41.2kΩ,
PARAMETER CONDITIONS MIN TYP MAX UNITS
TIP IDLE VOLTAGE
Active, I
Standby, I
= 0 --4-V
L
= 0 -<0 - V
L
RING IDLE VOLTAGE
Active, I
Standby, I
TIP-RING Open Loop Metallic Voltage, V
4-WIRE TRANSMIT PORT (V
Overload Level (Z
= 0 --44- V
L
= 0 ->-48- V
L
V
= -52V, RSG = 0Ω 43 - 47 V
BAT
> 20kΩ, 1% THD) (Note 12, Figure 7) 3.1 - - V
L
TX
TR
)
Output Offset Voltage EG = 0, ZL = ∞ (Note 13, Figure 7) -60 - 60 mV
Output Impedance (Guaranteed by Design) 0.2kHz < f < 03.4kHz - 5 20 W
2- to 4-Wire (Metallic to V
R
V
S
R
R
LR
) Voltage Gain 0.3kHz < f < 03.4kHz (Note 14, Figure 7) 0.98 1.0 1.02 V/V
TX
R
600Ω
E
2.16µF
L
C
I
DCMET
23mA
G
V
TR
TIP27V
19
RING28RSN
16
TX
R
T
600kΩ
R
RX
300kΩ
Z
D
TIP
27
V
M
Z
IN
RING28RSN
V
TX
19
R
T
600kΩ
R
RX
16
300kΩ
V
V
TXO
TX
PEAK
Z
L
FIGURE 6.
TWO-WIRE RETURN LOSS FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT),
OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE
VOLTAGE GAIN AND HARMONIC DISTORTION
4-WIRE RECEIVE PORT (RSN)
DC Voltage I
R
Sum Node Impedance (Gtd by Design) 0.2kHz < f < 3.4kHz - - 20 W
X
= 0mA - 0 - V
RSN
Current Gain-RSN to Metallic 0.3kHz < f < 3.4kHz (Note 15, Figure 8) 980 1000 1020 Ratio
FREQUENCY RESPONSE (OFF-HOOK)
2-Wire to 4-Wire 0dBm at 1.0kHz, E
RX
= 0V
-0.2 - 0.2 dB
0.3kHz < f < 3.4kHz (Note 16, Figure 9)
4-Wire to 2-Wire 0dBm at 1.0kHz, E
0.3kHz < f < 3.4kHz (Note 17, Figure 9)
4-Wire to 4-Wire 0dBm at 1.0kHz, E
0.3kHz < f < 3.4kHz (Note 18, Figure 9)
G
G
= 0V
= 0V
-0.2 - 0.2 dB
-0.2 - 0.2 dB
INSERTION LOSS
2-Wire to 4-Wire 0dBm, 1kHz (Note 19, Figure 9) -0.2 - 0.2 dB
4-Wire to 2-Wire 0dBm, 1kHz (Note 20, Figure 9) -0.2 - 0.2 dB
GAIN TRACKING (Ref = -10dBm, at 1.0kHz)
2-Wire to 4-Wire +3dBm to +7dBm (Note 21, Figure 9) -0.15 - 0.15 dB
2-Wire to 4-Wire -40dBm to +3dBm (Note 21, Figure 9) -0.1 - 0.1 dB
2-Wire to 4-Wire -55dBm to -40dBm (Note 21, Figure 9) -0.2 - 0.2 dB
4-Wire to 2-Wire -40dBm to +7dBm (Note 22, Figure 9) -0.1 - 0.1 dB
4-Wire to 2-Wire -55dBm to -40dBm (Note 22, Figure 9) -0.2 - 0.2 dB
5
HC5523
www.BDTIC.com/Intersil
Electrical Specifications T
= -40oC to 85oC, VCC = +5V ±5%, V
A
= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin
R
D
number references in the figures refer to the 28 lead PLCC package.
= -5V ±5%, V
EE
= -48V, AGND = BGND = 0V, R
BAT
(Continued)
DC1
= R
DC2
= 41.2kΩ,
PARAMETER CONDITIONS MIN TYP MAX UNITS
GRX = ((V
Where: V
and V
- V
)(300k))/(-3)(600)
TR2
is the Tip to Ring Voltage with V
is the Tip to Ring Voltage with V
TIP
27
V
TR
RING28R
R
600Ω
TR1
TR1
TR2
L
RSN
DC
= 0V
RSN
= -3V
RSN
R
RX
300kΩ
16
R
DC2
14
41.2kΩ
R
DC1
41.2kΩ
1.5µF
V
= 0V
RSN
= -3V
V
RSN
600Ω
C
DC
1/ωC < RL
C
V
TR
TIP27V
RING28RSN
R
L
I
DCMET
E
G
TX
19
16
R
T
600kΩ
R
RX
300kΩ
V
TX
E
RX
FIGURE 8. CURRENT GAIN-RSN TO METALLIC FIGURE 9. FREQUENCY RESPONSE, INSERTION LOSS,
GAIN TRACKING AND HARMONIC DISTORTION
NOISE
Idle Channel Noise at 2-Wire C-Message Weighting (No te 2 3 , Fi gu r e 10 ) - 8.5 - dBrnC
Psophometrical Weighting
- -81.5 - dBrnp
(Note 23, Figure 10)
Idle Channel Noise at 4-Wire C-Message Weighting (Note 24, Figure 10) - 8.5 - dBrnC
Psophometrical Weighting
- -81.5 - dBrnp
(Note 23, Figure 10)
HARMONIC DISTORTION
2-Wire to 4-Wire 0dBm, 1kHz (Note 25, Figure 7) - -65 -54 dB
4-Wire to 2-Wire 0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 9) - -65 -54 dB
BATTERY FEED CHARACTERISTICS
Constant Loop Current Tolerance
R
DCX
= 41.2kΩ
Loop Current Tolerance (Standby) I
Open Circuit Voltage (V
TIP
- V
)-40
RING
I
= 2500/(R
L
o
C to 85oC (Note 27)
-40
= (V
L
BAT
o
-40
C to 85oC (Note 28)
o
C to 85oC, (Active) RSG = ∞ 14 16.67 20 V
+ R
DC1
DC2
-3)/(RL +1800),
),
0.92I
0.8I
L
L
I
L
I
L
1.08I
1.2I
L
L
mA
mA
LOOP CURRENT DETECTOR
On-Hook to Off-Hook R
Off-Hook to On-Hook R
Loop Current Hysteresis R
= 39kΩ, -40oC to 85oC 372/R
D
= 39kΩ, -40oC to 85oC 325/R
D
= 39kΩ, -40oC to 85oC 25/R
D
465/R
D
405/R
D
60/R
D
558/R
D
485/R
D
95/R
D
D
mA
D
mA
D
mA
GROUND KEY DETECTOR
Tip/Ring Current Difference - Trigger (Note 29, Figure 11) 8 12 17 mA
Tip/Ring Current Difference - Reset (Note 29, Figure 11) 3 7 12 mA
Hysteresis (Note 29, Figure 11) 0 5 9 mA
6
HC5523
www.BDTIC.com/Intersil
Electrical Specifications T
= -40oC to 85oC, VCC = +5V ±5%, V
A
= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin
R
D
number references in the figures refer to the 28 lead PLCC package.
= -5V ±5%, V
EE
= -48V, AGND = BGND = 0V, R
BAT
(Continued)
DC1
= R
DC2
= 41.2kΩ,
PARAMETER CONDITIONS MIN TYP MAX UNITS
600Ω
TIP27V
R
L
V
TR V
RING28RSN
TX
19
16
R
T
600kΩ
R
RX
300kΩ
TIP
27
TX
RING28R
DET
RSN
16
DC
14
R
DC2
41.2kΩ
E1 = C1 = 0, C2 = 1
R
DC1
41.2kΩ
C
DC
1.5µF
FIGURE 10. IDLE CHANNEL NOISE FIGURE 11. GROUND KEY DETECT
RING TRIP DETECTOR (DT, DR)
Offset Voltage Source Res = 0 -20 - 20 mV
Input Bias Current Source Res = 0 -360 - 360 nA
Input Common-Mode Range Source Res = 0 V
+1 - 0 V
BAT
Input Resistance Source Res = 0, Unbalanced 1 - - MΩ
Source Res = 0, Balanced 3 - - MΩ
RING RELAY DRIVER
V
at 25mA IOL = 25mA - 0.2 0.6 V
SAT
Off-State Leakage Current V
= 12V - - 10 µA
OH
DIGITAL INPUTS (E0, E1, C1, C2)
Input Low Voltage, V
Input High Voltage, V
Input Low Current, I
Input Low Current, I
IL
IH
: C1, C2 VIL = 0.4V -200 - - µA
IL
: E0, E1 VIL = 0.4V -100 - - µA
IL
Input High Current V
DETECTOR OUTPUT (DET
Output Low Voltage, V
Output High Voltage, V
)
OL
OH
= 2.4V - - 40 µA
IH
IOL = 2mA - - 0.45 V
IOH = 100µA2.7--V
0-0.8V
2-VCCV
Internal Pull-Up Resistor 10 15 20 k
POWER DISSIPATION (V
BAT
= -48V)
Open Circuit State C1 = C2 = 0 - 26.3 41 mW
On-Hook, Standby C1 = C2 = 1 - 37.5 57 mW
On-Hook, Active C1 = 0, C2 = 1, R
Off-Hook, Active C1 = 0, C2 = 1, R
= High Impedance - 110 216 mW
L
= 600Ω -1.11.4W
L
TEMPERATURE GUARD
Thermal Shutdown 150 - 180
SUPPLY CURRENTS
Open Circuit State (C1, 2 = 0, 0)
On-Hook
Standby State (C1, 2 = 1, 1)
On-Hook
(V
BAT
= -28V)
I
CC
I
EE
I
BAT
I
CC
I
EE
I
BAT
-1.32.0mA
-0.60.9mA
- 0.35 0.55 mA
- 1.6 2.25 mA
- 0.62 0.9 mA
- 0.55 0.85 mA
Ω
ο
C
7
HC5523
www.BDTIC.com/Intersil
Electrical Specifications T
PARAMETER CONDITIONS MIN TYP MAX UNITS
Active State (C1, 2 = 0, 1)
On-Hook
PSRR
V
to 2 or 4-Wire Port (Note 30, Figure 12) - 40 - dB
CC
V
to 2 or 4-Wire Port (Note 30, Figure 12) - 40 - dB
EE
V
to 2 or 4-Wire Port (Note 30, Figure 12) - 40 - dB
BAT
= -40oC to 85oC, VCC = +5V ±5%, V
A
= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin
R
D
number references in the figures refer to the 28 lead PLCC package.
I
CC
I
EE
I
BAT
-48V SUPPLY
+5V SUPPLY
-5V SUPPLY
R
L
600Ω
TIP27V
RING28RSN
100mV
TX
19
16
= -5V ±5%, V
EE
, 50Hz TO 4kHz
RMS
R
T
600kΩ
R
RX
300kΩ
= -48V, AGND = BGND = 0V, R
BAT
PSRR = 20 log (V
V
TX
= R
DC1
(Continued)
-3.75.8mA
-1.11.8mA
-2.23.7mA
)
TX/VIN
DC2
= 41.2kΩ,
FIGURE 12. POWER SUPPLY REJECTION RATIO
Circuit Operation and Design Information
The HC5523 is a current feed voltage sense Subscriber Line
Interface Circuit (SLIC). This means that for short loop
applications the SLIC provides a programed constant current to
the tip and ring terminals while sensing the tip to ring voltage.
The following discussion separates the SLIC’s operation into
its DC and AC paths, then follows up with additional circuit
and design information.
Constant Loop Current (DC) Path
SLIC in the Active Mode
The DC path establishes a constant loop current that flows
out of tip and into the ring terminal. The loop current is
programmed by resistors R
the R
the voltage across R
pin (Figure 13). The RDC voltage is determined by
DC
in the saturation guard circuit. Under
1
constant current feed conditions, the voltage drop across R
sets the R
flows through R
establishes a current (I
+R
DC2
voltage to -2.5V. This occurs when current
DC
into the current source I2. The RDC voltage
1
RSN
). This current is then multiplied by 1000, in the loop
current circuit, to become the tip and ring loop currents.
For the purpose of the following discussion, the saturation
guard voltage is defined as the maximum tip to ring voltage
at which the SLIC can provide a constant current for a given
battery and overhead voltage.
, R
DC1
and the voltage on
DC2
) that is equal to V
RDC
/(R
DC1
For loop resistances that result in a tip to ring voltage less
than the saturation guard voltage the loop current is defined
as:
I
L
where: I
R
Capacitor CDC between R
signals from the battery feed control loop. The value of C
2.5V
------------------------------------- - 1000×= (EQ. 1)
+
R
DC1RDC2
= Constant loop current.
L
DC1
and R
= Loop current programming resistors.
DC2
DC1
and R
removes the VF
DC2
DC
is determined by Equation 2:
DC
×=
R
DC1
C
1
T
---------------
---------------+
R
1
DC2
(EQ. 2)
where T = 30ms
NOTE: The minimum CDC value is obtained if R
1
Figure 14 illustrates the relationship between the tip to ring
DC1
= R
DC2
voltage and the loop resistance. For a 0Ω loop resistance both
tip and ring are at V
/2. As the loop resistance increases,
BAT
so does the voltage differential between tip and ring. When
this differential voltage becomes equal to the saturation guard
voltage, the operation of the SLIC’s loop feed changes from a
constant current feed to a resistive feed. The loop current in
the resistive feed region is no longer constant but varies as a
function of the loop resistance.
8
+
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I
I
RING
TIP
TIP
RING
-
I
TIP
I
RING
+
A
HC5523
FIGURE 13. DC LOOP CURRENT
V
= -48V, IL = 23mA, RSG = 4.0kΩ
0
-10
-20
-30
-40
TIP TO RING VOLTAGE (V)
-50
SATURATION
GUARD VOLTAGE
CONSTANT CURRENT
FEED REGION
SATURATION
GUARD VOLTAGE
01.2K
BAT
RESISTIVE FEED
LOOP RESISTANCE (Ω)
FIGURE 14. VTR vs R
REGION
L
V
TIP
V
RING
∞
Figure 15 shows the relationship between the saturation
guard voltage, the loop current and the loop resistance.
Notice from Figure 15 that for a loop resistance <1.2kΩ
(R
= 4.0kΩ) the SLIC is operating in the constant current
SG
feed region and for resistances >1.2kΩ the SLIC is operating
in the resistive feed region. Operation in the resistive feed
region allows long loop and off-hook transmission by
keeping the tip and ring voltages off the rails. Operation in
this region is transparent to the customer.
50
40
30
V
= -48V, RSG = 4.0kΩ
BAT
CONSTANT CURRENT
FEED REGION
SATURATION GUARD
VOLTAGE, V
TR
= 38V
HC5523
LOOP CURRENT
CIRCUIT
SATURATION GUARD
CIRCUIT
A
1
I
1
-5V
2
I
2
The Saturation Guard circuit (Figure 13) monitors the tip to
ring voltage via the transconductance amplifier A
generates a current that is proportional to the tip to ring
voltage difference. I
current until the tip to ring voltage exceeds 12.5V. When the
tip to ring voltage exceeds 12.5V (with no R
supplies more current than I
A
amplifies its input current by a factor of 12 and the current
2
through R
output current from A
voltage across R
decreases. This results in a corresponding decrease in the
loop current. The R
saturation guard reference voltage beyond 12.5V. Equation
3 gives the relationship between the R
the programmable saturation guard reference voltage:
V
SGREF
where:
V
SGREF
= Saturation Guard programming resistor.
R
SG
When the Saturation guard reference voltage is exceeded,
the tip to ring voltage is calculated using Equation 4:
V
TRRL
V
TX
I
-5V
RSN
-
+
R
1
-
17.3kΩ
+
is internally set to sink all of A1’s
1
RSN
R
DC
-2.5V
R
SG
-5V
R
SG
SG
can sink. When this happens
1
becomes the difference between I2 and the
1
12.5
. As the current from A2 increases, the
2
decreases and the output voltage on RDC
1
pin provides the ability to increase the
SG
resistor value and
SG
5
510•
-----------------------------------+=
RSG17300+
= Saturation Guard reference voltage.
16.66 5 105• RSG17300+()⁄+
------------------------------------------------------------ ------------------------×=
R
LRDC1RDC2
+()600⁄+
R
RX
R
DC1
R
DC2
. A1
1
resistor) A1
C
DC
(EQ. 3)
(EQ. 4)
V
= -24V, RSG = ∞
BAT
RESISTIVE FEED
REGION
10 20
LOOP CURRENT (mA)
4kΩ
1.5kΩ
FIGURE 15. VTR vs IL and R
30
2kΩ
700Ω <400Ω
<1.2kΩ
SATURATION GUARD
VOLTAGE, V
RSG = 4.0kΩ100kΩ
RSG = ∞Ω
L
TR
= 13V
where:
V
= Voltage differential between tip and ring.
TR
RL = Loop resistance.
For on-hook transmission RL = ∞, Equation 4 reduces to:
16.66
V
TR
R
R
TIP TO RING VOLTAGE (V)
20
10
0
0
L
100kΩ
L
9
-----------------------------------+=
R
SG
•
510
17300+
5
(EQ. 5)
I
HC5523
www.BDTIC.com/Intersil
M
TIP
R
F
Z
L
Z
+
V
TR
-
TR
+
E
G
-
RING
+
V
TX
-
I
M
R
F
+
-
HC5523
FIGURE 16. SIMPLIFIED AC TRANSMISSION CIRCUIT
A = 250
1
A = 4
A = 250
V
TX
RSN
1000
+
V
Z
T
I
M
TX
-
Z
RX
+
V
RX
-
The value of R
should be calculated to allow maximum
SG
(AC) Transmission Path
loop length operation. This requires that the saturation guard
reference voltage be set as high as possible without clipping
the incoming or outgoing VF signal. A voltage margin of -4V
on tip and -4V on ring, for a total of -8V margin, is
recommended as a general guideline. The value of R
SG
is
calculated using Equation 6:
--------------------------- ---------------------------- ---------------------------- ---------------------------- ---------------------------- --- 17300–
R
=
SG
V
–()1
BATVMAR
5105•
R
+()
DC1RDC2
---------------------------- ------------------+
600R
L
16.66V–×
(EQ. 6)
where:
V
= Battery voltage.
BAT
V
= Voltage Margin. Recommended value of -8V to
MAR
allow a maximum overload level of 3.1V peak.
For on-hook transmission R
510
R
--------------------------------------------------------------- -- - 17300–=
SG
V
BATVMAR
•
= ∞, Equation 6 reduces to:
L
5
16.66V––
(EQ. 7)
SLIC in the Active Mode
Figure 16 shows a simplified AC transmission model. Circuit
analysis yields the following design equations:
V
TRVTXIM2RF
V
V
TX
RX
---------- -
-----------+
Z
Z
T
RX
V
TREGIMZL
where:
V
= Is the AC metallic voltage between tip and ring,
TR
including the voltage drop across the fuse resistors R
VTX = Is the AC metallic voltage. Either at the ground
referenced 4-wire side or the SLIC tip and ring terminals.
I
= Is the AC metallic current.
M
= Is a fuse resistor.
R
F
•+=
I
M
------------ -=
1000
•–=
ZT = Is used to set the SLIC’s 2-wire impedance.
SLIC in the Standby Mode
Overall system power is saved by configuring the SLIC in the
standby state when not in use. In the standby state the tip and
ring amplifiers are disabled and internal resistors are connected
between tip to ground and ring to V
. This connection
BAT
enables a loop current to flow when the phone goes off-hook.
The loop current detector then detects this current and the SLIC
is configured in the active mode for voice transmission. The
loop current in standby state is calculated as follows:
V
I
--------------------------------≈
L
R
BAT
L
3V–
1800Ω+
(EQ. 8)
where:
I
= Loop current in the standby state.
L
RL = Loop resistance.
VRX = Is the analog ground referenced receive signal.
= Is used to set the 4-wire to 2-wire gain.
Z
RX
EG = Is the AC open circuit voltage.
ZL = Is the line impedance.
(AC) 2-Wire Impedance
The AC 2-wire impedance (ZTR) is the impedance looking
into the SLIC, including the fuse resistors, and is calculated
as follows:
Let V
= 0. Then from Equation 10
RX
I
M
V
TXZT
------------ -•=
1000
(EQ. 9)
(EQ. 10)
(EQ. 11)
.
F
(EQ. 12)
V
= Battery voltage.
BAT
10
HC5523
www.BDTIC.com/Intersil
ZTR is defined as:
V
TR
TR
-----------=
I
M
Z
Substituting in Equation 9 for V
2R
V
TX
---------- -
Z
TR
I
M
-----------------------+=
•
FIM
I
M
Substituting in Equation 12 for V
Z
T
+=
------------ - 2R
Z
TR
1000
F
TR
TX
(EQ. 13)
(EQ. 14)
(EQ. 15)
Therefore
Z
1000 ZTR2RF–()•=
T
(EQ. 16)
Equation 16 can now be used to match the SLIC’s
impedance to any known line impedance (ZTR).
Example:
Calculate ZT to make ZTR = 600Ω in series with 2.16µF.
R
=20Ω.
F
Z
T
•=
1000 600
1
----------------------------------------- 220•–+
jω 2.16• 10
•
6–
Transhybrid Circuit
The purpose of the transhybrid circuit is to remove the
receive signal (V
preventing an echo on the transmit side. This is
accomplished by using an external op amp (usually part of
the CODEC) and by the inversion of the signal from the
4-wire receive port (RSN) to the 4-wire transmit port (V
Figure 17 shows the transhybrid circuit. The input signal will
be subtracted from the output signal if I
analysis yields the following equation:
V
V
TX
TX
RX
-----------+ 0=
Z
B
-----------
R
The value of Z
R–
Z
B
TX
Where VRX/VTX equals 1/ A
Therefore
ZBR
TX
) from the transmit signal (VTX), thereby
RX
equals I2. Node
1
is then
B
V
RX
-----------•=
V
TX
4-4
Z
T
++
------------ - 2R
Z
1000
RX
--------------------------------------------•=
-----------•
Z
T
FZL
Z
2R
+
L
F
).
TX
(EQ. 21)
(EQ. 22)
(EQ. 23)
ZT = 560kΩ in series with 2.16nF
(AC) 2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is equal to VTX/ V
From Equations 9 and 10 with VRX = 0
V
A
24–
TX
-----------
V
TR
------------------------------------------==
Z
T
Z
1000⁄
T
1000⁄ 2R
+
F
TR
(AC) 4-Wire to 2-Wire Gain
The 4-wire to 2-wire gain is equal to VTR/V
From Equations 9, 10 and 11 with EG = 0
V
TR
42–
-----------
V
RX
A
Z
T
-----------–
Z
RX
Z
--------------------------------------------•==
Z
T
++
------------ - 2R
1000
L
FZL
For applications where the 2-wire impedance (Z
Equation 15) is chosen to equal the line impedance (Z
expression for A
Z
A
42–
-----------–
Z
RX
1
T
-- -•=
2
simplifies to:
4-2
RX
TR
,
(AC) 4-Wire to 4-Wire Gain
The 4-wire to 4-wire gain is equal to VTX/V
From Equations 9, 10 and 11 with EG = 0
TX
RX
Z
-----------–
Z
RX
V
44–
-----------
V
A
T
--------------------------------------------•==
Z
+
L2RF
Z
T
------------ - 2R
++
1000
FZL
RX
(EQ. 17)
(EQ. 18)
), the
L
(EQ. 19)
(EQ. 20)
Example:
Given: RTX = 20kΩ, ZRX = 280kΩ, ZT = 562kΩ (standard
value), R
= 20Ω and Z = 600Ω
F
The value of ZB = 18.7kΩ
R
FB
I
2
R
TX
I
1
Z
T
Z
RX
Z
B
-
+
+
V
TX
-
+
V
RX
-
HC5523
V
TX
RSN
CODEC/
FILTER
FIGURE 17. TRANSHYBRID CIRCUIT
Supervisory Functions
The loop current, ground key and the ring trip detector
outputs are multiplexed to a single logic output pin called
DET
. See Table 1 to determine the active detector for a
given logic input. For further discussion of the logic circuitry
see section titled “Digital Logic Inputs”.
11
Before proceeding with an explanation of the loop current
www.BDTIC.com/Intersil
detector, ground key detector and later the longitudinal
impedance, it is important to understand the difference
between a “metallic” and “longitudinal” loop currents. Figure 18
illustrates 3 different types of loop current encountered.
Case 1 illustrates the metallic loop current. The definition of
a metallic loop current is when equal currents flow out of tip
and into ring. Loop current is a metallic current.
Cases 2 and 3 illustrate the longitudinal loop current. The
definition of a longitudinal loop current is a common mode
current, that flows either out of or into tip and ring
simultaneously. Longitudinal currents in the on-hook state
result in equal currents flowing through the sense resistors R
and R
(Figure 18). And longitudinal currents in the off-hook
2
1
state result in unequal currents flowing through the sense
resistors R
flowing away from the SLIC, the current through R
and R2. Notice that for case 2, longitudinal currents
1
is the
1
metallic loop current plus the longitudinal current; whereas the
current through R
is the metallic loop current minus the
2
longitudinal current. Longitudinal currents are generated when
the phone line is influenced by magnetic fields (e.g., power
lines).
Loop Current Detector
Figure 18 shows a simplified schematic of the loop current
and ground key detectors. The loop current detector works
by sensing the metallic current flowing through resistors R
and R
. This results in a current (IRD) out of the
2
transconductance amplifier (gm
of gm
and the metallic loop current. IRD then flows out the
1
) that is equal to the product
1
1
HC5523
R
pin and through resistor RD to VEE. The value of IRD is
D
equal to:
I
I
RD
The I
–
TIPIRING
----------------------------------- -
600
current results in a voltage drop across RD that is
RD
I
L
--------- -==
300
(EQ. 24)
compared to an internal 1.25V reference voltage. When the
voltage drop across R
configured for loop current detection, the DET
exceeds 1.25V, and the logic is
D
pin goes low.
The hysteresis resistor RH adds an additional voltage
effectively across R
, causing the on-hook to off-hook
D
threshold to be slightly higher than the off-hook to on-hook
threshold.
Taking into account the hysteresis voltage, the typical value
of R
for the on-hook to off-hook condition is:
D
R
--------------------------------------------------------------- -----------=
D
I
ON HO OK to OFF– HOOK–
465
(EQ. 25)
Taking into account the hysteresis voltage, the typical value
of R
for the off-hook to on-hook condition is:
D
--------------------------------------------------------------- -----------=
R
D
I
OFF H OOK to ON– HOOK–
A filter capacitor (C
375
) in parallel with RD will improve the
D
(EQ. 26)
accuracy of the trip point in a noisy environment. The value
of this capacitor is calculated using the following Equation:
T
------- -=
C
D
R
D
(EQ. 27)
where: T = 0.5ms
Ground Key Detector
ORDERING INFORMATION
CASE 1 CASE 2 CASE 3
I
METALLIC
←
I
METALLIC
→
I
LONGITUDINAL
←
I
LONGITUDINAL
←
I
LONGITUDINAL
I
LONGITUDINAL
gm1(I
METALLIC
+
-
TIP
RING
→
→
FIGURE 18. LOOP CURRENT AND GROUND KEY DETECTORS
R
1
R
2
HC5523
gm
1
gm
2
R
H
-
+
GROUND
KEY
COMPARATOR
CURRENT
COMPARATOR
gm2(I
I
GK
+
-
D
1
DIGITAL MULTIPLEXER
LOOP
- I
TIP
RING
D
2
I
1
)
R
D
R
H
+
-
+
V
)
1.25V
REF
I
RD
C
R
D
D
-
V
EE
-5V
DET
12
A simplified schematic of the ground key detector is shown
www.BDTIC.com/Intersil
in Figure 18. Ground key, is the process in which the ring
terminal is shorted to ground for the purpose of signaling an
Operator or seizing a phone line (between the Central Office
and a Private Branch Exchange). The Ground Key detector
is activated when unequal current flow through resistors R
and R
. This results in a current (IGK) out of the
2
transconductance amplifier (gm
of gm
and the differential (I
2
less than the internal current source (I
) that is equal to the product
2
-I
TIP
) loop current. If IGK is
RING
), then diode D1 is on
1
and the output of the ground key comparator is low. If I
greater than the internal current source (I
), then diode D2 is
1
GK
1
is
on and the output of the ground key comparator is high. With
the output of the ground key comparator high, and the logic
configured for ground key detect, the DET
pin goes low. The
ground key detector has a built in hysteresis of typically 5mA
between its trigger and reset values.
HC5523
R
RT
RING
RELAY
FIGURE 19. RING TRIP CIRCUIT FOR BATTERY BACKED
RINGING
TIP
RING
C
R
3
E
RT
R4R
RG
R
1
2
V
BAT
RINGRLY
DT
DR
COMPARATOR
-
+
RING TRIP
HC5523
DET
Ring Trip Detector
Ring trip detection is accomplished with the internal ring trip
comparator and the external circuitry shown in Figure 19.
The process of ring trip is initiated when the logic input pins
are in the following states: E0 = 0, E1 = 1/0, C1 = 1 and
C2 = 0. This logic condition connects the ring trip
comparator to the DET
energize the ring relay. The ring relay connects the tip and
ring of the phone to the external circuitry in Figure 19. When
the phone is on-hook the DT pin is more positive than the
DR pin and the DET
DR is more positive than DT and DET
goes low, indicating that the phone has gone off-hook, the
SLIC is commanded by the logic inputs to go into the active
state. In the active state, tip and ring are once again
connected to the phone and normal operation ensues.
Figure 19 illustrates battery backed unbalanced ring injected
ringing. For tip injected ringing just reverse the leads to the
phone. The ringing source could also be balanced.
NOTE: The DET output will toggle at 20Hz because the DT input is
not completely filtered by C
and determine if the DET
the off-hook condition is indicated.
output, and causes the Ringrly pin to
output is high. For off-hook conditions
goes low. When DET
. Software can examine the duty cycle
RT
pin is low for more that half the time, if so
Longitudinal Impedance
The feedback loop described in Figure 20(A, B) realizes the
desired longitudinal impedances from tip to ground and from
ring to ground. Nominal longitudinal impedance is resistive
and in the order of 22Ω.
In the presence of longitudinal currents this circuit attenuates
the voltages that would otherwise appear at the tip and ring
terminals, to levels well within the common mode range of
the SLIC. In fact, longitudinal currents may exceed the
programmed DC loop current without disturbing the SLIC’s
VF transmission capabilities.
The function of this circuit is to maintain the tip and ring
voltages symmetrically around V
longitudinal currents. The differential transconductance
amplifiers G
and GR accomplish this by sourcing or sinking
T
the required current to maintain V
When a longitudinal current is injected onto the tip and ring
inputs, the voltage at V
V
/2. When VC changes by the amount DVC, this change
BAT
moves from it’s equilibrium value
C
appears between the input terminals of the differential
transconductance amplifiers G
and G
are the differential currents ∆I1 and ∆I2, which in turn
R
feed the differential inputs of current sources I
respectively. I
and IR have current gains of 250 single
T
ended and 500 differentially, thus leading to a change in I
and I
that is equal to 500(∆I) and 500(∆I2).
R
The circuit shown in Figure 20(B) illustrates the tip side of
the longitudinal network. The advantages of a differential
input current source are: improved noise since the noise due
to current source 2I
is now correlated, power savings due
O
to differential current gain and minimized offset error at the
Operational Amplifier inputs via the two 5kΩ resistors.
/2, in the presence of
BAT
at V
C
and GR. The output of GT
T
BAT
/2.
T
and IR
T
13
HC5523
www.BDTIC.com/Intersil
Digital Logic Inputs
Table 1 is the logic truth table for the TTL compatible logic
input pins. The HC5523 has two enable inputs pins (E0, E1)
and two control inputs pins (C1, C2).
The enable pin E0 is used to enable or disable the DET
output pin. The DET
pin is enabled if E0 is at a logic level 0
and disabled if E0 is at a logic level 1.
The enable pin E1 gates the ground key detector to the DET
output with a logic level 0, and gates the loop or ring trip
detector to the DET
output with a logic level 1.
I
LONG
I
I
LONG
LONG
I
LONG
∆V
∆V
TIP
+
T
-
R
LARGE
R
LARGE
RING
+
R
-
HC5523
+
V
C
-
∆I
1
∆I
2
A combination of the control pins C1 and C2 is used to select
1 of the 4 possible operating states. A description of each
operating state and the control logic follow:
Open Circuit State (C1 = 0, C2 = 0)
In this state the SLIC is effectively off. All detectors and both
the tip and ring line drive amplifiers are powered down,
presenting a high impedance to the line. Power dissipation is
∆I
1
G
T
V
BAT
G
R
∆I
2
at a minimum.
/2
RING
TIP
V
R
LARGE
C
R
LARGE
TIP CURRENT SOURCE
WITH DIFFERENTIAL IN PUTS
20Ω
5kΩ
5kΩ
∆I
1
2I
0
TIP DIFFERENTIAL
TRANSCONDUCTANCE
AMPLIFIER
-
+
∆I
1
V
BAT
/2
G
T
I
T
I
R
FIGURE 20A. FIGURE 20B.
FIGURE 20. LONGITUDINAL IMPEDANCE NETWORK
Active State (C1 = 0, C2 = 1)
The tip output is capable of sourcing loop current and for open
circuit conditions is about -4V from ground. The ring output is
capable of sinking loop current and for open circuit conditions is
about V
+4V. VF signal transmission is normal. The loop
BAT
current and ground key detectors are both active, E0 and E1
determine which detector is gated to the DET
output.
Ringing State (C1 = 1, C2 = 0)
The ring relay driver and the ring trip detector are activated.
Both the tip and ring line drive amplifiers are powered down.
Both tip and ring are disconnected from the line via the
external ring relay.
Standby State (C1 = 1, C2 = 1)
Both the tip and ring line drive amplifiers are powered down.
Internal resistors are connected between tip to ground and
ring to V
condition. The loop current and ground key detectors are
both active, E0 and E1 determine which detector is gated to
the DET
to allow loop current detect in an off-hook
BAT
output.
AC Transmission Circuit Stability
To ensure stability of the AC transmission feedback loop two
compensation capacitors C
and CRC are required.
TC
Figure 21 (Application Circuit) illustrates their use.
Recommended value is 2200pF.
AC-DC Separation Capacitor, C
HP
The high pass filter capacitor connected between pins HPT
and HPR provides the separation between circuits sensing
tip to ring DC conditions and circuits processing AC signals.
A 10nf C
will position the low end frequency response
HP
3dB break point at 48Hz. Where:
f
3dB
where R
-----------------------------------------------------=
1
2 π• R
• CHP•()
HP
= 330kΩ
HP
(EQ. 28)
Thermal Shutdown Protection
The HC5523’s thermal shutdown protection is invoked if a
fault condition on the tip or ring causes the temperature of
the die to exceed 160
a high impedance state and will remain there until the
o
C. If this happens, the SLIC goes into
14
HC5523
www.BDTIC.com/Intersil
temperature of the die cools down by about 20oC. The SLIC
will return back to its normal operating mode, providing the
fault condition has been removed.
Positive transients on tip or ring are clamped to within a
couple of volts above ground via diodes D
normal operating conditions D
and D2 are reverse biased
1
and D2. Under
1
and out of the circuit.
Surge Voltage Protection
The HC5523 must be protected against surge voltages and
power crosses. Refer to “Maximum Ratings” TIPX and
RINGX terminals for maximum allowable transient tip and
ring voltages. The protection circuit shown in Figure 21
utilizes diodes together with a clamping device to protect tip
Negative transients on tip and ring are clamped to within a
couple of volts below ground via diodes D
3
help of a Surgector. The Surgector is required to block
conduction through diodes D
and D4 under normal
3
operating conditions and allows negative surges to be
returned to system ground.
and ring against high voltage transients.
SLIC Operating States
TABLE 1. LOGIC TRUTH TABLE
E0 E1 C1 C2 SLIC OPERATING STATE ACTIVE DETECTOR DET
0 0 0 0 Open Circuit No Active Detector Logic Level High
0 0 0 1 Active Ground Key Detector Ground Key Status
0 0 1 0 Ringing No Active Detector Logic Level High
0 0 1 1 Standby Ground Key Detector Ground Key Status
0 1 0 0 Open Circuit No Active Detector Logic Level High
0 1 0 1 Active Loop Current Detector Loop Current Status
0 1 1 0 Ringing Ring Trip Detector Ring Trip Status
0 1 1 1 Standby Loop Current Detector Loop Current Status
and D4 with the
OUTPUT
1 0 0 0 Open Circuit No Active Detector
1 0 0 1 Active Ground Key Detector
1 0 1 0 Ringing No Active Detector
1 0 1 1 Standby Ground Key Detector
1 1 0 0 Open Circuit No Active Detector
1 1 0 1 Active Loop Current Detector
1 1 1 0 Ringing Ring Trip Detector
1 1 1 1 Standby Loop Current Detector
The fuse resistors (RF) serve a dual purpose of being
nondestructive power dissipaters during surge and fuses
The analog and digital grounds should be tied together at the
device.
when the line in exposed to a power cross.
Notes
Power-Up Sequence
The HC5523 has no required power-up sequence. This is a
result of the Dielectrically Isolated (DI) process used in the
fabrication of the part. By using the DI process, care is no
longer required to insure that the substrate be kept at the
most negative potential as with junction isolated ICs.
Printed Circuit Board Layout
Care in the printed circuit board layout is essential for proper
operation. All connections to the RSN pin should be made as
close to the device pin as possible, to limit the interference
that might be injected into the RSN terminal. It is good
practice to surround the RSN pin with a ground plane.
2. Overload Level (Two-Wire port) - The overload level is specified at the 2-wire port (V
receive port (E
amplitude of E
ence Figure 1.
3. Longitudinal Impedance - The longitudinal impedance is
computed using the following equations, where TIP and RING
voltages are referenced to ground. L
are defined in Figure 2.
A
T
(TIP) L
(RING) LZR = VR/A
where: EL = 1V
4. Longitudinal Current Limit (Off-Hook Active) - Off-Hook
(Active, C
by increasing the amplitude of E
Logic Level High
) with the signal source at the 4-wire
TR0
). I
RX
until 1% THD is measured at V
RX
= VT/A
ZT
T
R
(0Hz to 100Hz)
RMS
= 1, C2 = 0) longitudinal current limit is determined
1
= 30mA, RSG = 4kΩ, increase the
DCMET
, LZR, VT, VR, AR and
ZT
(Figure 3A) until the 2-wire
L
TRO
. Refer-
15
HC5523
www.BDTIC.com/Intersil
longitudinal balance drops below 45dB. DET pin remains low
(no false detection).
5. Longitudinal Current Limit (On -Hook Standby) - On-Hook
(Active, C
by increasing the amplitude of E
longitudinal balance drops below 45dB. DET
= 1, C2 = 1) longitudinal current limit is determined
1
(Figure 3B) until the 2-wire
L
pin remains high
(no false detection).
6. Longitudinal to Metallic Balance - The longitudinal to metallic balance is computed using the following equation:
BLME = 20 • log (E
Figure 4.
), where: EL and VTR are defined in
L/VTR
7. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
metallic to longitudinal balance is defined in this spec.
8. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
balance is computed using the following equation:
BLFE = 20 • log (E
),: EL and VTX are defined in Figure 4.
L/VTX
9. Metallic to Longitudinal Balance - The metallic to longitudi-
nal balance is computed using the following equation:
BMLE = 20 • log (E
where: E
and ERX are defined in Figure 5.
TR, VL
TR/VL
), ERX = 0
10. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal balance is computed using the following equation:
BFLE = 20 • log (E
where: E
and ETR are defined in Figure 5.
RX, VL
), ETR = source is removed.
RX/VL
11. Two-Wire Return Loss - The 2-wire return loss is computed
using the following equation:
r = -20 • log (2V
where: Z
impedance of the line, nominally 600Ω. (Reference Figure 6).
= The desired impedance; e.g., the characteristic
D
M/VS
)
12. Overload Level (4-Wire port) - The overload level is specified
at the 4-wire transmit port (V
the 2-wire port, I
= 23mA, ZL = 20kΩ, RSG = 4kΩ (Refer-
DCMET
ence Figure 7). Increase the amplitude of E
measured at V
the 4-wire port is equal to 1.
. Note that the gain from the 2-wire port to
TXO
) with the signal source (EG) at
TXO
until 1% THD is
G
13. Output Offset Voltage - The output offset vo ltage is specified
with the following conditions: E
and is measured at VTX. EG, I
in Figure 7. Note: I
resistor between tip and ring.
DCMET
= 0, I
G
DCMET
is established with a series 600Ω
14. Two-Wire to Four-Wire (Metallic to V
2-wire to 4-wire (metallic to V
using the following equation.
G
= (VTX/VTR), EG = 0dBm0, VTX, VTR, and EG are defined
2-4
in Figure 7.
) voltage gain is computed
TX
= 23mA, ZL = ∞
DCMET
, VTX and ZL are defined
) Voltage Gain - The
TX
15. Current Gain RSN to Metallic - The current gain RSN to
Metallic is computed using the following equation:
[(R
+ R
)/(V
- V
K = I
M
and V
DC1
DC2
are defined in Figure 8.
RSN
RDC
)] K, IM, R
RSN
DC1
, R
DC2
, V
RDC
16. Two-Wire to Four-Wire Frequency Response - The 2-wire to
4-wire frequency response is measured with respect to
= 0dBm at 1.0kHz, ERX = 0V, I
E
G
quency response is computed using the following equation:
F
= 20 • log (VTX/VTR), vary frequency from 300Hz to
2-4
3.4kHz and compare to 1kHz reading.
, VTR, and EG are defined in Figure 9.
V
TX
= 23mA. The fre-
DCMET
17. Four-Wire to Two-Wire Frequency Response - The 4-wire to
2-wire frequency response is measured with respect to E
0dBm at 1.0kHz, E
= 0V, I
G
= 23mA. The frequency
DCMET
RX
response is computed using the following equation:
= 20 • log (VTR/ERX), vary frequency from 300Hz to
F
4-2
=
3.4kHz and compare to 1kHz reading.
V
and ERX are defined in Figure 9.
TR
18. Four-Wire to Four-Wire Frequency Response - The 4-wire
to 4-wire frequency response is measured with respect to E
= 0dBm at 1.0kHz, EG = 0V, I
response is computed using the following equation:
= 20 • log (VTX/ERX), vary frequency from 300Hz to
F
4-4
3.4kHz and compare to 1kHz reading.
and ERX are defined in Figure 9.
V
TX
= 23mA. The frequency
DCMET
RX
19. Two-Wire to Four-Wire Insertion Loss - The 2-wire to 4-wire
insertion loss is measured with respect to E
input signal, E
the following equation:
L
= 20 • log (VTX/VTR)
2-4
where: V
fuse resistors, R
= 0, I
RX
, VTR, and EG are defined in Figure 9. (Note: The
TX
, impact the insertion loss. The specified
F
insertion loss is for R
F
DCMET
= 0).
= 23mA and is computed using
= 0dBm at 1.0kHz
G
20. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire
insertion loss is measured based upon E
input signal, E
the following equation:
L
= 20 • log (VTR/ERX)
4-2
where: V
= 0, I
G
and ERX are defined in Figure 9.
TR
= 23mA and is computed using
DCMET
= 0dBm, 1.0kHz
RX
21. Two-Wire to Four-Wire Gain Tracking - The 2-wir e to 4-wire
gain tracking is referenced to measurements taken for E
-10dBm, 1.0kHz signal, E
RX
= 0, I
= 23mA and is com-
DCMET
=
G
puted using the following equation.
= 20 • log (VTX/VTR) vary amplitude -40dBm to +3dBm, or
G
2-4
-55dBm to -40dBm and compare to -10dBm reading.
and VTR are defined in Figure 9.
V
TX
22. Four-Wire to Two-Wire Gain Tracking - The 4- wire to 2-wire
gain tracking is referenced to measurements taken for E
-10dBm, 1.0kHz signal, E
puted using the following equation:
G
= 20 • log (VTR/ERX) vary amplitude -40dBm to +3dBm, or
4-2
-55dBm to -40dBm and compare to -10dBm reading.
and ERX are defined in Figure 9. The level is specified at
V
TR
= 0, I
G
= 23mA and is com-
DCMET
RX
the 4-wire receive port and referenced to a 600Ω impedance
level.
23. Two-Wire Idle Channel Noise - The 2-wire idle channel noise
is specified with the 2-wire port terminated in 600Ω (RL)
at V
TR
and with the 4-wire receive port grounded (Reference Figure
10).
24. Four-Wire Idle Channel Noise - The 4-wire idle channel noise
is specified with the 2-wire port terminated in 600Ω (RL).
at V
TX
The noise specification is with respect to a 600Ω impedance
level at V
Figure 10).
. The 4-wire receive port is grounded (Reference
TX
25. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic distortion is measured with the following conditions. E
1kHz, I
Figure 7).
= 23mA. Measurement taken at VTX. (Reference
DCMET
= 0dBm at
G
26. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic distortion is measured with the following conditions. E
Vary frequency between 300Hz and 3.4kHz, I
Measurement taken at V
. (Reference Figure 9).
TR
RX
DCMET
= 0dBm0.
= 23mA.
27. Constant Loop Current - The constant loop current is calculated using the following equation:
= 2500 / (R
I
L
DC1
+ R
DC2
)
28. Standby State Loop Current - The standby state loop current
is calculated using the following equation:
=
16
HC5523
www.BDTIC.com/Intersil
IL = [|V
29. Ground Key Detector - (TRIGGER) Increase the input current
to 8mA and verify that DET
(RESET) Decrease the input current from 17mA to 3mA and
verify that DET
(Hysteresis) Compare difference between trigger and reset.
30. Power Supply Rejection Ratio - Inject a 100mV
(50Hz to 4kHz) on V
puted using the following equation:
PSRR = 20 • log (V
12.
| - 3] / [RL +1800], TA = 25oC
BAT
goes low.
goes high.
, VCC and VEE supplies. PSRR is com-
BAT
). VTX and VIN are defined in Figure
TX/VIN
RMS
signal
17
HC5523
www.BDTIC.com/Intersil
Pin Descriptions
PLCC PDIP SYMBOL DESCRIPTION
1RING
2 7 BGND Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
48 V
5 9 RINGRLY Ring relay driver output.
610 V
711 R
8 12 E1 TTL compatible logic input. The logic state of E1 in conjunction with the logic state of C1 determines which detector
9 13 E0 TTL compatible logic input. Enables the DET
11 14 DET Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered
12 15 C2 TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active,
13 16 C1 TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active,
14 17 R
15 18 AGND Analog ground.
16 19 RSN Receive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that
18 20 V
19 21 V
20 22 HPR RING side of AC/DC separation capacitor C
21 1 HPT TIP side of AC/DC separation capacitor C
22 2 RD Loop current programming resistor. Resistor R
23 3 DT Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a
25 4 DR Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a
26 TIP
27 5 TIPX Output of tip power amplifier.
28 6 RINGX Output of ring power amplifier.
3, 10,
17, 24
CC
BAT
SENSE
N/C No internal connection.
Internally connected to output of RING power amplifier.
SENS
E
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
+5V power supply.
Battery supply voltage, -24V to -56V.
Saturation guard programming resistor pin.
SG
is gated to the DET
set to a logic level one.
(see Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET
output is an open collector with an internal pull-up of approximately 15kΩ to V
Ringing or Standby) of the SLIC.
Ringing or Standby) of the SLIC.
DC feed current programming resistor pin. Constant current feed is programmed by resistors R
DC
connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to
AGND to isolate the AC signal components.
flows between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into
the RSN pin. The constant current programming resistors and the networks for program receive gain and 2-wire
impedance all connect to this pin.
-5V power supply.
EE
Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming
TX
the 2-wire input impedance connects between this pin and RSN.
DC loop current. The other end of C
loop current. The other end of C
capacitor C
comparator in the SLIC with inputs DT and DR.
comparator in the SLIC with inputs DT and DR.
Internally connected to output of tip power amplifier.
output.
output when set to logic level zero and disables DET output when
. C
HP
is connected to HPT.
HP
is connected to HPR.
HP
is also connected between this pin and VEE.
D
HP
. C
HP
is required to properly separate the tip AC current from the DC
HP
sets the trigger level for the loop current detect circuit. A filter
D
CC.
is required to properly separate the ring AC current from the
DC1
and R
DC2
18
Pinouts
www.BDTIC.com/Intersil
RINGRLY
V
BAT
R
N/C
DET
SG
E1
E0
HC5523 (PLCC)
TOP VIEW
VCCN/C
5
6
7
8
9
10
11
12 13 14 15 16 17 18
C2
C1
HC5523
HC5523 (PDIP)
TOP VIEW
HPT
SENSE
BGND
RING
RINGX
1234
DC
R
AGND
RSN
TIPX
N/C
SENSE
TIP
262728
25
DR
24
N/C
23
DT
22
RD
21
HPT
20
HPR
19
V
TX
EE
V
RINGRLY
RD
DT
DR
TIPX
RINGX
BGND
V
CC
V
BAT
R
SG
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
HPR
V
TX
V
EE
RSN
AGND
R
DC
C1
C2
DET
E0
E1
19
Application Circuit
www.BDTIC.com/Intersil
HC5523
(V
BAT
R
RT
R
PTC
TIP
PTC
RING
RINGING
+ 90V
RMS
)
C
C
C
C
, CRC2200pF, 20%, 100V
TC
Relay Relay, 2C Contacts, 5V or 12V Coil
- D5IN4007 Diode
D
1
Surgector SGT27S10
PTC Polyswitch TR600-150
R
, RF2Line Resistor, 20Ω, 1% Match, 2 W
F1
C
3
R
R
F1
D
D
R
F2
+5V RELAY
OR
12V
RT
4
3
4
R
R
V
BAT
NOTE 31
Surgector
G
D
5
1
R
D
2
AK
D
6
-5V
D
1
C
TC
C
V
BAT
RC
-5V
R
SG
D
2
U1 SLIC (Subscriber Line Interface Circuit)
HC5526
U2 Combination CODEC/Filter e.g.
CD22354A or Programmable CODEC/
Filter, e.g. SLAC
1.5µF, 20%, 10V
DC
10nF, 20%, 100V (Note 2)
HP
0.39µF, 20%, 100V
RT
D
Diode, 1N4454
6
Carbon column resistor or thick film on
ceramic
21 HPT
22 RD
23 DT
25 DR
27 TIPX
2 BGND
4 V
CC
28 RINGX
6 V
BAT
5 RINGRLY
7 R
SG
R
DC1
CHP (NOTE 32)
U
HPR 20
1
V
19
TX
VEE 18
RSN 16
AGND 15
14
R
DC
C1 13
C2 12
DET
11
E
O
E
1
R1, R3200kΩ, 5%, 1/4W
910kΩ, 5%, 1/4W
R
2
1.2MΩ, 5%, 1/4W
R
4
R
18.7kΩ,1%, 1/4W
B
39kΩ, 5%, 1/4W
R
D
, R
41.2kΩ, 5%, 1/4W
DC2
R
20.0kΩ, 1%, 1/4W
FB
280kΩ, 1%, 1/4W
R
RX
562kΩ, 1%, 1/4W
R
T
R
20kΩ, 1%, 1/4W
TX
150Ω, 5%, 2W
R
RT
R
SGVBAT
V
BAT
= -28V, R
= -48V, R
R
FB
U
R
TX
-5V
R
DC2
9
8
= ∞
SG
= 21.4kΩ, 1/4W 5%
SG
R
R
B
T
R
RX
R
DC1
C
DC
2
-
+
CODEC/FILTER
NOTES:
31. It is recommended that the anodes of D
32. To meet the specified 25dB 2-wire return loss at 200Hz, C
and D4 be shorted to ground through a battery referenced surgector (SGT27S10).
3
needs to be 20nF, 20%, 100V.
HP
FIGURE 21. APPLICATION CIRCUIT
20
HC5523
www.BDTIC.com/Intersil
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
0.020 (0.51) MAX
3 PLCS
0.045 (1.14)
MIN
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
C
L
D1
D
0.026 (0.66)
0.032 (0.81)
0.050 (1.27) TP
0.042 (1.07)
0.056 (1.42)
EE1
VIEW “A” TYP.
-C-
C
L
A
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.004 (0.10) C
0.025 (0.64)
0.045 (1.14)
D2/E2
D2/E2
A1
-C-
VIEW “A”
0.020 (0.51)
MIN
SEATING
PLANE
N28.45 (JEDEC MS-018AB ISSUE A)
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
R
SYMBOL
A 0.165 0.180 4.20 4.57 -
A1 0.090 0.120 2.29 3.04 -
D 0.485 0.495 12.32 12.57 D1 0.450 0.456 11.43 11.58 3
D2 0.191 0.219 4.86 5.56 4, 5
E 0.485 0.495 12.32 12.57 -
E1 0.450 0.456 11.43 11.58 3
E2 0.191 0.219 4.86 5.56 4, 5
N28 286
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
Rev. 2 11/97
21
Dual-In-Line Plastic Packages (PDIP)
www.BDTIC.com/Intersil
HC5523
N
D1
-C-
E1
-B-
A1
A2
E
A
L
e
C
C
L
e
A
C
e
B
INDEX
AREA
BASE
PLANE
SEATING
PLANE
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendicular to datum .
7. e
e
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
12 3 N/2
-A-
D1
B1
B
e
A
and eC are measured at the lead tips with the leads unconstrained.
B
must be zero or greater.
C
D
e
0.010 (0.25) C AM BS
-C-
E22.4 (JEDEC MS-010-AA ISSUE C)
22 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -
B 0.014 0.022 0.356 0.558 B1 0.045 0.065 1.15 1.65 8
C 0.009 0.015 0.229 0.381 -
D 1.065 1.120 27.06 28.44 5
D1 0.005 - 0.13 - 5
E 0.390 0.425 9.91 10.79 6
E1 0.330 0.390 8.39 9.90 5
e 0.100 BSC 2.54 BSC -
e
A
e
B
L 0.115 0.160 2.93 4.06 4
N22 229
0.400 BSC 10.16 BSC 6
- 0.500 - 12.70 7
NOTESMIN MAX MIN MAX
Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is ca utioned to verify that data she ets are current before pl acing orders. Information fur nished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or othe rwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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