Datasheet HC55185 Datasheet (intersil)

®

www.BDTIC.com/Intersil

HC55185

Data Sheet December 18, 2006

VoIP Ringing SLIC Family

The RSLIC-VoIP family of
ringing subscriber line
interface circuits (RSLIC)
supports analog Plain Old

T elephone Service (POTS) in
short and medium loop length, wireless and wireline
applications. Ideally suited for remote subscriber units, this
family of products offers flexibility to designers with high
ringing voltage and low power consumption system
requirements.

The RSLIC-VoIP family operates to 100V which translates
directly to the amount of ringing voltage supplied to the end
subscriber. With the high operating voltage, subscriber loop
lengths can be extended to 500Ω (i.e., 5,000 feet) and
beyond.

Other key features across the product family include: low
power consumption, ringing using sinusoidal or trapezoidal
waveforms, robust auto-detection mechanisms for when
subscribers go on or off hook, and minimal external discrete
application components. Integrated test access features are
also offered on selected products to support loopback
testing as well as line measurement tests.

There are five product offerings of the HC55185 with each
version providing voltage grades of high battery voltage and
longitudinal balance. The voltage feed amplifier design uses
low fixed loop gains to achieve high analog performance
with low susceptibility to system induced noise.

Block Diagram

POL CDC VBHVBL

ILIM

DC

CONTROL

BATTERY

SWITCH

RINGING

PORT

VRS

FN4831.14

Features

• Onboard Ringing Generation

• Compatible with Existing HC5518x Devices

• Low Standby Power Consumption (75V, 65mW)

• Reduced Idle Channel Noise

• Programmable Transient Current Limit

• Improved Off Hook Software Interface

• Integrated MTU DC Characteristics

• Low External Component Count

• Silent Polarity Reversal

• Pulse Metering and On Hook Transmission

• Tip Open Ground Start Operation

• Balanced and Unbalanced Ringing

• Thermal Shutdown with Alarm Indicator

• 28 Lead Surface Mount Packaging

• Reduced Footprint Micro Leadframe Packaging

• Dielectric Isolated (DI) High Voltage Design

• QFN Package Option

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline

- Near Chip Scale Package Footprint; Improves PCB
efficiency and has a thinner profile

• Pb-free plus anneal available (RoHS compliant)

Applications

• Voice Over Internet Protocol (VoIP)

• Cable Modems

• Voice Over D S L (VoDSL)

• Short Loop Access Platforms

TIP

RING

TL

2-WIRE

PORT

TRANSIENT

CURRENT

LIMIT

TRANSMIT

SENSING

4-WIRE

PORT

VRX
VTX

-IN
VFB

• Remote Subscriber Units

• Terminal Adapters

Related Literature

• AN9814, User’s Guide for Development Board

SW+

SW-

TEST

ACCESS

DETECTOR

LOGIC

RTD DET

RD E0

ALM

CONTROL

LOGIC

BSEL SWC

F2
F1
F0

• AN9824, Modeling of the AC Loop

• Interfacing to DSP CODECs (Contact Factory)

• TB379 Thermal Characterization of Packages for ICs

• AN9922, Thermal Characterization and Modeling of the
RSLIC18 in the Micro Leadframe Package

1

Copyright Intersil Americas Inc. 2001-2006. All Rights Reserved. RSLIC18™ is a trademark of Intersil Americas Inc.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

HC55185

www.BDTIC.com/Intersil

Ordering Information

HIGH BATTERY (VBH)

PART NUMBER PART MARKING

HC55185AIM* HC55185 AIM
HC55185AIMZ* (Note) HC55185 AIMZ
HC55185BIM* HC55185 BIM
HC55185BIMZ* (Note) HC55185 BIMZ
HC55185CIM* HC55185 CIM
HC55185CIMZ* (Note) HC55185 CIMZ
HC55185DIM* HC55185 DIM
HC55185DIMZ* (Note) HC55185 DIMZ
HC55185ECM* HC55185 ECM
HC55185ECMZ* (Note) HC55185 ECMZ
HC55185ECR* HC55185 ECR
HC55185ECRZ* (Note) HC55185 ECRZ
HC55185FCM* HC55185 FCM
HC55185FCMZ* (Note) HC55185 FCMZ
HC55185FCR* HC55185 FCR
HC55185FCRZ* (Note) HC55185 FCRZ
HC55185GIM HC55185 GIM
HC55185GIMZ (Note) HC55185 GIMZ
HC55185GCM HC55185 GCM
HC55185GCMZ (Note) HC55185 GCMZ
HC55185GCR* HC55185 GCR
HC55185GCRZ* (Note) HC55185 GCRZ
HC5518XEVAL1 Evaluation board platform, including CODEC.

*Add "96" suffix for tape and reel
**Reference “Special Considerations for the QFN Package” text.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

•••

•••

•• •

•• •

•••

•••

•••

•••

••

••

•••

•••

•••

•••

LONGITUDINAL

BALANCE

••

••

••

••

•••

•••

•••

•••

FULL
TEST

TEMP.

RANGE (°C) PACKAGE

-40 to +85 28 Ld PLCC N28.45

-40 to +85 28 Ld PLCC (Pb-free) N28.45

-40 to +85 28 Ld PLCC N28.45

-40 to +85 28 Ld PLCC (Pb-free) N28.45

-40 to +85 28 Ld PLCC N28.45

-40 to +85 28 Ld PLCC (Pb-free) N28.45

-40 to +85 28 Ld PLCC N28.45

-40 to +85 28 Ld PLCC (Pb-free) N28.45
0 to +75 28 Ld PLCC N28.45
0 to +75 28 Ld PLCC (Pb-free) N28.45
0 to +75 32 Ld QFN L32.7x7**
0 to +75 32 Ld QFN (Pb-free) L32.7x7**
0 to +85 28 Ld PLCC N28.45
0 to +85 28 Ld PLCC (Pb-free) N28.45
0 to +85 32 Ld QFN L32.7x7**
0 to +85 32 Ld QFN (Pb-free) L32.7x7**

-40 to +85 28 Ld PLCC N28.45

-40 to +85 28 Ld PLCC (Pb-free) N28.45
0 to +85 28 Ld PLCC N28.45
0 to +85 28 Ld PLCC (Pb-free) N28.45
0 to +85 32 Ld QFN L32.7x7**
0 to +85 32 Ld QFN (Pb-free) L32.7x7**

PKG.

DWG. #100V 85V 75V 58dB 53dB

Device Operating Modes

MODE F2 F1 F0 E0 = 1 E0 = 0 HC55185A HC55185B HC55185C HC55185D HC55185E HC55185F HC55185G

Low Power Standby 0 0 0 SHD GKD
Forward Active 0 0 1 SHD GKD
Unbalanced Ringing 0 1 0 RTD RTD
Reverse Active 0 1 1 SHD GKD
Ringing 1 0 0 RTD RTD
Forward Loop Back 1 0 1 SHD GKD
Tip Open 1 1 0 SHD GKD
Power Denial 1 1 1 n/a n/a

•••••••

•••••••

•••••••

•••••••

•••• ••

•••• ••

•••••••

2

•

FN4831.14

December 18, 2006

Pinouts

www.BDTIC.com/Intersil

SW+

SW-

SWC

F2

F1

F0

E0

HC55185

(28 LD PLCC)

TOP VIEW

BL

BH

V

V

5

6

7

8

9

10

11

12 13 14 15 16 17 18

DET

ALM

BGND

AGND

TIP

1234

BSEL

RING

TL

RD

POL

HC55185

HC55185

(32 LD QFN)

TOP VIEW

ILIM

262728

SW+

SW-

SWC

F2

F1

F0

E0

NC

VRS

RTD

25

24

CDC

23

V

CC

22

-IN

VFB

21

VTX

20

19

VRX

VBHVBLBGND

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

9 10111213141516

DET

TIPNCRINGNCRD

ALM

BSEL

AGND

TL

POL

VRS

NC

ILIM

24

RTD

23

CDC

22

V

21

CC

-IN

20

VFB

19

VTX

18

VRX

17

3

FN4831.14

December 18, 2006

HC55185

www.BDTIC.com/Intersil

Absolute Maximum Ratings T

Maximum Supply Voltages

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

CC

- VBH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V

V

CC

Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . . -110V

Maximum Tip/Ring Negative Voltage Pulse (Note 8) . . . . . . VBH -15V

Maximum Tip/Ring Positive Voltage Pulse (Note 8) . . . . . . . . . . . .+8V

ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V

= +25°C Thermal Information

A

Thermal Resistance (Typical) θ

PLCC (Note 1) . . . . . . . . . . . . . . . . . . . 53 N/A

QFN (Note 2) . . . . . . . . . . . . . . . . . . . . 27 1

Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(PLCC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389

(°C/W) θJC (°C/W)

JA

Operating Conditions

Temperature Range

Commercial (C suffix) . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C

Industrial (I suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Positive Power Supply (V
Low Battery Power Supply (V
High Battery Power Supply (V

AIM, CIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

BIM, DIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

EIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Uncommitted Switch (loop back or relay driver) . . . . . +5V to -100V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

for the PLCC package is measured with the component mounted on a low effective thermal conductivity test board in free air. See T ech Brief

1. θ

JA

TB379 for details.

for the QFN package is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach

2. θ

JA

features including conductive thermal vias. θ
See Tech Brief 379 and AN9922 for additional information and board layout considerations.

). . . . . . . . . . . . . . . . . . . . . . . +5V, ±5%

CC

). . . . . . . . . . . . . -16V to -52V, ±5%

BL

)

BH

to 100V, ±5%

BL

to -85V, ±10%

BL

to -75V, ±10%

BL

, the “case temp” is measured at the center of the exposed metal pad on the package underside.

JC

Die Characteristics

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI

BH

Electrical Specifications Unless Otherwise Specified, T

(C) grade, V
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to

3.4kHz. Protection resistors = 0Ω.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

RINGING PARAMETERS

VRS Input Impedance (Note 3) 450 - - kΩ
Differential Ringing Gain (Note 4) Balanced Ringing, VRS to 2-Wire, R

Centering Voltage Accuracy Tip, Referenced to V

Open Circuit Ringing Voltage Balanced Ringing, VRS Input = 0.840V

Ringing Voltage Total Distortion RL = 1.3 kΩ, V
4-Wire to 2-Wire Ringing Off Isolation Active Mode, Referenced to VRS Input - 90 - dB
2-Wire to 4-Wire Transmit Isolation Ringing Mode Referenced to the Differential

AC TRANSMISSION PARAMETERS

Receive Input Impedance (Note 3) 160 - - kΩ
Transmit Output Impedance (Note 3) --1Ω
4-Wire Port Overload Level (Note 3) THD = 1% 3.1 3.5 - V
2-Wire Port Overload Level (Note 3) THD = 1% 3.1 3.5 - V
2-Wire Return Loss 300Hz - 24 - dB

= -24V , VBH= -100V , -85V or -75V, VCC = +5V , AGND = BGND = 0V, loop current limit = 25mA.

BL

Unbalanced Ringing, VRS to 2-Wire, R

Ring, Referenced to V

Unbalanced Ringing, VRS Input = 0.840V

Ringing Amplitude

1kHz - 40 - dB

3.4kHz - 21 - dB

= -40°C to +85°C for industrial (I) grade and TA = 0°C to +85°C for commercial

A

= ∞ 78 80 82 V/V

LOAD

= ∞ 40 V/V

LOAD

/2 + 0.5 (Note 9) - ± 2.5 - V

BH

/2 + 0.5 - ± 2.5 - V

BH

RMS

RMS

= |VBH| -5 - - 4.0 %

T-R

-67-V

33.5 V

-80- dB

PEAK
PEAK

RMS
RMS

4

FN4831.14

December 18, 2006

HC55185

www.BDTIC.com/Intersil

Electrical Specifications Unless Otherwise Specified, T

(C) grade, V
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to

3.4kHz. Protection resistors = 0Ω. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

2-Wire Longitudinal Balance (Notes 5, 6) Forward Active, Grade A and B 58 62 - dB

4-Wire Longitudinal Balance (Notes 5, 6) Forward Active, Grade A and B 58 67 - dB

2-Wire to 4-Wire Level Linearity
4-Wire to 2-Wire Level Linearity
Referenced to -10dBm

Longitudinal Current Capability Per Wire (Note 3) Test for False Detect 20 - - mA

4-Wire to 2-Wire Insertion Loss -0.20 0.00 +0.20 dB
2-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB
4-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB
Forward Active Idle Channel Noise (Note 6) 2-Wire C-Message, T = +25°C - 10 13 dBrnC

Reverse Active Idle Channel Noise (Note 6) 2-Wire C-Message, T = +25°C - 11 14 dBrnC

DC PARAMETERS

Off Hook Loop Current Limit Programming Accuracy -8.5 - +8.5 %

Off Hook Transient Current Limit Programming Accuracy -10 - +10 %

Loop Current During Low Power Standby Forward Polarity Only 18 - 26 mA
Open Circuit Voltage (|Tip - Ring|) V

Low Power Standby, Open Circuit Voltage
(Tip - Ring)

Absolute Open Circuit Voltage V

TEST ACCESS FUNCTIONS

Switch On Voltage I
Loopback Max Battery --52V

LOOP DETECTORS AND SUPERVISORY FUNCTIONS

Switch Hook Programming Range 5-15mA
Switch Hook Programming Accuracy Assumes 1% External Programming Resistor -10 - +10 %
Dial Pulse Distortion -1.0- %
Ring Trip Comparator Threshold 2.3 2.5 2.9 V
Ring Trip Programming Current Accuracy -10 - +10 %
Ground Key Threshold -12- mA
E0 Transition, DET Output Delay -20- μs
Thermal Alarm Output IC Junction Temperature - 175 - °C

LOGIC INPUTS (F0, F1, F2, E0, SWC, BSEL)

Input Low Voltage --0.8V
Input High Voltage 2.0 - - V
Input Low Current V

= -24V , VBH= -100V , -85V or -75V, VCC = +5V , AGND = BGND = 0V, loop current limit = 25mA.

BL

Forward Active, Grade C, D and E 53 59 - dB

Forward Active, Grade C, D and E 53 64 - dB
+3 to -40dBm, 1kHz - ±0.025 - dB

-40 to -50dBm, 1kHz - ±0.050 - dB

-50 to -55dBm, 1kHz - ±0.100 - dB

Test for False Detect, Low Power Standby 10 - - mA

4-Wire C-Message, T = +25°C - 4 7 dBrnC

4-Wire C-Message, T = +25°C - 5 8 dBrnC

Programming Range 15 - 45 mA

Programming Range 40 - 100 mA

VBL = -24V 14 15.5 17 V
VBH > -60V 43 49 - V
VBL = -48V - 44.5 - V
VBH > -60V 43 51.5 - V

= -40°C to +85°C for industrial (I) grade and TA = 0°C to +85°C for commercial

A

1

= -16V - 8.0 - V

BL

in LPS and FA; V

RG

= 45mA - 0.30 0.60 V

OL

= 0.4V -20 -10 - μA

IL

in RA; VBH > -60V - -53 -56 V

TG

RMS
RMS

DC
DC
DC
DC
DC
DC

5

FN4831.14

December 18, 2006

HC55185

www.BDTIC.com/Intersil

Electrical Specifications Unless Otherwise Specified, T

(C) grade, V
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to

3.4kHz. Protection resistors = 0Ω. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Input High Current VIH = 2.4V - - 1 μA

LOGIC OUTPUTS (DET

Output Low Voltage I
Output High Voltage I

SUPPLY CURRENTS

Low Power Standby, BSEL = 1 I

Forward or Reverse Active, BSEL = 0 I

Forward Active, BSEL = 1 I

Ringing, BSEL = 1 (Balanced Ringing, 100) I

Ringing, BSEL = 1 (Unbalanced Ringing, 010) I

Forward Loopback, BSEL = 0 I

Tip Open, BSEL = 0 I

Power Denial, BSEL = 0 or 1 I

ON HOOK POWER DISSIPATION (Note 7)
Forward or Reverse V
Low Power Standby V

Ringing V

OFF HOOK POWER DISSIPATION (Note 7)
Forward or Reverse V

POWER SUPPLY REJECTION RATIO

V

to 2-Wire f = 300Hz - 40 - dB

CC

V

to 4-Wire f = 300Hz - 45 - dB

CC

V

to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 30 - dB

BL

to 4-Wire 300Hz ≤ f ≤ 3.4kHz - 35 - dB

V

BL

V

to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 33 - dB

BH

, ALM)

= -24V , VBH= -100V , -85V or -75V, VCC = +5V , AGND = BGND = 0V, loop current limit = 25mA.

BL

I

I

I
I

I
I

I
I

I

I

I

V
V

V
V

f = 1kHz - 35 - dB
f = 3.4kHz - 28 - dB

f = 1kHz - 43 - dB
f = 3.4kHz - 33 - dB

= -40°C to +85°C for industrial (I) grade and TA = 0°C to +85°C for commercial

A

= 5mA - 0.15 0.4 V

OL

= 100μA2.43.5-V

OH

CC
BH
CC
BL
CC
BL
BH
CC
BL
BH
CC
BL
BH
CC
BL
CC
BL
CC
BL

= -24V - 55 - mW

BL

= -100V - 85 - mW

BH

= -85V - 75 - mW

BH

= -75V - 65 - mW

BH

= -100V - 250 - mW

BH

= -85V - 230 - mW

BH

= -75V - 225 - mW

BH

= -24V - 305 - mW

BL

-3.96.0mA

- 0.66 0.90 mA

-4.96.5mA

-1.22.5mA

-7.09.5mA

-0.92.0mA

-2.23.0mA

-6.49.0mA

-0.31.0mA

-2.03.0mA

-9.3 mA

-0.3 mA

-2.4 mA

- 10.3 13.5 mA

- 23.5 32 mA

-3.85.5mA

-0.31.0mA

-4.06.0mA

- 0.22 0.5 mA

6

FN4831.14

December 18, 2006

HC55185

www.BDTIC.com/Intersil

Electrical Specifications Unless Otherwise Specified, T

(C) grade, V
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to

3.4kHz. Protection resistors = 0Ω. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VBH to 4-Wire 300Hz ≤ f ≤ 1kHz - 40 - dB

NOTES:

3. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial
design release and upon design changes which would affect these characteristics.

4. Differential Ringing Gain is measured with VRS = 0.795V
for -75V devices.

5. Longitudinal Balance is tested per IEEE455-1985, with 368Ω per Tip and Ring terminal.

6. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical
characterization and design.

7. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current
limits.

8. Characterized with 2 x 10μs, and 10 x 1000μs first level lightning surge waveforms (GR-1089-CORE)

9. For Unbalanced Ringing the Tip terminal is offset to 0V and the Ring terminal is centered at Vbh/2 + 0.5V.

= -24V , VBH= -100V , -85V or -75V, VCC = +5V , AGND = BGND = 0V, loop current limit = 25mA.

BL

1kHz < f ≤ 3.4kHz - 45 - dB

Special Considerations for the QFN
Package

The new QFN package offers a significant footprint reduction
(65%) and improved thermal performance with respect to the
28 lead PLCC. To realize the thermal enhancements and
maintain the high voltage (-100V) performance, the exposed
leadframe should be soldered to a power/heat sink plane
that is electrically connected to the high battery supply (V
within the application board. This approach distributes the
heat evenly across the board and is accomplished by using
conductive thermal vias. Reference technical brief TB379
and AN9922 for additional information on thermal
characterization and board layout considerations.

Product Family Cross Reference

The following table provides an ordering and functional cross
reference for the existing HC55180 through HC55184
products and the new and improved HC55185 product.

TABLE 1. PRODUCT CROSS REFERENCE

EXISTING DEVICES FUNCTIONAL EQUIVALENT

HC55180CIM, HC55180DIM None Offered
HC55181AIM, HC55182AIM HC55185AIM
HC55181BIM, HC55182BIM HC55185BIM
HC55181CIM, HC55182CIM HC55185CIM
HC55181DIM, HC55182DIM HC55185DIM
HC55183ECM, HC55184ECM HC55185ECM

= -40°C to +85°C for industrial (I) grade and TA = 0°C to +85°C for commercial

A

for -100V devices, VRS = 0.663 V

RMS

for -85V devices and VRS = 0.575V

RMS

Application Circuit Modifications

The HC55185 basic application circuit is nearly identical to
that of the HC55180 through HC55184. The HC55185
requires an additional resistor to program the transient
current limit feature. This pro gramming resistor is connected
from pin 16 (TL) to ground. In addition some component
values have been changed to improve overall device

BH

)

performance. The table below lists the component value
changes required for the HC55185 application circuit.

TABLE 2. COMPONENT VALUE CHANGES

REFERENCE HC55180 - 184 HC55185

RS 210kΩ 66.5kΩ
RP1 ≥ 35Ω≥ 49Ω
RP2 ≥ 35Ω≥ 49Ω
CFB 0.47μ 4.7μ

The value of RS is based on a 600Ω termination impedance
and RP1 = RP2 = 49.9Ω. Design equations are provided to
calculate RS for other combinations of termination and
protection resistance.

The CFB capacitor must be non-polarized for proper device
operation in Reverse Active. Ceramic surface mount
capacitors (1206 body style) are available from Panasonic
with a 6.3V voltage rating. These can be used for CFB since
it is internally limited to approximately ±3V. The CDC
capacitor may be either polarized or non polarized.

Parametric Improvements

RMS

The most significant parametric improvement of the

Any of the HC55185 products may be used without the
battery switch function by shorting the supply pins VBL and
VBH together. This provides compatibility with HC55180
type applications which do not require the battery switch.

HC55185 is reduction in Idle Channel Noise. This
improvement was accomplished by redistributing gains in
the impedance matching loop. The impact to the application
circuit is the change in the impedance programming resistor
RS. The redistribution of gains also improves AC
performance at the upper end of the voice band.

7

FN4831.14

December 18, 2006

HC55185

www.BDTIC.com/Intersil

Functional Improvements

In addition to parametric improvements, internal circuit
changes and application circuit changes have been made to
improve the overall device functionality.

Off Hook Interface

The transient behavior of the device in response to mode
changes has been significantly improved. The benefit to the
application is reduction or more likely elimination of DET
glitches when off hook events occur. In addition to internal
circuit modifications, the change of CFB value contributes to
this functional improvement.

Transient Current Limit

The drive current capability of the output amplifiers is
determined by an externally programmable output current
limit circuit which is separate from the DC loop current limit
function and programmed at the pin TL. The current limit
circuit works in both the source and sink direction, with an
internally fixed offset to prevent the current limit functions
from turning on simultaneously. The current limit function is
provided by sensing line current and reducing the voltage
drive to the load when the externally set threshold is
exceeded, hence forcing a constant source or sink current.

SOURCE CURRENT PROGRAMMING

The source current is externally programmed as shown in
Equation 1.

1780

-------------

R

=

TL

I

SRC

For example a source current limit setting of 50mA is
programmed with a 35.6kΩ resistor connected from pin 16 of
the device to ground. This setting determines the maximum
amount of current which flows from Tip to Ring during an off
hook event until the DC loop current limit responds. In addition
this setting also determines the amount of current which will
flow from Tip or Ring when external battery faults occur.

SINK CURRENT PROGRAMMING

The sink current limit is internally offset 20% higher than the
externally programmed source current limit setting.

I

1.20 I

SNK

If the source current limit is set to 50mA, the sink current limit
will be 60mA. This setting will determine the maximum current
that flows into Tip or Ring when external ground faults occur.

FUNCTIONAL DESCRIPTION

Each amplifier is designed to limit source current and sink
current. The diagram below shows the functionality of the
circuit for the case of limiting the source current. A similar

×=

SRC

(EQ. 1)

(EQ. 2)

diagram applies to the sink current limit with current polarity
changed accordingly.

IO/K

I

= 1.21/TL

REF

I

SIG

FIGURE 1. CURRENT LIMIT FUNCTIONAL DIAGRAM

During normal operation, the error current (I
the output voltage is determined by the signal current (I

VB/2

I

ERR

-

+

200k

20

TIP or RING

) is zero and

ERR

I

O

SIG

multiplied by the 200k feedback resistor. With the current
polarity as shown for I

, the output voltage moves positive

SIG

with respect to half battery. Assuming the amplifier output is
driving a load at a more negative potential, the amplifier
output will source current.

During excessive output source current flow, the scaled
output current (I
forcing an error current (I

/K) exceeds the reference current (I

O

). With the polarity as shown

ERR

REF

)

the error current subtracts from the signal current, which
reduces the amplifier output voltage. By reducing the output
voltage the source current to the load is decreased and the
output current is limited.

DETERMINING THE PROPER SETTING

Since this feature programs the maximum output current of
the device, the setting must be high enough to allow for
detection of ring trip or programmed off hook loop current,
whichever is greater.

To allow for proper ring trip operation, the transient current
limit setting should be set at least 25% higher than the peak
ring trip current setting. Setting the transient current 25%
higher should account for programming tolerances of both
the ring trip threshold and the transient current limit.

If loop current is larger than ring trip current (low REN applica­tions) then the transient current limit should be set at least 35%
higher than the loop current setting. The slightly higher offset
accounts for the slope of the loop current limit function.

Attention to detail should be exercised when programming
the transient current limit setting. If ring trip detect does not
occur while ringing, then re-examine the transient current
limit and ring trip threshold settings.

)

8

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Design Equations

Loop Supervision Thresholds

SWITCH HOOK DETECT

The switch hook detect threshold is set by a single external
resistor, RSH. Equation 3 is used to calculate the value of RSH.

R

600 ISH⁄=

SH

The term I

is the desired DC loop current threshold. The

SH

loop current threshold programming range is from 5mA to
15mA.

GROUND KEY DETECT

The ground key detector senses a DC current imbalance
between the Tip and Ring terminals when the ring terminal is
connected to ground. The ground key detect threshold is not
externally programmable and is internally fixed to 12mA
regardless of the switch hook threshold.

RING TRIP DETECT

The ring trip detect threshold is set by a single external
resistor, R

. IRT should be set between the peak ringing

RT

current and the peak off hook current while still ringing.

1800 IRT⁄=

R

RT

In addition, the ring trip current must be set below the
transient current limit, including tolerances. The capacitor
C

, in parallel with RRT, will set the ring trip response time.

RT

Loop Current Limit

The loop current limit of the device is programmed by the
external resistor R

. The value of RIL can be calculated

IL

using Equation 5:

1760

------------ -

R

=

IL

I

LIM

The term I

is the desired loop current limit. The loop

LIM

current limit programming range is from 15mA to 45mA.

Impedance Matching

The impedance of the device is programmed with the
external component R
the feedback amplifier that provides impedance matching. If
complex impedance matching is required, then a complex
network can be substituted for R

RESISTIVE IMPEDANCE SYNTHESIS

The source impedance of the device, Z
in Equation 6.

133.3 ZO()=

R

S

The required impedance is defined by the terminating
impedance and protection resistors as shown in Equation 7.

Z

OZL2RP

–=

. RS is the gain setting resistor for

S

.

S

, can be calculated

O

(EQ. 3)

(EQ. 4)

(EQ. 5)

(EQ. 6)

(EQ. 7)

4-WIRE TO 2-WIRE GAIN

The 4-wire to 2-wire gain is defined as the receive gain. It is
a function of the terminating impedance, synthesized
impedance and protection resistors. Equation 8 calculates
the receive gain, G

⎛⎞

G

42

------------------------------------------

2

–=

⎜⎟

ZO + 2RP + Z

⎝⎠

.

42

Z

L

L

(EQ. 8)

When the device source impedance and protection resistors
equals the terminating impedance, the receive gain equals
unity.

2-WIRE TO 4-WIRE GAIN

The 2-wire to 4-wire gain (G

) is the gain from tip and ring to

24

the VTX output. The transmit gain is calculated in Equation 9.

Z

G

⎜⎟

24

⎝⎠

⎛⎞

–=

O

------------------------------------------

ZO + 2RP + Z

L

(EQ. 9)

When the protection resistors are set to zero, the transmit
gain is -6dB.

TRANSHYBRID GAIN

The transhybrid gain is defined as the 4-wire to 4-wire gain
(G

).

44

G

44

Z

⎛⎞

–=

⎜⎟
⎝⎠

O

---------------------------------------

ZO2RPZ

++

L

(EQ. 10)

When the protection resistors are set to zero, the transhybrid
gain is -6dB.

COMPLEX IMPEDANCE SYNTHESIS

Substituting the impedance programming resistor, RS, with a
complex programming network provides complex
impedance synthesis.

2-WIRE

NETWORK

C

2

R

1

R

2

FIGURE 2. COMPLEX PROGRAMMING NETWORK

PROGRAMMING

NETWORK

C

R

Series

R

Parallel

Parallel

The reference designators in the programming network
match the evaluation board. The component R
different design equation than the R

used for resistive

S

has a

S

impedance synthesis. The design equations for each
component are provided below.

R

Series

R

Parallel

C

ParallelC2

133.3 R12RP()–()×=

133.3 R2×=

·

133.3⁄

=

(EQ. 11)

(EQ. 12)

(EQ. 13)

9

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December 18, 2006

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Low Power Standby

Overview

The low power standby mode (LPS, 000) should be used
during idle line conditions. The device is designed to operate
from the high battery during this mode. Most of the internal
circuitry is powered down, resulting in low power dissipation.
If the 2-wire (tip/ring) DC voltage requirements are not
critical during idle line conditions, the device may be
operated from the low battery. Operation from the low battery
will decrease the standby power dissipation.

TABLE 3. DEVICE INTERFACES DURING LPS

INTERFACE ON OFF NOTES

Receive x AC transmission, impedance
Ringing x
Transmit x
2-Wire x Amplifiers disabled.
Loop Detect x Switch hook or ground key.

2-Wire Interface

During LPS, the 2-wire interface is maintained with internal
switches and voltage references. The Tip and Ring
amplifiers are turned off to conserve power. The device will
provide MTU compliance, loop current and loop supervision.
Figure 3 represents the internal circuitry providing the 2-wire
interface during low power standby.

TIP

RING

MTU REF

FIGURE 3. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM

MTU Compliance

Maintenance Termination Unit or MTU compliance places
DC voltage requirements on the 2-wire terminals during idle
line conditions. The minimum idle voltage is 42.75V. The
high side of the MTU range is 56V. The voltage is expressed
as the difference between Tip and Ring.

The Tip voltage is held near ground through a 600Ω resistor
and switch. The Ring voltage is limited to a maximum of

-56V (by MTU REF) when operating from either the high or
low battery. A switch and 600Ω resistor connect the MTU
reference to the Ring terminal. When the high battery

matching and ringing are
disabled during this mode.

GND

600Ω

TIP AMP

RING AMP

600Ω

voltage exceeds the MTU reference of -56V, the Ring
terminal will be clamped by the internal reference (typically

-54V). The same Ring relationships apply when operating
from the low battery voltage. For high battery voltages (V

BH

less than or equal to the internal MTU reference threshold:

V

RINGVBH

4+=

(EQ. 14)

Loop Current

During LPS, the device will provide current to a load. The
current path is through resistors and switches, and will be
function of the off hook loop resistance (R

LOOP

). This
includes the off hook phone resistance and copper loop
resistance. The current available during LPS is determined
by Equation 15.

I

LOOP

1– 49–()–()600 600 R

++()⁄=

LOOP

(EQ. 15)

Internal current limiting of the standby switches will limit the
maximum current to 20mA.

Another loop current related parameter is longitudinal
current capability. The longitudinal current capability is
reduced to 10mA

per pin. The reduction in longitudinal

RMS

current capability is a result of turning off the Tip and Ring
amplifiers.

On Hook Power Dissipation

The on hook power dissipation of the device during LPS is
determined by the operating voltages and quiescent currents
and is calculated using Equation 16.

P

LPSVBHIBHQ

× VBLI

× VCCI

BLQ

×++=

CCQ

(EQ. 16)

The quiescent current terms are specified in the electrical
tables for each operating mode. Load power dissipation is
not a factor since this is an on hook mode. Some
applications may specify a standby current. The standby
current may be a charging current required for modern
telephone electronics.

Standby Current Power Dissipation

Any standby line current, I
power dissipation term P
power contribution is zero when the standby line current is
zero.

P

SLCISLCVBH

49– 1I

If the battery voltage is less than -49V (the MTU clamp is
off), the standby line current power contribution reduces to
Equation 18.

P

SLCISLCVBH

1I

Most applications do not specify charging current
requirements during standby. When specified, the typical
charging current may be as high as 5mA.

, introduces an additional

SLC

. Equation 17 illustrates the

SLC

x1200++()×=

SLC

x1200++()×=

SLC

(EQ. 17)

(EQ. 18)

)

10

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December 18, 2006

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Forward Active

Overview

The forward active mode (FA, 001) is the primary AC
transmission mode of the device. On hook transmission, DC
loop feed and voice transmission are supported during forward
active. Loop supervision is provided by either the switch hook
detector (E0 = 1) or the ground key detector (E0 = 0). The
device may be operated from either high or low battery for on­hook transmission and low battery for loop feed.

On-Hook Transmission

The primary purpose of on hook transmission will be to
support caller ID and other advanced signalling features.
The transmission over load level while on hook is 3.5V

When operating from the high battery, the DC voltages at Tip
and Ring are MTU compliant. The typical Tip voltage is -4V
and the Ring voltage is a function of the battery voltage for
battery voltages less than -60V as shown in Equation 19.

V

RINGVBH

4+=

Loop supervision is provided by the switch hook detector at
the DET

output. When DET goes low, the low battery should

be selected for DC loop feed and voice transmission.

Feed Architecture

The design implements a voltage feed current sense
architecture. The device controls the voltage across Tip and
Ring based on the sensing of load current. Resistors are
placed in series with Tip and Ring outputs to provide the
current sensing. The diagram below illustrates the concept.

R

B

R

V

OUT

R

L

FIGURE 4. VOLTAGE FEED CURRENT SENSE DIAGRAM

CS

-

+

-

+

K

S

By monitoring the current at the amplifier output, a negative
feedback mechanism sets the output voltage for a defined
load. The amplifier gains are set by resistor ratios (R
R

) providing all the performance benefits of matched

C

resistors. The internal sense resistor, R
than the gain resistors and is typically 20Ω for this device.
The feedback mechanism, K

, represents the amplifier

S

configuration providing the negative feedback.

R

A

, is much smaller

CS

PEAK

(EQ. 19)

V

IN

R

C

, RB,

A

filter is set by the external capacitor C

. The value of the

DC

external capacitor should be 4.7μF.
Most applications will operate the device from low battery

while off hook. The DC feed characteristic of the device will
drive Tip and Ring towards half battery to regulate the DC
loop current. For light loads, Tip will be near -4V and Ring
will be near V

+ 4V . The following diagram shows the DC

VBL

feed characteristic.

V

TR(OC)

, DC (V)

TR

.

V

I

(mA)

LOOP

FIGURE 5. DC FEED CHARACTERISTIC

The point on the y-axis labeled V

m = (ΔVTR/ΔIL) = 11.1kΩ

I

LIM

is the open circuit

TR(OC)

Tip to Ring voltage and is defined by the feed battery
voltage.

V

TR OC()VBL

8–=

(EQ. 20)

The curve of Figure 5 determines the actual loop current for
a given set of loop conditions. The loop conditions are
determined by the low battery voltage and the DC loop
impedance. The DC loop impedance is the sum of the
protection resistance, copper resistance (Ω/foot) and the
telephone off hook DC resistance.

I

(mA)

I

FIGURE 6. I

SC

LOOP

I

LIM

LOOP

2R

P

vs R

R

LOOP

LOOP

I

A

I

B

R

(Ω)

LOAD CHARACTERISTIC

KNEE

The slope of the feed characteristic and the battery voltage
define the maximum loop current on the shortest possible
loop as the short circuit current I

I

SCILIM

The term I

+=

LIM

line segment I

V

------------------------------------------------------

is the programmed current limit, 1760/RIL. The

–

TR OC()2RPILIM

1.1e4

represents the constant current region of the

A

SC

.

(EQ. 21)

loop current limit function.

I

AILIM

V

--------------------------------------------------------------

+=

–

TR OC()RLOOPILIM

1.1e4

(EQ. 22)

DC Loop Feed

The feedback mechanism for monitoring the DC portion of
the loop current is the loop detector. A low pass filter is used
in the feedback to block voice band signals from interfering
with the loop current limit function. The pole of the low pass

The maximum loop impedance for a programmed loop
current is defined as R

V

TR OC()

------------------------

KNEE

=

I

LIM

R

11

KNEE

.

(EQ. 23)

FN4831.14

December 18, 2006

HC55185

www.BDTIC.com/Intersil

When R

is exceeded, the device will transition from

KNEE

constant current feed to constant voltage, resistive feed. The
line segment I

represents the resistive feed portion of the

B

load characteristic.

V

I

B

TR OC()

------------------------

=

R

LOOP

(EQ. 24)

Voice Transmission

The feedback mechanism for monitoring the AC portion of
the loop current consists of two amplifiers, the sense
amplifier (SA) and the transmit amplifier (TA). The AC
feedback signal is used for impedance synthesis. A detailed
model of the AC feed back loop is provided below.

RR

VRX

TIP

RING

20

20

-

+

+

-

R

4R
4R
4R
4R 3R

1:1

R

T

A

+

-

3R

-

+

8K

V

SA

VTX

R

S

-IN
C

FB

VFB

of the signal injected at V

. The echo must be cancelled to

RX

maintain voice quality. Most applications will use a summing
amplifier in the CODEC front end as shown below to cancel
the echo signal.

R

VRX

R

1:1

VTX

T

A

+

-

HC5518x

FIGURE 8. TRANSHYBRID BALANCE INTERFACE

The resistor ratio, R
the transmit gain, G

R

S

-IN

, provides the final adjustment for

F/RB

. The transmit gain is calculated using

TX

R

A

R

F

R

B

­+

+2.4V

RX OUT

TX IN

CODEC

Equation 27.

R

⎛⎞

F

G–

------- -

⎜⎟

24

R

⎝⎠

B

= RB, hence the device 2-wire to

F

=

G

TX

Most applications set R
4-wire equals the transmit gain. Typically R

B

(EQ. 27)

is greater than

20kΩ to prevent loading of the device transmit output.

FIGURE 7. AC SIGNAL TRANSMISSION MODEL

The gain of the transmit amplifier, set by R
programmed impedance of the device. The capacitor C

, determines the

S

FB

blocks the DC component of the loop current. The ground
symbols in the model represent AC grounds, not actual DC
potentials.

The sense amp output voltage, V

, as a function of Tip and

SA

Ring voltage and load is calculated using Equation 25.

30

V

SA

VTVR–()–

=

------

Z

L

(EQ. 25)

The transmit amplifier provides the programmable gain
required for impedance synthesis. In addition, the output of
this amplifier interfaces to the CODEC transmit input. The
output voltage is calculated using Equation 26.

V

VTX

–=

V

⎛⎞

----------

SA

⎝⎠

8e3

(EQ. 26)

R

S

Once the impedance matching components have been
selected using the design equations, the above equations
provide additional insight as to the expected AC node
voltages for a specific Tip and Ring load.

Transhybrid Balance

The final step in completing the impedance synthesis design
is calculating the necessary gains for transhybrid balance.
The AC feed back loop produces an echo at the V

output

TX

The resistor ratio, R
gain of the device, G
transmit gain requirement and R

, is determined by the transhybrid

F/RA

. RF is previously defined by the

44

is calculated using

A

Equation 28.

R

B

----------

=

R

A

G

44

(EQ. 28)

Power Dissipation

The power dissipated by the device during on hook
transmission is strictly a function of the quiescent currents
for each supply voltage during Forward Active operation.

I×

VBLI

P

FAQVBH

BHQ

× VCCI

BLQ

Off hook power dissipation is increased above the quiescent
power dissipation by the DC load. If the loop length is less
than or equal to R
current, I

, and the power dissipation is calculated using

A

, the device is providing constant

KNEE

Equation 30.

P

FA IA()PFA Q()VBLxIA

()R

()–+=

If the loop length is greater than R
operating in the constant voltage, resistive feed region. The
power dissipated in this region is calculated using Equation 31.

P

FA IB()PFA Q()VBLxIB

()R

()–+=

LOOP

KNEE

LOOP

×++=

CCQ

2

xI

A

, the device is

2

xI

B

(EQ. 29)

(EQ. 30)

(EQ. 31)

12

FN4831.14

December 18, 2006

HC55185

www.BDTIC.com/Intersil

Since the current relationships are different for constant
current versus constant voltage, the region of device
operation is critical to valid power dissipation calculations.

Reverse Active

Overview

The reverse active mode (RA, 011) provides the same
functionality as the forward active mode. On hook
transmission, DC loop feed and voice transmission are
supported. Loop supervision is provided by either the switch
hook detector (E0 = 1) or the ground key detector (E0 = 0).
The device may be operated from either high or low battery.

During reverse active the Tip and Ring DC voltage
characteristics exchange roles. That is, Ring is typically 4V
below ground and Tip is typically 4V more positive than
battery. Otherwise, all feed and voice transmission
characteristics are identical to forward active.

Silent Polarity Reversal

Changing from forward active to reverse active or vice versa
is referred to as polarity reversal. Many applications require
slew rate control of the polarity reversal event. Requirements
range from minimizing cross talk to protocol signalling.

The device uses an external low voltage capacitor, C
set the reversal time. Once programmed, the reversal time
will remain nearly constant over various load conditions. In
addition, the reversal timing capacitor is isolated from the AC
loop, therefore loop stability is not impacted.

POL

, to

POL pin and minimal voltage excursion ±0.75V, are well
suited to polarized capacitors.

Power Dissipation

The power dissipation equations for forward active operation
also apply to the reverse active mode.

Ringing

Overview

The ringing mode (RNG,100) provides linear amplification to
support a variety of ringing waveforms. A programmable ring
trip function provides loop supervision and auto disconnect
upon ring trip. The device is designed to operate from the
high battery during this mode.

Architecture

The device provides linear amplification to the signal applied
to the ringing input, V
device is 80V/V. The circuit model for the ringing path is
shown in Figure 10.

R

TIP

RING

20

20

R

. The differential ring i n g ga in of the

RS

R/8

-

+

5:1

V

+

BH

-

+

-

2

600k

-

+

VRS

The internal circuitry used to set the polarity reversal time is
shown below.

I

1

POL

75kΩ

I

2

FIGURE 9. REVERSAL TIMING CONTROL

C

POL

During forward active, the current from source I1 charges
the external timing capacitor C

and the switch is open.

POL

The internal resistor provides a clamping function for
voltages on the POL node. During reverse active, the switch
closes and I2 (roughly twice I1) pulls current from I1 and the
timing capacitor. The current at the POL node provides the
drive to a differential pair which controls the reversal time of
the Tip and Ring DC voltages.

C

POL

=

Δtime

----------------

75000

(EQ. 32)

Where Δtime is the required reversal time. Polarized
capacitors may be used for C

. The low voltage at the

POL

FIGURE 10. LINEAR RINGING MODEL

The voltage gain from the VRS input to the Tip output is
40V/V . The resistor ratio provides a gain of 8 and the current
mirror provides a gain of 5. The voltage gain from the VRS
input to the Ring output is -40V/V. The equations for the Tip
and Ring outputs during ringing are provided below.

V

BH

-----------

V

T

V

R

2

V

BH

-----------

2

40 VRS×()+=

40 VRS×()–=

(EQ. 33)

(EQ. 34)

When the input signal at VRS is zero, the Tip and Ring
amplifier outputs are centered at half battery. The device
provides auto centering for easy implementation of
sinusoidal ringing waveforms. Both AC and DC control of the
Tip and Ring outputs is available during ringing. This feature
allows for DC offsets as part of the ringing waveform.

Ringing Input

The ringing input, VRS, is a high impedance input. The high
impedance allows the use of low value capacitors for AC
coupling the ring signal. The V
during the ringing mode, therefore a free running oscillator
may be connected to VRS at all times.

input is enabled only

RS

13

FN4831.14

December 18, 2006

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When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95V

. Hence, the

P-P

maximum signal swing at VRS to achieve full scale ringing is
approximately 2.4V

. The low signal levels are compatible

P-P

with the output voltage range of the CODEC. The digital
nature of the CODEC ideally suits it for the function of
programmable ringing generator. See Applications Section.

Logic Control

Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.

Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the
ringing current, which is then filtered with external components
R

and CRT. The resistor RRT sets the trip threshold and the

RT

capacitor C

sets the trip response time. Most applications will

RT

require a trip response time less than 150ms.
Three very distinct actions occur when the devices detects a

ring trip. First, the DET

output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.

Power Dissipation

The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to valid
power calculations is the correct definition of average and RMS
currents. The average current defines the high battery supply
current. The RMS current defines the load current.

The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, P

P

The terms t
interval is t
ratio t

The quiescent power of the device in the ringing mode is
defined in Equation 36.

P

The total power during the ringing interval is the sum of the
quiescent power and loading power:

P

, and the silent interval power, Ps.

r

t

r

--------------

RNGPr

rQ()VBHIBHQ

rPrQ()VBHIAVG

× P

trts+

and tS represent the cadence. The ringing

R

and the silent interval is tS. The typical cadence

R

is 1:2.

R:tS

× VBLI

×

t

s

--------------

×+=

s

trts+

× VCCI

------------------------------------------

–+=

Z

BLQ

2

V

RMS

+

RENRLOOP

(EQ. 35)

×++=

CCQ

(EQ. 36)

(EQ. 37)

For sinusoidal waveforms, the average current, I

AVG

, is

defined in Equation 38.

I

AVG

2

⎛⎞

-- -

------------------------------------------

=

⎝⎠

Z

π

RENRLOOP

V

RMS

2×

+

(EQ. 38)

The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.

Unbalanced Ringing

The HC55185GCM offers a new Unbalanced Ringing mode
(010). This feature has been added to accommodate some
Analog PBX Trunk Lines that require the Tip terminal to be
held near ground for the duration of the ringing bursts. The
Tip terminal is offset to 0V’s with an internal current source
that is applied to the inverting input of the Tip amplifier. This
reduces the differential ringing gain to 40V/V. The Ring
terminal will center at Vbh/2 and swing from -Vbh to ground.
As in Balanced Ringing, off hook detection is accomplished
by sensing the peak current and comparing it to a preset
threshold. This allows the same sensing, comparing and
threshold circuitry to be used in both Ringing modes. This
mode of operation does not require any additional external
components.

Forward Loop Back

Overview

The Forward Loop Back mode (FLB, 101) provides test
capability for the device. An internal signal path is enabled
allowing for both DC and AC verification. The internal 600Ω
terminating resistor has a tolerance of ±20% . The device is
intended to operate from only the low battery during this
mode.

Architecture

When the forward loop back mode is initiated internal
switches connect a 600Ω load across the outputs of the Tip
and Ring amplifiers.

TIP

TIP AMP

600Ω

RING AMP

RING

FIGURE 11. FORWARD LOOP BACK INTERNAL TERMINATION

DC Verification

When the internal signal path is provided, DC current will
flow from Tip to Ring. The DC current will force DET
indicating the presence of loop current. In addition, the ALM
output will also go low. This does not indicate a thermal
alarm condition. Rather, proper logic operation is verified in
the event of a thermal shutdown. In addition to verifying
device functionality, toggling the logic outputs verifies the
interface to the system controller.

low,

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AC Verification

The entire AC loop of the device is active during the forward
loop back mode. Therefore a 4-wire to 4-w i re level test
capability is provided. Depending on the transhybrid balance
implementation, test coverage is provided by a one or two
step process.

System architectures which cannot disable the transhybrid
function would require a two step process. The first step
would be to send a test tone to the device while on hook and
not in forward loop back mode. The return signal would be
the test level times the gain R
amplifier. Since the device would not be terminated,
cancellation would not occur. The second step would be to
program the device to FLB and resend the test tone. The
return signal would be much lower in amplitude than the first
step, indicating the device was active and the internal
termination attenuated the return signal.

System architectures which disable the transhybrid function
would achieve test coverage with a signal step. Once the
transhybrid function is disable, prog ra m th e de vi ce for FL B
and send the test tone. The return signal level is determined
by the 4-wire to 4-wire gain of the device.

of the transhybrid

F/RA

Tip Open

Overview

The tip open mode (110) is intended for compatibility for PBX
type interfaces. Used during idle line conditions, the device
does not provide transmission. Loop supervision is provided
by either the switch hook detector (E0 = 1) or the ground key
detector (E0 = 0). The ground key detector will be used in
most applications. The device may be operated from either
high or low battery.

Functionality

During tip open operation, the Tip switch is disabled and the
Ring switch is enabled. The minimum Tip impedance is
30kΩ. The only active path through the device will be the
Ring switch.

In keeping with the MTU characteristics of the device, Ring
will not exceed -56V when operating from the high battery.
Though MTU does not apply to tip open, safety requirements
are satisfied.

Power Denial

Overview

The power denial mode (111) will shutdown the entire device
except for the logic interface. Loop supervision is not
provided. This mode may be used as a sleep mode or to
shut down in the presence of a persistent thermal alarm.
Switching between high and low battery will have no effect
during power denial.

Functionality

During power denial, both the Tip and Ring amplifiers are
disabled, representing high impedances. The voltages at
both outputs are near ground.

Thermal Shutdown

In the event the safe die temperature is exceeded, the ALM
output will go low and DET
automatically shutdown. When the device cools, ALM
go high and DET
fault persists, ALM
shutdown. Programming power denial will permanently
shutdown the device and stop the self cooling cycling.

will reflect the loop status. If the thermal

will go low again and the part will

will go high and the part will

will

Battery Switching

Overview

The integrated battery switch selects between the high
battery and low battery. The battery switch is controlled
with the logic input BSEL. When BSEL is a logic high, the
high battery is selected and when a logic low, the low
battery is selected. All operating modes of the device will
operate from high or low battery except forward loop back.

Functionality

The logic control is independent of the operating mode
decode. Independent logic control provides the most
flexibility and will support all application configurations.

When changing device operating states, battery switching
should occur simultaneously with or prior to changing the
operating mode. In most cases, this will minimize overall
power dissipation and prevent glitches on the DET

The only external component required to support the battery
switch is a diode in series with the V
event that high battery is removed, the diode allows the
device to transition to low battery operation.

supply lead. In the

BH

Low Battery Operation

All off hook operating conditions should use the low battery .
The prime benefit will be reduced power dissipation. The
typical low battery for the device is -24V . How eve r this may
be increased to support longer loop lengths or high loop
current requirements. S t andby condition s may also operate
from the low battery if MTU compliance is not required,
further reducing standby power dissipation.

High Battery Operation

Other than ringing, the high battery should be used for
standby conditions which must provide MTU compliance.
During standby operation the power consumption is typically
85mW with -100V battery. If ringing requirements do not
require full 100V operation, then a lower battery will result in
lower standby power.

output.

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High Voltage Decoupling

The 100V rating of the device will require a capacitor of
higher voltage rating for decoupling. Suggested decoupling
values for all device pins are 0.1μF. Standard surface mount
ceramic capacitors are rated at 100V . For applications driven
at low cost and small size, the decoupling scheme shown
below could be implemented.

0.22μ 0.22μ

VBH VBL

HC5518X

FIGURE 12. ALTERNATE DECOUPLING SCHEME

It is important to place the external diode between the VBH
pin and the decoupling capacitor. Attaching the decoupling
capacitor directly to the VBH pin will degrade the reliability of
the device. Refer to Figure 12 for the proper arrangement.
This applies to both single and stacked and decoupling
arrangements.

If VBL and VBH are tied together to override the battery
switch function, then the external diode is not needed and
the decoupling may be attached directly to VBH.

Uncommitted Switch

Overview

The uncommitted switch is a three terminal device designed
for flexibility. The independent logic control input, SWC
allows switch operation regardless of device operating
mode. The switch is activated by a logic low. The positive
and negative terminals of the device are labeled SW+ and
SW- respectively.

Relay Driver

The uncommitted switch may be used as a relay driver by
connecting SW+ to the relay coil and SW- to ground. The
switch is designed to have a maximum on voltage of 0.6V
with a load current of 45mA.

,

+5V

RELAY

SW+

SW-

FIGURE 13. EXTERNAL RELAY SWITCHING

SWC

Test Load

The switch may be used to connect test loads across Tip
and Ring. The test loads can provide external test
termination for the device. Proper connection of the
uncommitted switch to Tip and Ring is shown in Figure 14.

TIP

RING

TEST

LOAD

SW+

SW-

FIGURE 14. TEST LOAD SWITCHING

The diode in series with the test load blocks current from
flowing through the uncommitted switch when the polarity of
the Tip and Ring terminals are reversed. In addition to the
reverse active state, the polarity of Tip and Ring are
reversed for half of the ringing cycle. With independent logic
control and the blocking diode, the uncommitted switch may
be continuously connected to the Tip and Ring terminals.

SWC

Since the device provides the ringing waveform, the relay
functions which may be supported include subscriber
disconnect, test access or line interface bypass. An external
snubber diode is not required when using the uncommitted
switch as a relay driver.

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Basic Application Circuit

C

PS1

C

PS2

C

PS3

VCC

R

P1

R

P2

C

R

R

R

V

CC

C

R

RT

RT

SH

IL

C

POL

TL

TIP

HC55185

RING
SW+
SW-

RTD

RD

ILIM

DC

CDC

POL

TL

VBL

U

VBH

VRX

1

VRS

VFB

SWC

BSEL

DET

ALM

BGNDAGND

VTX

-IN

E0
F0
F1
F2

TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT

LIST

COMPONENT VALUE TOL RATING

U1 - Ringing SLIC HC55185 N/A N/A

D

1

C

RX

C

RS

C

TX

R

S

C

FB

R

TL

R

RT

R

SH

R

IL

R

S

, CRS, CTX, CRT, C

C

RX

, C

C

DC

FB

C

PS1

, C

C

PS2

PS3

D

1

, R

R

P1

P2

Standard applications will use ≥ 49Ω per side. Protection resistor

POL

18.7kΩ 1% 0.1W

23.7kΩ 1% 0.1W

49.9kΩ 1% 0.1W

71.5kΩ 1% 0.1W

66.5kΩ 1% 0.1W

0.47μF 20% 10V

4.7μF 20% 10V

0.1μF 20% >100V

0.1μF 20% 100V

1N400X type with breakdown > 100V.

values are application dependent and will be determined by
protection requirements.

Design Parameters: Ring Trip Threshold = 76mA
Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize

PEAK

, Switch

Device Impedance = (3*66.5kΩ)/400 = 498.8Ω, with 49.9Ω
protection resistors, impedance across Tip and Ring
terminals = 599Ω. Transient current limit = 95mA.

FIGURE 15. HC55185 BASIC APPLICATION CIRCUIT

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Pin Descriptions

PLCC QFN SYMBOL DESCRIPTION

1 29 TIP TIP power amplifier output.
2 30 BGND Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.

Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
3 31 VBL Low battery supply connection.
4 32 VBH High battery supply connection for the most negative battery.
5 1 SW+ Uncommitted switch positive terminal.
6 2 SW- Uncommitted switch negative terminal.
7 3 SWC Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch

8 4 F2 Mode Control Input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of

9 5 F1 Mode control input.

10 6 F0 Mode control input.
11 7 E0 Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0) comparator

12 9 DET Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating

13 10 ALM Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature

14 11 AGND Analog ground reference. This pin should be externally connected to BGND.
15 12 BSEL Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery.
16 13 TL Programming pin for the transient current limit feature, set by an external resistor to ground.
17 14 POL External capacitor on this pin sets the polarity reversal time.
18 15 VRS Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.
19 17 VRX Analog Receive Voltage - 4-wire analog audio input voltage. AC couples to CODEC.
20 18 VTX Transmit Output Voltage - Output of impedance matching amplifier, AC couples to CODEC.
21 19 VFB Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching.
22 20 -IN Impedance matching amplifier summing node.
23 21 VCC Positive voltage power supply, usually +5V.
24 22 CDC DC Biasing Filter Capacitor - Connects between this pin and V
25 23 RTD Ring trip filter network.
26 24 ILIM Loop Current Limit programming resistor.
27 25 RD Switch hook detection threshold programming resistor.

28 27 RING RING power amplifier output.

and logic “1” disabling the switch.

operation of the device.

outputs to the DET

mode. The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table

shown on page 2).

(approximately 175°C) and the device has been powered down automatically.

output based upon the state at th e F2-F0 pins (see the Device Operating Mo des table shown on page 2).

.

CC

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Quad Flat No-Lead Plastic Package (QFN)

2X

0.15

C

A

6

INDEX

AREA

AREA

2X

2X

SEATING PLANE

(DATUM B)

(DATUM A)

6

INDEX
AREA

FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE

0.15

CC

C

4X

C

4X P

4X P

NX L

e

1
2
3

B

AC0.15

0

8

C

L

D

9

N

BOTTOM VIEW

D1

D1/2

N

TOP VIEW

SIDE VIEW

NX b

D2

D2

2

e
(Nd-1)Xe

REF.

NX b

5

L1

TERMINAL TIP

D/2

5

N

SECTION "C-C"

0.10 BAMC
7

NX k

1
2

3

L

10

A3

E2/2

A

E1/2 E/2

E1

A2

A

A1

8

E2

7

8

9
CORNER
OPTION 4X

A1

9

/ /

0.10 C

0.08

9

(Ne-1)Xe

REF.

C

L

E

B

e

0.152XB

C

L1

C

L

10

L32.7x7

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKC ISSUE C)

MILLIMETERS

SYMBOL

A0.800.901.00 -
A1 - - 0.05 ­A2 - - 1.00 9
A3 0.20 REF 9

b 0.23 0.28 0.38 5, 8

D 7.00 BSC ­D1 6.75 BSC 9
D2 4.55 4.70 4.85 7, 8

E 7.00 BSC ­E1 6.75 BSC 9
E2 4.55 4.70 4.85 7, 8

e 0.65 BSC -

k 0.25 ---

L 0.50 0.60 0.75 8

L1 - - 0.15 10

N322
Nd 8 3
Ne 8 3

P--0.60 9

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present
when Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

NOTESMIN TYP MAX

Rev. 4 8/03

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Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)

0.048 (1.22)
PIN (1) IDENTIFIER

0.020 (0.51) MAX
3 PLCS

C

L

D1

D

0.026 (0.66)

0.032 (0.81)

0.045 (1.14)
MIN

0.050 (1.27) TP

0.042 (1.07)

0.056 (1.42)

EE1

VIEW “A” TYP.

C

L

A1

A

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)
MIN

0.004 (0.10) C

0.025 (0.64)

0.045 (1.14)

D2/E2

D2/E2

VIEW “A”

0.020 (0.51)
MIN

SEATING

-C-

PLANE

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.

4. To be measured at seating plane contact point.

-C-

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

N28.45 (JEDEC MS-018AB ISSUE A)

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

R

SYMBOL

A 0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D 0.485 0.495 12.32 12.57 ­D1 0.450 0.456 11.43 11.58 3
D2 0.191 0.219 4.86 5.56 4, 5

E 0.485 0.495 12.32 12.57 ­E1 0.450 0.456 11.43 11.58 3
E2 0.191 0.219 4.86 5.56 4, 5

N28 286

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

Rev. 2 11/97

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN4831.14

December 18, 2006