Intersil Corporation HC55151, HC55150, HC55143, HC55142, HC55141 Datasheet

HC55120, HC55121, HC55130, HC55131, HC55140,

TM

HC55141, HC55142, HC55143, HC55150, HC55151

Data Sheet June 2000

Low Power Universal SLIC Family

The UniSLIC14 is a family of Ultra Low Power SLICs. The feature set and common pinouts of the UniSLIC14 family positions it as a universal solution for: Plain Old Telephone Service (POTS),PBX,Central Office, Loop Carrier,Fiber in the Loop, ISDN-TA and NT1+, Pairgain and Wireless Local Loop.

The UniSLIC14 family achieves its ultra low power operation through: Its automatic single and dual battery selection (based on line length) and battery tracking anti clipping to ensure the maximum loop coverage on the lowest battery voltage. This architecture is ideal for power critical applications such as ISDN NT1+, Pairgain and Wireless local loop products.

The UniSLIC14 family has many user programmable features. This family of SLICs delivers a low noise, low component count solution for Central Ofﬁce and Loop Carrier universal voice grade designs. The product family integrates advanced pulse metering, test and signaling capabilities, and zero crossing ring control.

The UniSLIC14 family is designed in the Intersil “Latch” free Bonded Wafer process. This process dielectrically isolates the active circuitry toeliminate anyleakage paths as foundin our competition’s JI process. This makes the UniSLIC14 family compliant with “hot plug” requirements and operation in harsh outdoor environments.

Block Diagram

RRLY

TRLY1 TRLY2

DT

DR

TIP

RING

BGND

AGND

V

BH

V

BL

V

CC

RING AND TEST

RELAY DRIVERS

ZERO CURRENT

CROSSING

RING TRIP

DETECTOR

POLARITY REVERSAL

2-WIRE

INTERFACE

BATTERY

SELECTION

AND

BIAS

NETWORK

STATE

DECODER

AND

DETECTOR

LOGIC

LOOP CURRENT

DETECTOR

GKD/LOOP LENGTH

DETECTOR

LINE FEED

CONTROL

4-WIRE INTERFACE

VF SIGNAL PATH

PULSE METERING

SIGNAL PATH

SPM

C1 C2

C3 C4

C5 SHD

GKD_LVM

CRT_REV_LVM

ILIM RSYNC_REV ROH CDC RDC_RAC RD

V

TX

V

RX

PTG ZT C

H

File Number 4659.5

Features

• Ultra Low Active Power (OHT) < 60mW

• Single/Dual Battery Operation

• Automatic Silent Battery Selection

• Power Management/Shutdown

• Battery Tracking Anti Clipping

• Single 5V Supply with 3V Compatible Logic

• Zero Crossing Ring Control

- Zero Voltage On/Zero Current Off

• Tip/Ring Disconnect

• Pulse Metering Capability

• 4 Wire Loopback

• Programmable Current Feed

• Programmable Resistive Feed

• Programmable Loop Detect Threshold

• Programmable On-Hook and Off-Hook Overheads

• Programmable Overhead for Pulse Metering

• Programmable Polarity Reversal Time

• Selectable Transmit Gain 0dB/-6dB

• 2 Wire Impedance Set by Single Network

• Loop and Ground Key Detectors

• On-Hook Transmission

• Common Pinout

• HC55121

- Polarity Reversal

• HC55130

- -63dB Longitudinal Balance

• HC55140

- Polarity Reversal

- Ground Start

- Line Voltage Measurement

- 2 Wire Loopback

- -63dB Longitudinal Balance

• HC55142

- Polarity Reversal

- Ground Start

- Line Voltage Measurement

- 2.2V

Pulse Metering

RMS

- 2 Wire Loopback

• HC55150

- Polarity Reversal

- Line Voltage Measurement

- 2.2V

Pulse Metering

RMS

- 2 Wire Loopback

Applications

• Related Literature

- AN9871, User’s Guide for UniSLIC14 Eval Board

4-1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Ordering Information

MAX

PART

NUMBER

HC55120CB 30

HC55120CM 30

HC55121IB 30

HC55121IM 30

HC55130IB 45 63dB -40 to85M28.3

HC55130IM 45 63dB -40 to85N28.45

HC55131IM 45

HC55140IB 45

HC55140IM 45

HC55141IM 45

HC55142IB 45

HC55142IM 45

HC55143IM 45

HC55150CB 45

HC55150CM 45

HC55151CM 45

HC5514XEVAL1 Evaluation board

LOOP

CURRENT

(mA)

POLARITY

REVERSAL

GND

START

GND KEY

•

•• • •

••• • •

••• • ••

••• • • •

••• • •••

••••

•••••

LINE

VOLTAGE

MEASUREMENT

†

PULSE

METERING

2 TEST RELAY

DRIVERS

† Available by placing SLIC in Test mode.

2 WIRE

LOOP-

BACK

LONGITUDINAL

†

•

BALANCE

53dB 0 to 70 M28.3

53dB 0 to 70 N28.45

53dB -40 to85M28.3

53dB -40 to85N28.45

63dB -40 to85N32.45x55

63dB -40 to85M28.3

63dB -40 to85N28.45

63dB -40 to85N32.45x55

63dB -40 to85M28.3

63dB -40 to85N28.45

63dB -40 to85N32.45x55

55dB 0 to 70 M28.3

55dB 0 to 70 N28.45

55dB 0 to 70 N32.45x55

TEMP

RANGE

o

C)

(

PKG.

NO.

SOIC

PLCC

SOIC

PLCC

SOIC

PLCC

SOIC

PLCC

SOIC

PLCC

SOIC

PLCC

Device Operating Modes

C3 C2 C1 DESCRIPTION HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1

0 0 0 Open Circuit

4-Wire Loopback

0 0 1 Ringing 0 1 0 Forward Active 0 1 1 Test Forward Active

2 Wire Loopback and Line Voltage Measurement

1 0 0 Tip Open Ground Start 1 0 1 Reserved 1 1 0 Reverse Active 1 1 1 Test Reverse Active

Line Voltage Measurement

4-2

••••••

• •••

••

••••••

• •••

•••

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Absolute Maximum Ratings T

Temperature, Humidity

Storage Temperature Range . . . . . . . . . . . . . . . . -65oC to 150oC

Operating Temperature Range. . . . . . . . . . . . . . . -40oC to 110oC

Operating Junction Temperature Range. . . . . . . . -40oC to 150oC

Power Supply (-40oC ≤ TA≤ 85oC)

Supply Voltage VCC to GND . . . . . . . . . . . . . . . . . . . .-0.4V to 7V

Supply Voltage VBLto GND. . . . . . . . . . . . . . . . . . . .-VBHto 0.4V

Supply Voltage VBH to GND, Continuous. . . . . . . . . .-75V to 0.4V

Supply Voltage VBH to GND, 10ms . . . . . . . . . . . . . .-80V to 0.4V

Relay Driver

=25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θ

28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . 52oC/W

28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . 45oC/W

32 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . 66.2oC/W

Continuous Power Dissipation at 85oC

28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W

28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0W

32 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4W

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . 300oC

(PLCC, SOIC - Lead Tips Only) Derate above 70oC

JA

Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . . . . . .0V to 14V

Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

Digital Inputs, Outputs (C1, C2, C3, C4, C5, SHD, GKD_LVM)

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to V

Output Voltage (SHD, GKD_LVM Not Active). . . . . . -0.4V to V

CC CC

Output Current (SHD,GKD_LVM) . . . . . . . . . . . . . . . . . . . . . 5mA

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V

Gate Count. . . . . . . . . . . . . . . . . . . . . . . .543 Transistors, 51 Diodes

Tip and Ring Terminals

Tipx or Ringx, Current, Pulse < 10ms, T Tipx or Ringx, Current, Pulse < 1ms, T Tipx or Ringx, Current, Pulse < 10µs, T Tipx or Ringx, Current, Pulse < 1µs, T Tipx or Ringx, Pulse < 250ns, T

REP

> 10s . . . . . . . . . .2A

REP

> 10s . . . . . . . . . . .5A

REP

> 10s . . . . . . . . .15A

REP

> 10s . . . . . . . . . .20A

REP

> 10s 20A

Tipx and Ringx Terminals (-40oC ≤ TA ≤ 85oC)

Tipx or Ringx Current. . . . . . . . . . . . . . . . . . . . -100mA to 100mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Typical Operating Conditions

These represent the conditions under which the device was developed and are suggested as guidelines.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Ambient Temperature HC55120, HC55150/1 0 - 70

HC55121, HC55130/1, HC55140/1,

-40 - 85

HC55142/3

o

C

o

C

VBH with Respect to GND -58 - -8 V VBL with Respect to GND V

BH

-0 V

VCC with Respect to GND 4.75 - 5.25 V

4-3

Electrical Speciﬁcations T

= -40oCto85oC, VCC= +5V ±5%, VBH= -48V,VBL= -24V,PTG = Open, RP1=RP2=0Ω, ZT= 120kΩ,R

A

R

= 40kΩ,CH= 0.1µF, CDC= 4.7µF, C

OH

= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Speciﬁed.

RT/REV

to the part. (NA) symbol used to indicate the test does not apply to the part.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1

2-WIRE PORT

Overload Level, Off Hook Forward and Reverse

Overload Level, On Hook Forward and Reverse

4-4

Input Impedance (Into Tip and Ring) - ZT/200 - Ω Longitudinal Impedance (Tip, Ring)

1% THD, I

DCMET

≥ 18mA

3.2 - - V

(Note 2, Figure 1) 1% THD, IDCMET ≤ 5mA

1.3 - - V

(Note 3, Figure 1)

0 < f < 100Hz (Note 4, Figure 2) - 0 - Ω/Wire Forward

Forward and Reverse

LONGITUDINAL CURRENT LIMIT (TIP, RING)

On-Hook, Off-Hook (Active), RL = 736Ω Forward and Reverse

No False Detections, (Loop Current), LB > 45dB (Notes 5, 6, Figures 3A, 3B)

28 - - mA

PEAK

Wire Forward

/

RMS

= 38.3kΩ,RD= 50kΩ, RDC_RAC = 20kΩ,

LIM

Symbol used to indicate the test applies

(•)

Forward

Only

Forward

Only

Forward

•

Only

Forward

Only

•••

••••••

Forward

Only

•

Only

Forward

•

Only

•••

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

V

TIP

V

R

TR

L

I

DCMET

RING VRX

TX

E

RX

FIGURE 1. OVERLOAD LEVEL (OFF HOOK, ON HOOK)

368Ω

E

L

C10µF

368Ω

TIP

A

RING

A

SHD

V

TX

VRX

A

300Ω

A

LZT = VT/A

T

R

1V

RMS

0 < f < 100Hz

E

L

C

FIGURE 2. LONGITUDINAL IMPEDANCE

368Ω

A

E

C

L

368Ω

A

T

V

T

V

TIP

RING

R

TIP

RING

SHD

V

TX

VRX

LZR = VR/A

V

TX

VRX

R

V

TX

FIGURE 3A. LONGITUDINAL CURRENT LIMIT ON-HOOK (ACTIVE) FIGURE 3B. LONGITUDINAL CURRENT LIMIT OFF-HOOK (ACTIVE)

Electrical Speciﬁcations T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1

OFF-HOOK LONGITUDINAL BALANCE

Longitudinal to Metallic (Note 7) Forward and Reverse

4-5

Longitudinal to Metallic (Note 7) Forward and Reverse

Longitudinal to 4-Wire (Note 9) (Forward and Reverse)

Metallic to Longitudinal (Note 10) Forward and Reverse

4-Wire to Longitudinal (Note 11) Forward and Reverse

= -40oCto85oC, VCC= +5V ±5%, VBH= -48V,VBL= -24V,PTG = Open, RP1=RP2=0Ω, ZT= 120kΩ,R

A

ROH= 40kΩ,CH= 0.1µF, CDC= 4.7µF, C to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

IEEE 455 - 1985, RLR, RLT = 368Ω Normal Polarity:

0.2kHz < f < 1.0kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 55

1.0kHz < f < 3.4kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 55

0.2kHz < f < 1.0kHz, -40oC to 85oC - - - dB NA 53 63 63 63 NA

1.0kHz < f < 3.4kHz, -40oC to 85oC - - - dB NA 53 58 58 58 NA Reverse Polarity 0.2kHz < f < 3.4kHz,

(Figure 4)

RLR, RLT = 300Ω, Normal Polarity:

0.2kHz < f < 1.0kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 55

1.0kHz < f < 3.4kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 55

0.2kHz < f < 1.0kHz, -40oC to 85oC - - - dB NA 53 63 63 63 NA

1.0kHz < f < 3.4kHz, -40oC to 85oC - - - dB NA 53 58 58 58 NA Reverse Polarity 0.2kHz < f < 3.4kHz,

(Figure 4)

Normal Polarity: Forward

o

0.2kHz < f < 1.0kHz, 0

1.0kHz < f < 3.4kHz, 0

0.2kHz < f < 1.0kHz, -40oC to 85oC - - - dB NA 53 63 63 63 NA

1.0kHz < f < 3.4kHz, -40 Reverse Polarity 0.2kHz < f < 3.4kHz,

(Figure 4) FCC Part 68, Para 68.310 (Note 8)

0.2kHz < f < 3.4kHz, (Figure 5)

0.2kHz < f < 3.4kHz, (Figure 5) 40 - - dB Forward

C to 70oC - - - dB 53 NA NA NA NA 61

o

C to 70oC - - - dB 53 NA NA NA NA 61

o

C to 85oC - - - dB NA 53 58 58 58 NA

= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Speciﬁed.

RT/REV

MIN MIN MIN MIN MIN MIN

Forward

Only

--- dB NA53 NA 58 58 55

MIN MIN MIN MIN MIN MIN

Forward

Only

--- dB NA53 NA 58 58 55

MIN MIN MIN MIN MIN MIN

Only

- - dB NA 53 NA 58 58 61

40 50 - dB Forward

Only

•

= 38.3kΩ,RD= 50kΩ, RDC_RAC = 20kΩ,

LIM

Symbol used to indicate the test applies

(•)

Forward

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

•••

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Electrical Speciﬁcations T

= -40oCto85oC, VCC= +5V ±5%, VBH= -48V,VBL= -24V,PTG = Open, RP1=RP2=0Ω, ZT= 120kΩ,R

A

ROH= 40kΩ,CH= 0.1µF, CDC= 4.7µF, C

= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Speciﬁed.

RT/REV

to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1

R

4-6

LT

E

L

C

2.16µF

R

LR

FIGURE 4. LONGITUDINAL TO METALLIC AND LONGITUDINAL TO 4-WIRE BALANCE

TIP

V

TR

RING

V

TX

VRX

V

TX

FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO LONGITUDINAL

BALANCE

2-Wire Return Loss Forward and Reverse

0.2kHz to 1.0kHz (Note 12, Figure 6) 30 35 - dB Forward

1.0kHz to 3kHz (Note 12, Figure 6) 23 25 - dB 3kHz to 3.4kHz (Note 12, Figure 6) 21 23 - dB

TIP IDLE VOLTAGE (User Programmable)

TIPX Idle Voltage Active, IL < 5mA -2.6 -2.2 -1.8 V Forward Forward and Reverse

RING IDLE VOLTAGE (User Programmable)

RINGX Idle Voltage Forward and Reverse

V

TR

Forward and Reverse V

TR(ROH)

Pulse Metering

Active, I Tip open, IL < 5mA -46.4 -45.3 -44.2 V Active, I

Active, IL≥ 8.5mA, ROH = 50kΩ 36 38.1 - V NA

< 5mA -46.4 -45.3 -44.2 V Forward

L

< 5mA 41 43.1 45 V Forward

L

Forward and Reverse

2.16µF

C

V

L

300Ω

Only

= 38.3kΩ,RD= 50kΩ, RDC_RAC = 20kΩ,

LIM

Symbol used to indicate the test applies

(•)

R

LT

R

LR

TIP

E

TR

RING

V

TX

VRX

E

RX

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Forward

•

Only

Forward

Only

Forward

Only

Forward

Only

NA NA

•••

••

Z

D

TIP

R

V

S

R

LR

V

M

Z

IN

RING

FIGURE 6. TWO-WIRE RETURN LOSS

V

TX

VRX

TIP

V

TX

V

TX

Z

L

600Ω

V

TR

E

G

R

L

VRX

RING

FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT), OUTPUT OFFSET

VOLTAGE AND HARMONIC DISTORTION

Electrical Speciﬁcations T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1

4-WIRE TRANSMIT PORT (VTX)

Overload Level, Off Hook (IL≥ 18mA) Forward and Reverse

Overload Level, On Hook (IL≤ 5mA)

4-7

Forward and Reverse VTX Output Offset Voltage

Forward and Reverse Output Impedance

(Guaranteed by Design)

4-WIRE RECEIVE PORT (VRX)

VRX Input Impedance (Guaranteed by Design)

FREQUENCY RESPONSE (OFF-HOOK)

2-Wire to 4-Wire Forward and Reverse

4-Wire to 2-Wire Forward and Reverse

4-Wire to 4-Wire Forward and Reverse

= -40oCto85oC, VCC= +5V ±5%, VBH= -48V,VBL= -24V,PTG = Open, RP1=RP2=0Ω, ZT= 120kΩ,R

A

ROH= 40kΩ,CH= 0.1µF, CDC= 4.7µF, C to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

(ZL > 20kΩ, IL 1% THD) (Note 13, Figure 7) TA = 0oC to 85oC TA = -40oC to 0oC

(ZL > 20kΩ, 1% THD) (Note 14, Figure 7)

EG = 0, ZL= ∞, (Note 15, Figure 7) -200 - 200 mV Forward

0.2kHz < f < 03.4kHz - 0.1 1 Ω

0.2kHz < f < 3.4kHz - 500 600 kΩ

Relative to 0dBm at 1.0kHz, ERX= 0V Forward

0.3kHz < f < 3.4kHz -0.15 - 0.15 dB f = 8.0kHz (Note 16, Figure 8) - 0.24 0.5 dB f = 12kHz (Note 16, Figure 8) - 0.58 1.0 dB f = 16kHz (Note 16, Figure 8) - 1.0 1.5 dB Relative to 0dBm at 1.0kHz, EG= 0V

0.3kHz < f < 3.4kHz -0.15 - 0.15 dB f = 8kHz (Note 17, Figure 8) -0.5 0.24 - dB f = 12kHz (Note 17, Figure 8) -1.0 0.58 - dB f = 16kHz (Note 17, Figure 8) -1.5 1.0 - dB Relative to 0dBm at 1.0kHz, EG= 0V Forward

0.3kHz < f < 3.4kHz (Note 18, Figure 8) -0.15 - 0.15 dB 8kHz, 12kHz, 16kHz (Note 18, Figure 8) -0.5 0 0.5 dB

= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Speciﬁed.

RT/REV

Forward

3.2 - - V

3.0 - - V

1.3 - - V

PEAK PEAK

PEAK

Only

Forward

Only

••••••

Only

Forward

Only

•

= 38.3kΩ,RD= 50kΩ, RDC_RAC = 20kΩ,

LIM

Symbol used to indicate the test applies

(•)

Forward

Only

Forward

Only

Forward

Only

Forward

Only

•••

Forward

Only

•••

Forward

Only

•••

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

TIP

R

600Ω

L

V

TR

RING VRX

E

G

FIGURE 8. FREQUENCY RESPONSE, INSERTION LOSS, GAIN TRACKING

AND HARMONIC DISTORTION

V

PTG

TX

OPEN

E

RX

V

TX

V

TIP

R

L

600Ω

V

TR

RING

FIGURE 9. IDLE CHANNEL NOISE

TX

VRX

V

TX

Electrical Speciﬁcations T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1

INSERTION LOSS

2-Wire to 4-Wire Forward and Reverse

4-Wire to 2-Wire

4-8

Forward and Reverse

GAIN TRACKING (Ref = -10dBm, at 1.0kHz)

2-Wire to 4-Wire Forward and Reverse

4-Wire to 2-Wire Forward and Reverse

NOISE

Idle Channel Noise at 2-Wire C-Message Weighting - 10.5 13 dBrnC Forward Forward and Reverse Psophometric Weighting (Note 24,

Idle Channel Noise at 4-Wire C-Message Weighting - 10.5 13 dBrnC Forward Forward and Reverse Psophometrical Weighting

HARMONIC DISTORTION

2-Wire to 4-Wire Forward and Reverse

4-Wire to 2-Wire Forward and Reverse

= -40oCto85oC, VCC= +5V ±5%, VBH= -48V,VBL= -24V,PTG = Open, RP1=RP2=0Ω, ZT= 120kΩ,R

A

ROH= 40kΩ,CH= 0.1µF, CDC= 4.7µF, C to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

0dBm, 1kHz PTG = Open (Note 19, Figure 8) -0.2 - 0.2 dB Forward PTG = GND (Note 20, Figure 8) -6.22 -6.02 -5.82 dB 0dBm, 1kHz (Note 21, Figure 8) -0.2 - 0.2 dB Forward

-40dBm to +3dBm (Note 22, Figure 8) -0.1 - 0.1 dB Forward

-55dBm to -40dBm (Note 22, Figure 8) -0.2 - 0.2 dB

-40dBm to +3dBm (Note 23, Figure 8) -0.1 - 0.1 dB Forward

-55dBm to -40dBm (Note 23, Figure 8) -0.2 - 0.2 dB

Note 30, Figure 9)

(Note 25, Note 30, Figure 9)

0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 7)

0dBm, 0.3kHz to 3.4kHz (Note 27, Figure 8)

= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Speciﬁed.

RT/REV

- -79.5 -77 dBmp

- -67 -50 dB Forward

Only

= 38.3kΩ,RD= 50kΩ, RDC_RAC = 20kΩ,

LIM

Symbol used to indicate the test applies

(•)

Forward

• •••

•

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

•••

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

TIP

V

TX

R

L

V

600Ω

FIGURE 10. CONSTANT LOOP CURRENT TOLERANCE

TR

RING

LIM

VRX

R

LIM

38.3kΩ

7kΩ

V

BH

I

R1

R

1

FIGURE 11. TIPX VOLTAGE

TIP

S

RING

V

VRX

TX

Electrical Speciﬁcations T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1

BATTERY FEED CHARACTERISTICS

Constant Loop Current Tolerance 18mA ≤ IL ≤ 45mA, Forward IL = 26.5mA, R

Forward and Reverse Tip Open State TIPX Leakage

4-9

Current Tip Open State RINGX Current R1= 0Ω, VBH = -48V, R

Tip Open State RINGX Voltage 5mA < IR1 < 26mA (Figure 11) - 42.8 - V Tip Voltage (Ground Start) Active State, (S Open) R1= 150Ω

Tip Voltage (Ground Start) Active State, (S Closed) Tip Lead to

Open Circuit State Loop Current (Active) RL = 0Ω -20 0 20 µA

LOOP CURRENT DETECTOR

Programmable Threshold I Forward and Reverse I

GROUND KEY DETECTOR

Ground Key Detector Threshold Tip/Ring Current Difference

LINE VOLTAGE MEASUREMENT

Pulse Width (

RING TRIP DETECTOR (DT, DR)

Ring Trip Comparator Current Source Res = 2MΩ -2- µA Input Common-Mode Range Source Res = 2MΩ --±200 V

= 38.3kΩ

LIM

GKD_LVM) Pulse Width = (20)(C

= -40oCto85oC, VCC= +5V ±5%, VBH= -48V,VBL= -24V,PTG = Open, RP1=RP2=0Ω, ZT= 120kΩ,R

A

ROH= 40kΩ,CH= 0.1µF, CDC= 4.7µF, C to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

(Note 27, Figure 10) 0.92I

S = Closed (Figure 11) - - -200 µA

= 38.3kΩ 22.6 26.8 31 mA

LIM

R1 = 2.5kΩ, VBH = -48V (Figure 11) 15.5 17.1 18.2 mA

(Figure 11)

-48V Through 7kΩ, Ring Lead to Ground Through 150Ω (Figure 11)

= (500/ RD) ≥ 5mA, 0.9I

LTh

= 8.5mA

LTh

R

= 58.8kΩ

D

Tip Open 5 8 11 mA Active (Note 29, R1 =2.5kΩ, Figure 12) 12.5 20 27.5 mA

REV.../ILIM

) 0.32 0.36 0.4 ms/V NA NA NA

= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Speciﬁed.

RT/REV

I

L

-5.3 -4.8 -4.3 V NA NA NA

-5.3 -4.8 -4.3 V NA NA NA NA

LThILTh

1.08I

L

1.1I

LTh

mA

L

mA Forward

= 38.3kΩ,RD= 50kΩ, RDC_RAC = 20kΩ,

LIM

Symbol used to indicate the test applies

(•)

Forward

Only

•

Only

•••

••••••

••

NA

••

••••••

Forward

Only

•

••

Only

NA

•••

••

NA

•••

••••••

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Electrical Speciﬁcations T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1

RING RELAY DRIVER

V

at 30mA IOL = 30mA - 0.2 0.5 V

SAT

V

at 40mA IOL = 40mA - 0.52 0.8 V

SAT

Off State Leakage Current VOH = 13.2V - 0.1 10 µA

4-10

TEST RELAY DRIVER (TRLY1, TRLY2)

V

at 30mA I

SAT

V

at 40mA I

SAT

Off State Leakage Current V

= -40oCto85oC, VCC= +5V ±5%, VBH= -48V,VBL= -24V,PTG = Open, RP1=RP2=0Ω, ZT= 120kΩ,R

A

ROH= 40kΩ,CH= 0.1µF, CDC= 4.7µF, C to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

= 30mA - 0.3 0.5 V NA NA NA/• NA/• NA/• NA/•

OL

= 40mA - 0.62 0.9 V NA NA NA/• NA/• NA/• NA/•

OL

= 13.2V - - 10 µA NA NA NA/• NA/• NA/• NA/•

OH

= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Speciﬁed.

RT/REV

= 38.3kΩ,RD= 50kΩ, RDC_RAC = 20kΩ,

LIM

Symbol used to indicate the test applies

(•)

••••••

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

TIP

RING

2.5kΩ

FIGURE 12. GROUND KEY DETECT

DIGITAL INPUTS (C1, C2, C3)

Input Low Voltage, V Input High Voltage, V Input Low Current, I Input High Current, I

DETECTOR OUTPUTS (SHD, GKD_LVM)

SHD Output Low Voltage, V Forward, Reverse

SHD Output High Voltage, V Forward, Reverse

GKD_LVM Output Low Voltage, VOLForward and Tip Open

GKD_LVM Output High Voltage, VOHForward and Tip Open

Internal Pull-Up Resistor - 15 - kΩ

IL

IH

IL

IH

OL

OH

VIL = 0.4V - - -10 µA VIH = 2.5V - 25 50 µA

IOL = 1mA - - 0.5 V Forward

IOH = 100µA 2.7 - - V Forward

IOL = 1mA R1 = 2.5kΩ (Figure 11)

IOH = 100µA 2.7 - - V GKD GKD NA GKD_

0 - 0.8 V

2.0 - V

- - 0.5 V GKD GKD NA GKD_

CC

V

TX

VRX

SHD

V

••••••

Forward

Only

•

Only

Forward

Only

•••

LVM

GKD_

LVM

GKD_

LVM

••••••

Electrical Speciﬁcations T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1

POWER DISSIPATION (VBH = -48V, VBL = -24V)

Open Circuit State C1, C2, C3 = 0, 0, 0 - 25 - mW Forward

On-Hook, Active C1, C2, C3 = 0, 1, 0

4-11

Forward and Reverse IL= 0mA, Longitudinal

POWER SUPPLY CURRENTS (VBH = -48V, VBL = -24V)

VCC Current, I

VBH Current, I

VBL Current, I

VCC Current, I Forward and Reverse

VBH Current, I Forward and Reverse

VBL Current, I Forward and Reverse

POWER SUPPLY REJECTION RATIOS

VCC to 2 or 4 Wire Port Forward and Reverse

VBH to 2 or 4 Wire Port Forward and Reverse

VBL to 2 or 4 Wire Port Forward and Reverse

TEMPERATURE GUARD

Junction Threshold Temperature - 175 -

CC

BH

BL

CC

BH

BL

= -40oCto85oC, VCC= +5V ±5%, VBH= -48V,VBL= -24V,PTG = Open, RP1=RP2=0Ω, ZT= 120kΩ,R

A

ROH= 40kΩ,CH= 0.1µF, CDC= 4.7µF, C to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

C1, C2, C3 = 1, 1, 0

Current = 0mA

Open Circuit State - 2.25 3.0 mA Forward

Active State IL= 0mA, Longitudinal Current = 0mA

Active State RL = 600Ω 50Hz < f < 3400Hz, V

=100mV

IN

= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Speciﬁed.

RT/REV

- 52 - mW Forward

- 0.3 0.45 mA Forward

- 0.022 0.035 mA Forward

- 2.7 3.6 mA Forward

- 0.8 1.06 mA Forward

- - 0.01 mA Forward

- 40 - dB Forward

o

C•

Only

= 38.3kΩ,RD= 50kΩ, RDC_RAC = 20kΩ,

LIM

Symbol used to indicate the test applies

(•)

Forward

•

Only

•••

• •••

Forward

•

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

Forward

Only

•••

•••••

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Notes

2. Overload Level (Two-WirePort, Off Hook) - The overload levelis specified at the 2-wire port (VTR) with the signal source at the 4-wire receive port (ERX). RL = 600Ω, I Increase the amplitude of ERXuntil 1% THD is measured at VTR. Reference Figure 1.

3. Overload Level (Two-WirePort, On Hook) - The overload levelis specified at the 2-wire port (VTR) with the signal source at the 4-wire receive port (ERX). RL = ∞, I

DCMET

the amplitude of ERX until 1% THD is measured at VTR. Reference Figure 1.

4. Longitudinal Impedance - The longitudinal impedance is computed using the following equations, where TIP and RING voltages are referenced to ground. LZT,LZR,VT,VR,ARand A are deﬁned in Figure 2. (TIP) LZT = VT/A (RING) LZR = VR/A where: EL = 1V

T

R

(0Hz to 100Hz)

RMS

5. Longitudinal Current Limit (On-Hook Active) - On-Hook longitudinal current limit is determined by increasing the (60Hz) amplitude of EL (Figure 3A) until the 2-wire longitudinal current is greater than 28mA remains low (no false detection) and the 2-wire to 4-wire

/Wire. Under this condition, SHD pin

RMS

longitudinal balance is veriﬁed to be greater than 45dB (LB

= 20log VTX/EL).

2-4

6. Longitudinal Current Limit (Off-Hook Active) - Off-Hook longitudinal current limit is determined by increasing the (60Hz) amplitude of EL (Figure 3B) until the 2-wire longitudinal current is greater than 28mA remains high (no false detection) and the 2-wire to 4-wire

/Wire. Under this condition, SHD pin

RMS

longitudinal balance is veriﬁed to be greater than 45dB (LB

= 20log VTX/EL).

2-4

7. Longitudinal to Metallic Balance - The longitudinal to metallic balance is computed using the following equation:

BLME = 20 log (EL/VTR), where: EL and VTR are deﬁned in Figure 4.

8. Metallic to Longitudinal FCC Part 68, Para 68.310 - The metallic to longitudinal balance is deﬁned in this spec.

9. Longitudinal to Four-WireBalance - The longitudinal to4-wire balance is computed using the following equation:

BLFE = 20 log (EL/VTX), EL and VTX are deﬁned in Figure 4.

10. Metallic to Longitudinal Balance - The metallic to longitudinal balance is computed using the following equation:

BMLE = 20 log (ETR/VL), ERX = 0 where: E

and ERX are deﬁned in Figure 5.

TR,VL

11. Four-Wire to LongitudinalBalance - The 4-wire tolongitudinal balance is computed using the following equation:

BFLE = 20 log (ERX/VL), ETR = source is removed. where: E

and ETR are deﬁned in Figure 5.

RX,VL

12. Two-WireReturn Loss - The 2-wire return loss is computed using the following equation: r = -20 log (2VM/VS) where: ZD= The desired impedance; e.g., the characteristic impedance of the line, nominally 600Ω. (Reference Figure 6).

13. Overload Level (4-Wire Port Off-Hook) - The overload level is speciﬁed at the 4-wire transmit port (VTX) with the signal source (EG) at the 2-wire port, ZL = 20kΩ, RL = 600Ω (Reference Figure 7). Increase the amplitude of EG until 1% THD is measured at VTX. Note the PTG pin is open, and the gain from the 2-wire port to the 4-wire port is equal to 1.

≥ 18mA.

DCMET

= 0mA. Increase

14. Overload Level (4-Wire Port On-Hook) - Theoverload levelis speciﬁed at the 4-wire transmit port (VTX) with the signal source (EG) at the 2-wire port, ZL= 20kΩ, RL= ∞(Reference Figure 7). Increase the amplitude of EGuntil 1% THD is measured at VTX. Note the PTG pin is open, and the gain from the 2-wire port to the 4-wire port is equal to 1.

15. Output OffsetVoltage - The output offset voltage is speciﬁed with the following conditions: EG=0,RL= 600Ω,ZL= ∞ and is measured at VTX. EG,RL, VTX and ZLare deﬁned in Figure 7.

16. Two-Wireto Four-Wire Frequency Response - The 2-wire to 4-wire frequency response is measured with respect to EG= 0dBm at 1.0kHz, ERX= 0V (VRX input floating), RL= 600Ω. The frequency response is computed using the following equation:

F

= 20 log (VTX/VTR), vary frequency from 300Hz to 3.4kHz

T

2-4

and compare to 1kHz reading. VTX, VTR,RLand EG are deﬁned in Figure 8.

17. Four-Wireto Two-WireFrequencyResponse - The 4-wire to 2wire frequency response is measured with respectto ERX= 0dBm at 1.0kHz, EG source removed from circuit, RL = 600Ω. The frequency response is computed using the following equation:

F

= 20 log (VTR/ERX), vary frequency from 300Hz to 3.4kHz

4-2

and compare to 1kHz reading. VTR,RLand ERX are deﬁned in Figure 8.

18. Four-Wire to Four-Wire FrequencyResponse - The 4-wire to 4-wire frequency response is measured with respect to ERX= 0dBm at 1.0kHz, EG source removed from circuit, RL= 600Ω. The frequency response is computed using the following equation:

F

= 20 log (VTX/ERX), vary frequency from 300Hz to 3.4kHz

4-4

and compare to 1kHz reading. V

and ERX are deﬁned in Figure 8.

TX ,RL

19. Two-WiretoFour-WireInsertionLoss(PTG = Open) - The 2-wire to 4-wire insertion loss is measured with respect to EG= 0dBm at 1.0kHz input signal, ERX = 0 (VRX input floating), RL= 600Ω and is computed using the following equation:

L

= 20 log (VTX/VTR)

2-4

where: VTX, VTR,RLand EG are deﬁned in Figure 8. (Note: The fuse resistors, RF, impact the insertion loss. The speciﬁed insertion loss is for RF1 = RF2 = 0).

20. Two-WiretoFour-WireInsertion Loss (PTG = AGND) - The 2-wire to 4-wire insertion loss is measured with respect to EG= 0dBm at 1.0kHz input signal, ERX = 0 (VRX input floating), RL = 600Ω and is computed using the following equation:

L

= 20 log (VTX/VTR)

2-4

where: VTX, VTR,RLand EG are deﬁned in Figure 8. (Note: The fuse resistors, RF, impact the insertion loss. The speciﬁed insertion loss is for RF1 = RF2 = 0).

21. Four-Wire to Two-WireInsertion Loss - The 4-wire to 2-wire insertion loss is measured based upon ERX = 0dBm, 1.0kHz input signal, EG source removed from circuit, RL = 600Ω and is computed using the following equation:

L

= 20 log (VTR/ERX)

4-2

where: VTR,RLand ERX are deﬁned in Figure 8.

22. Two-Wireto Four-Wire Gain Tracking - The 2-wire to 4-wire gain tracking is referenced to measurements taken for EG= -10dBm, 1.0kHz signal, ERX = 0 (VRX output ﬂoating), RL= 600Ω and is computed using the following equation.

G

=20• log (VTX/VTR) vary amplitude -40dBm to +3dBm, or

2-4

-55dBm to -40dBm and compare to -10dBm reading. VTX,RLand VTR are deﬁned in Figure 8.

4-12

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

23. Four-Wire to Two-WireGain Tracking - The 4-wire to 2-wire gain tracking is referenced to measurements taken for ERX= -10dBm, 1.0kHz signal, EG source removed from circuit, RL= 600Ω and is computed using the following equation:

G

= 20 • log (VTR/ERX) vary amplitude -40dBm to +3dBm,

4-2

or -55dBm to -40dBm and compare to -10dBm reading. VTR, RL and ERX are defined in Figure 8. The level is specified at

the 4-wire receiveport and referenced to a 600Ω impedance level.

24. Two-WireIdle Channel Noise - The 2-wire idle channel noise at VTR is specified with the 2-wire port terminated in 600Ω (RL) and with the 4-wire receive port (VTX) floating (Reference Figure 9).

25. Four-Wire Idle ChannelNoise - The 4-wire idlechannel noise at VTXis speciﬁed with the 2-wire port terminated in 600Ω (RL). The noise specification is with respect to a 600Ω impedance level at VTX. The 4-wire receive port (VTX) floating (Reference Figure 9).

Circuit Operation and Design Information

The UniSLIC14 family of SLICs are voltage feed current sense Subscriber Line Interface Circuits (SLIC). For short loop applications, the voltage between the tip and ring terminals variesto maintain a constant loop current. Forlong loop applications, the voltage between the tip and ring terminals are relatively constant and the loop current varies in proportion to the load.

The tip and ring voltages for various loop resistances are shown in Figure 13. The tip voltage remains relatively constant as the ring voltage moves to limit the loop current for short loops.

The loop current for various loop resistances are shown in Figure 14. For short loops, the loop current is limited to the programmed current limit, set by RILIM. For long loop applications, the loop current varies in accordance with Ohms law for the given tip to ring voltage and the loop resistance.

26. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic distortion is measured within the voice band with the following conditions. EG = 0dBm at 1kHz, RL = 600Ω. Measurement taken at VTX. (Reference Figure 7).

27. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic distortion is measured within the voice band with the following conditions. ERX = 0dBm0. Vary frequency between 300Hz and

3.4kHz, RL = 600Ω. Measurement taken at VTR. (Reference Figure 8).

28. Constant LoopCurrent - The constant loop current is calculated using the following equation:

IL = 1000/R

= VTR/600 (Reference Figure 10).

LIM

29. Ground KeyDetector - (TRIGGER) Ground the Ring pin through a 2.5kΩ resistor and verify that GKD goes low.

(RESET) Disconnect the Ring pin and verify that GKD goes high.

(Hysteresis) Compare difference between trigger and reset.

30. Electrical Test - Not tested in production at -40oC.

.

35

30

25

CONSTANT LOOP CURRENT

20

REGION

15

10

LOOP CURRENT (mA)

5

0

200 600 1K 1.4K 1.8K 2.2K 2.6K 3.8K3.0K 3.4K

CONSTANT TIP TO RING

VOLTAGE REGION

VBH = -48V RD = 41.2kΩ ROH = 38.3kΩ RDC_RAC = 19.6kΩ RILim = 33.2kΩ

LOOP RESISTANCE (Ω)

FIGURE 14. LOOP CURRENT vs LOOP RESISTANCE

0

TIP

-5

-10

-15

-20

-25

-30

-35 CONSTANT

-40

LOOP CURRENT

TIP AND RING VOLTAGES (V)

REGION

-45

-50 200 600 1000 1400 1800 2000 4K 10K6K 8K

RING

LOOP RESISTANCE (Ω)

CONSTANT TIP TO RING

VOLTAGE REGION

VBH = -48V RD = 41.2kΩ ROH = 38.3kΩ RDC_RAC = 19.6kΩ RILim = 33.2kΩ

-2.5V

-44.5V

FIGURE 13. TIP AND RING VOLTAGES vs LOOP RESISTANCE

4-13

The followingdiscussion separates the SLIC’s operation into its DC and AC paths, then follows up with additional circuit and design information.

DC Feed Curve

The DC feed curve for the UniSLIC14 family is user programmable. The user deﬁnes the on hook and off hook overhead voltages (including the overhead voltage for off hook pulse metering if applicable), the maximum and minimum loop current limits, the switch hook detect threshold and the battery voltage. From these requirements, the DC feed curve is customized for optimum operation in any given application.An Excel spread sheet to calculate the external components can be downloaded off our web site www.intersil.com/telecom/unislic14.xls.

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

VBH

2.5V

†

SLIC SELF PROGRAMMING

VOH(on) AT LOAD

CONSTANT

R

SAT

VOH(off) AT LOAD

CURRENT REGION

60kΩ SLOPE

I

SHD

IOH

TIP TO RING ABSOLUTE VOLTAGE (V)

RLOOP(max)

ISH- ILOOP(min) ILOOP(max)

†Internal overhead voltage automatically generated by the SLIC.

FIGURE 15. UniSLIC14 DC FEED CURVE

On Hook Overhead Voltage

DC FEED CURVE

V

BH

2.5V

V

OH(on)

TIP TO RING VOLTAGE

ISH- = I

SHD

ON HOOK OVERHEAD

ISH-

I

SHD

LOOP CURRENT

(0.6)

Switch Hook Detect threshold (I current for a constant on hook overhead voltage is deﬁned as ISH-.

The on hook overhead voltage, required for a given signal levelat the load, must take into account the AC voltage drop across the 2 external protection resistors (R internal sense resistors (R on hook overload voltage is calculated using Equation 1.

V

OH on()at LoadVsp on()

where V

OH(on) at Load

V

= Required on hook transmission for speech

sp(on)

= On hook overhead voltage at load

RP = Protection Resistors (Typically 30Ω) RS = Internal Sense Resistors (40Ω) ZL = AC load impedance for (600Ω)

1.5V = Additional on hook overhead voltage requirement

Theon hook overheadvoltage at the load (V

(on) at Load)

OH

is independent of the V battery voltage. Once set, the on hook voltage remains constant as the V

BH

battery voltagechanges. The on hook voltage also remains constant over temperature and line leakages up to 0.6 times the

). The maximum loop

SHD

) and the 2

) as shown in Figure 16. The AC

S

2RP2RS+



× 1.5V+=

1

----------------------------- -+

 

Z

P

L

BH

(EQ. 1)

LOOP CURRENT (mA)

To account for any process and temperature variations in the performance of the SLIC, 1.5V is added to the ov erhead voltage requirement for the on hook case in Equation 1 and

2.0V for the off hook case in Equation 3. Note the 2.5V overhead is automatically generated in the SLIC and is not part of the external overhead programming.

EXTERNAL PROTECTION RESISTOR

2R

V

ZL

(LOAD)

Z

L

P

V

OH ON OFF,()

Where: VZL is the required on hook or offhook transmission delivered to the load.

FIGURE 16. OVERHEAD VOLTAGE OF THE TIP AND RING

AMPLIFIERS

REQUIRED

OVERHEAD VOLTAGE

(ON, OFF)

V

OH

2R

S

INTERNAL SENSE RESISTORS

UniSLIC14

2RP2RS+



----------------------------- -

=

 

Z

L

Off Hook Overhead Voltage

DC FEED CURVE

V

SAT

V

OH(off)

TIP TO RING VOLTAGE

BH

2.5V

I

LOOP(min)

LOOP CURRENT

OFF HOOK OVER HEAD

The off hook overhead voltage V

(off) at Load is

OH

also independent ofthe V battery voltage and remains constant over temperature. The required off hook overheadvoltage is the sum of the AC and DC voltage drops across the internal sense resistors (R

TIP AND RING AMPLIFIERS

V

ZL

BH

, the

S)

4-14

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

protection resistors (R voltage for speech (V voltage for the pulse metering (V

), the required (peak) off hook

P

) and the required (peak) off hook

sp(off)

pm(off)

), if applicable.

The off hook overhead voltage is deﬁned in Equation 2 and calculated using Equation 3.

V

OH off()at LoadVOH Rsense()Vsp off()Vpm off()

++=

(EQ. 2)

where: V

OH(off) at Load

VOH(R

sense

across sense resistors (2R V

= Required (peak) off hook AC voltage for speech

sp(off)

V

pm(off)

= Off hook overhead voltage at load

) = Required overhead for the DC voltage drop

x Iloop

S

(max)

)

= Required (peak) off hook AC voltage for pulse

metering

+

2R



V

OH(off) at Load

80 I

× V

LOOP max()

+V

× 2.0V+

pm off()

×+=

sp off()

2R



1

 

2RS+

P

----------------------------- -+

Z

pm

P2RS

1

----------------------------- -+

 

Z

L

(EQ. 3)

where: 80 = 2R

s

+ 2R

(reference Figure 17)

INT

Zpm= Pulse metering load impedance (typically 200Ω).

2.0V = Additional off hook overhead voltage requirement

R

Resistance Calculation

SAT

The R

resistance of the DC feed curve is used to

SAT

determine the value of the RDC_RAC resistor (Equation 6). The value of this resistor has an effect on both the on hook and off hook overheads. In most applications the off hook condition will dominate the overhead requirements. Therefore,we’ll start by calculating the R

value for the off

SAT

hook conditions and then verify that the on hook conditions are also satisﬁed.

DC FEED CURVE

V

BH

V

SAT

V

OH(off)

2.5V R

SAT

When considering the Off hook condition, R to V

OH(off) at Load

Iloop

(Equation 4).

(min)

is equal

SAT

divided by

For the given system requirements (recommended

TIP TO RING VOLTAGE

I

LOOP(min)

LOOP CURRENT

application circuit in back of data sheet): Iloop (min) = 20mA, Iloop (max) = 30mA,

V

OH(off) AT LOAD

value of R

R

SAT(off)

=

SAT(off)

V

OH(off) at Load

--------------------------------------- -

I

LOOP(min)

R

SAT

I

LOOP(min)

V V V

= 3.2V

sp(off) spm(off) OH(off) at Load

= 0V

,

PEAK

,

PEAK

= 8.34V the

is equal to 417Ω as calculated in Equation 4.

8.34V

---------------- 417Ω== 20mA

(EQ. 4)

Before using this R

value, to calculate the RDC_RAC

SAT

resistor, we need to verify that the on hook requirements will also be met.

DC FEED CURVE

V

BH

V

SAT

V

OH(on)

2.5V

R

SAT

The on hook overhead voltage calculated with the off hook R

SAT

(R

SAT(off)

), is given in Equation 5 and equals 3.0V. The on hook overhead calculated with Equation 1

TIP TO RING VOLTAGE

V

OH(on) AT LOAD

R

SAT on()

ISH-(min)

LOOP CURRENT

R

ISH-

(min)

2.85V

----------------- - 395Ω==

7.2mA

equals 2.85V for the given system requirements (recommended application circuit in back of data sheet):

SAT

Switch Hook Detect threshold = 12mA, ISH- = (0.6)12mA =

7.2mA, V

sp(on)

Thus, the on hook overhead

= 0.775V

RMS

requirements of 2.85V will be

met if we use the R

V

OH on()

V

OH on()

V

OH on()

ISH-()R

7.2mA 417Ω×=

3.0V=

()=

SAT(off)

SAT off()

value.

(EQ. 5)

If the on hook overhead requirement is not met, then we need to use the R

SAT(on)

value to determine the RDC_RAC resistor value. The external saturation guard resistor RDC_RAC is equal to 50 times R

In the example above R

would equal 417Ω and

SAT

.

RDC_RAC would then equal to 20.85kΩ (closest standard value is 21kΩ).

RDC_RAC = 50 x R

SAT

(EQ. 6)

The Switch Hook Detect threshold current is set by resistor R

and is calculated using Equation 7. For the above

D

example R

is calculated to be 41.6kΩ (500/12mA). The

D

next closest standard value is 41.2kΩ.

500

------------

RD=

I

SHD

The true value of ISH-, for the selected value of R

(EQ. 7)

is given

D

by Equation 8:

ISH- =

500

--------- -

R

(0.6)

D

(EQ. 8)

Forthe example above,ISH- equals7.28mA (500 x0.6/ 41.2K). Verify that the value of ISH- is above the suspected line leakage of the application. The UniSLIC family will provide a constant on hook voltage level for leakage currents up to this value of line leakage.

4-15

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

DC FEED CURVE

V

BH

V

SAT

V

OH(off)

TIP TO RING VOLTAGE

2.5V

I

OH

ISH-

I

LOOP(min)

LOOP CURRENT

OFF HOOK OVER HEAD

for ISH- into Equation 9 and solving for R terms of I

R

OH

LOOP(min)

500

--------- -

I

OH

and RD.

500

--------------------------------------------==

I

LOOP(min)

- ISH-

The ROH resistor, which isused to set the offhook overhead voltage , is calculated using Equations 9 and 10.

I

is deﬁned as the

OH

difference between the I

LOOP(min)

and ISH-.

Substituting Equation 8

deﬁnes ROH in

OH

(EQ. 9)

Equation 10 can be used to determine the actual ISH- value resulting from the R

resistor selected. The value of R

D

should be the next standard value that is lower than that calculated. This will insure meeting the I

LOOP(min)

requirement. ROH for the above example equals 39.1kΩ.

R

500

----------------------------------------------------------- -

ROH=

RDI

LOOP(min)

D

- 500(.6)

(EQ. 10)

The current limit is set by a single resistor and is calculated using Equation 11.

1000

-----------------------------

R

=

LIM

I

LOOP(max)

DC FEED CURVE

V

BH

V

SAT

TIP TO RING VOLTAGE

2.5V

R

LOOP(MAX)

LOOP CURRENT

I

LOOP(min)

overhead voltage. If R

V

OH(off)

LOOP(MAX)

The maximum loop resistance is calculated using Equation 12. The resistance of the protection resistors (2R

) is subtracted out

P

to obtain the maximum loop length to meet the required off hook

meets the loop length

(EQ. 11)

requirements you are done. If the loop length needs to be longer, then consider adjusting one of the following: 1) the SHD threshold, 2) minimum loop current requirement or 3) the on and off hook signal levels.

2V V

R

LOOP(max)

V

BHVSAT

-------------------------------------------------------------------------------

=

++[]–

I

LOOP(min)

OH off()

-2R

P

(EQ. 12)

SLIC in the Active Mode

Figure 17 shows a simpliﬁed AC transmission model. Circuit analysis yields the following design equations:

VA= IM2R

I

M

-------

V

A

Z

2

1

--------- -

S

80k

–()=

TR2RP

200× Z

–()× 5××

TR2RP

(EQ. 13)

(EQ. 14)

Node Equation

V

RX

------------ -

500k

-

V

A

------------ -

500k

=I

X

(EQ. 15)

Substitute Equation 14 into Equation 15

V

RX

------------ -

500k

-

-----------------------------------------

I

=

X

Loop Equation

500k - VTX′ +IX500k = 0

I

X

–()

I

MZTR2RP

1000k

(EQ. 16)

(EQ. 17)

Substitute Equation 16 into Equation 17

V

′ 2VRXIMZTR2RP–()–=

TX

Loop Equation V

TR-IM2RP+VTX

′ = 0

(EQ. 18)

(EQ. 19)

Substitute Equation 18 into Equation 19

V

TRIMZTR2VRX

Substituting -V to solve for V



1

V



TR



–=

TR/ZL

TR

Z

TR

---------- -+

=

Z

L

into Equation 20 for IMand rearranging

results in Equation 21

2– V

RX

(EQ. 20)

(EQ. 21)

where: VRX = The input voltage at the VRX pin.

= An internal node voltage that is a function of the loop

V

A

current detector and the impedance matching networks. I

= Internal current in the SLIC that is the difference

X

between the input receive current and the feedback current. I

= The AC metallic current.

M

= A protection resistor (typical 30Ω).

R

P

= An external resistor/network for matching the line

Z

T

impedance. V

´= The tip to ring voltage at the output pins of the SLIC.

TX

= The tip to ring voltage including the voltage across the

V

TR

protection resistors. Z

= The line impedance.

L

= The input impedance of the SLIC including the

Z

TR

protection resistors.

(AC) 4-Wire to 2-Wire Gain

The 4-wire to 2-wire gain is equal to VTR/VRX. From Equation 21 and the relationship ZT= 200(ZTR-2RP).

V

TR

-----------

G

=

4-2

V

RX

Notice that the phase of the 4-wire to 2-wire signal is 180 out of phase with the input signal.

=-2

Z

L

-------------------------

ZL+Z

TR

Z

----------------------------------------------

–=

2

Z

L

Z

T



--------- - 2RP+

+

L



200

(EQ. 22)

o

4-16

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

I

X

+

-

I

M

+

TIP

-

I

M

+

E

-

Z

TR

Z

L

+

V

TR

-

G

RING

-

R

P

-

VTX´

+

I

+

M

-

R

P

500K

R

S

INT

-

INT

I

X

20Ω

-

+

UniSLIC14

+

-

1/80K

I

Z

= 200 (ZTR - 2RP)

T

500K

I

X

5

500K

VA = IM(ZTR-2RP)

20Ω

R

20Ω

R

S

+

500K

I

X

500K

2

A = 1

+

500K

V

TX

PTG

V

RX

+

V

TX

-

+

V

RX

-

FIGURE 17. SIMPLIFIED AC TRANSMISSION CIRCUIT

(AC) 2-Wire to 4-Wire Gain

The 2-wire to 4-wire gain is equal to VTX/EG with VRX = 0

Loop Equation

E–GZLIM2RPIMVTX′–++ 0=

From Equation 18 with V

′ IMZTR2RP–()–=

V

TX

RX

= 0

Substituting Equation 24 into Equation 23 and simplifying.

E

GIMZLZTR

+()=

By design, VTX = -VTX´, therefore

I

V

TX

----------

--------------------------------------- -

=

G

2-4

E

G

–()

MZTR2RP

I

+()

MZLZTR

ZTR2RP–()

---------------------------------=

+()

Z

LZTR

A more useful form of the equation is rewritten in terms of V

TX/VTR

from E

V

TR

Rearranging Equation 27 in terms of E

. A voltage divider equation is written to convert

to VTR as shown in Equation 27.

G

Z



TR

------------------------

=



ZTRZL+



E

G

, and substituting

G

into Equation 26 results in an equation for 2-wire to 4-wire gain that’s a function of the synthesized input impedance of the SLIC (Z

=

G

2-4

) and the protection resistors (RP).

TR

Z

V

TX

---------- -

V

TR

-----------------------------

=

Z

-2R

TR

P

(EQ. 23)

(EQ. 24)

(EQ. 25)

(EQ. 26)

(EQ. 27)

(EQ. 28)

Notice that the phase of the 2-wire to 4-wire signal is in phase with the input signal.

(AC) 4-Wire to 4-Wire Gain

The 4-wire to 4-wire gain is equal to VTX/VRX, EG = 0. From Equation 18.

VTX′ V–

TX

Substituting -V

2– V

RXIMZTR2RP

into Equation 29 for IMresults in

TR/ZL

–()+==

(EQ. 29)

Equation 30.

V

TX

VTRZTR2RP–()

2– V

---------------------------------------------–=

RX

Z

L

(EQ. 30)

Substituting Equation 21 for VTR in Equation 30 and simplifying results in Equation 31.

G

44–

V

TX

==

----------- 2–

V

RX

ZL+2R

  

------------------------

ZLZTR+

P

(EQ. 31)

(AC) 2-Wire Impedance

The AC 2-wire impedance (ZTR) is the impedance looking into the SLIC, including the fuse resistors. The formula to calculate the proper Z shown in Equation 32.

ZT200 ZTR2RP–()•=

Equation 32 can now be used to match the SLIC’s impedance to any known line impedance (Z

formatching the 2-wire impedance is

T

(EQ. 32)

).

TR

4-17

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

EXAMPLE:

Calculate Z R

= 30Ω.

P

ZT200 600

= 114kΩ in series with 0.0108µF.

Z

T

to make ZTR = 600Ω in series with 2.16µF.

T



=



1

----------------------------------- 2()30()–+ jω2.16X10

6–

(EQ. 33)

Note: Some impedance models, with a series capacitor, will cause the op-amp feedback to behave as an open circuit DC. A resistor with a value of about 10 times the reactance of the Z

capacitor (2.16µF/200 = 10.8nF) at the low

T

frequency of interest (200Hz for example) can be placed in parallel with the capacitor in order to solve the problem (736kΩ for a 10.8nF capacitor).

Calculating Tip and Ring Voltages

The on hook tip to ground voltage is calculated using Equation 34. The minus 1.0 volt results from the SLIC self programming. ISH- is the maximum loop current for a constant on hook overhead voltage (ISH- = I the value of R

is calculated in Equation 4.

SAT(off)

On hook Tip Voltage

R

SAToff



V

TIP onhook()

+=

1.0V– ISH-()–

----------------------



2

SHD

(0.6)) and

(EQ. 34)

Off hook Ring Voltage in Current Limit

V

RING CL()VTIP offhook()ILOOP MAX()RL

– 0.2V–=

(EQ. 37)

The off hook ring to ground voltage (not in current limit) is calculated using Equation 38. The 1.5V results from the SLIC self programming. I

LOOP(min)

current allowed by the design and the value of R

is the minimum loop

SAT(off)

calculated in Equation 4. Off hook Ring Voltage not in Current Limit

R

SAT off()



V

RING NCL()VBH

I

LOOP MIN()RP

×–

++=

1.5V I

()

LOOP min()

--------------------------



2

(EQ. 38)

Layout Considerations

Systems with Dual Supplies (VBH and VBL)

If the VBL supply is not derived from the VBH supply, it is recommended that an additional diode be placed in series with the V on pin 8 of the device and cathode to the external supply. This external diode will inhibit large currents and potential damage to the SLIC, in the event the V to GND. If V required.

supply. The orientation of this diode is anode

BH

supply is shorted

is derived from VBH then this diode is not

BL

BH

is

The off hook tip to ground voltage is calculated using Equation 35. I

LOOP(min)

allowedby the design andthe valueof R

is the minimum loop current

SAT(off)

is calculated

in Equation 4. Off hook Tip Voltage

R

SAT off()

V

TIP offhook()

I

LOOP MAX()RP

1V– I

()

–=

LOOP min()

×–

--------------------------

2

(EQ. 35)

The on hook ring to ground voltage is calculated using Equation 36. The 1.5 volt results from the SLIC self programming. ISH- is the maximum loop current for a constant on hook overhead voltage (ISH- = I the value of R

is calculated in Equation 4.

SAT(off)

SHD

(0.6)) and

On hook Ring Voltage

R

SAT off()



V

RING onhook()VBH

1.5V ISH()

++=

--------------------------



2

(EQ. 36)

The calculation of the ring voltage with respect to ground in the off hook condition is dependent upon whether the SLIC is in current limit or not.

The off hook ring to ground voltage (in current limit) is calculated using Equation 37. I current limit and R

is the load resistance across tip and

L

is the programmed loop

LIM

ring. The minus 0.2V is a correction factor forthe 60kΩ slope in Figure 15.

Floating the PTG Pin

The PTG pin is a high impedance pin (500kΩ) that is used to program the 2-wire to 4-wire gain to either 0dB or -6dB.

If 0dB is required, it is necessary to ﬂoat the PTG pin. The PC board interconnect should be as short as possible to minimize stray capacitance on this pin. Stray capacitance on this pin forms a low pass ﬁlter and will cause the 2-wire to 4-wire gain to roll off at the higher frequencies.

If a 2-wire to 4-wire gain of -6dB is required, the PTG pin should be grounded as close to the device as possible.

SPM Pin

For optimum performance, the PC board interconnect the SPM pin should be as short as possible. If pulses metering is not being used, then this pin should be grounded as close to the device pin as possible.

RLIM Pin

The current limiting resistor R RLIM pin as possible.

needs to be as close to the

LIM

Layout of the 2-Wire Impedance Matching Resistor Z

Proper connection to the ZT pin is to have the external Z network as close to the device pin as possible.

The ZT pin is a high impedance pin that is used to set the proper feedback for matching the impedance of the 2-wire side. This will eliminate circuit board capacitance on this pin to maintain the 2-wire return loss across frequency.

T

4-18

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

TABLE 1. DETECTOR STATES

OUTPUT

STATE C3 C2 C1 SLIC OPERATING STATE ACTIVE DETECTOR

0 0 0 0 Open Circuit State 4 wire loopback test capability HIGH HIGH 1 0 0 1 Ringing State

(Previous State cannot be Reverse Active State)

2 0 1 0 Forward Active State Loop Current Detector

Ring Trip Detector HIGH

Ground Key Detector

SHD GKD_ LVM

3 0 1 1 Test Active State

Requires previous state to be in the ForwardActivestate to determine the On hook or Off hook status ofthe line.

4 1 0 0 Tip Open - Ground Start State Ground Key Detector 5 1 0 1 Reserved Reserved N/A N/A

6 1 1 0 Reverse Active State Loop Current Detector

7 1 1 1 Test Reversal Active State

Requires previous state to be in the ReverseActivestatetodeterminethe On hook or Off hook status ofthe line.

8 X X X Thermal Shutdown LOW LOW

Digital Logic Inputs

Table 1 is the logic truth table for the 3V to 5V logic input pins. A combination of the control pins C3, C2 and C1 select 1 of the possible 6 operating states. The 8th state listed is Thermal Shutdown.Thermal Shutdown protection is invoked if a fault condition on the tip or ring causes the junction temperature of the die to exceed 175 each operating state and the control logic follows:

Open Circuit State (C3 = 0, C2 = 0, C1 = 0)

In this state, the tip and ring outputs are in a high impedance condition (>1MΩ). No supervisory functions are available and

SHD and GKD outputs are at a TTL high level.

4-wire loopback testing can be performed in this state. With the PTG pin ﬂoating,the signal on the V of phase and approximately 2 times the V the PTG pin is grounded, then the amplitude will be approximately the same as its input and 180

Ringing State (C3 = 0, C2 = 0, C1 = 1)

In this state, the output of the ring relay driver pin (RRLY) goes low (energizing the ring relay to connect the ringing signal to the phone) if either of the following two conditions are satisﬁed:

o

C. A description of

output is 180oout

TX

input signal. If

RX

o

out of phase.

On Hook Loopback Detector LOW Ground Key Detector HIGH Off Hook Loop Current Detector LOW Line Voltage Detector

Ground Key Detector

On Hook Loop Current Detector HIGH Off Hook Loop Current Detector LOW

Line Voltage Detector

(1) The RSYNC_REV pin is grounded through a resistor -

This connection enables the RRLY pin to go low the instant the ringing state is invoked,without anyregard forthe ringing voltage (90V

RMS

-120V

) across the relay contacts. The

RMS

resistor (34.8kΩ to 70kΩ) is required to limit the current into the RSYNC_REV pin.

(2) A ring sync pulse is applied to the RSYNC_REV pin -

This connection enables the RRLY pin to go low at the command of a ring sync pulse. A ring sync pulse should go low at zero voltage crossing of the ring signal. This pulse should have a rise and fall time <400µs and a minimum pulse width of 2ms.

Zero ring current detection is performed automatically inside the SLIC. This feature de-energizes the ring relay slightly before zero current occurs to partially compensate for the delay in the opening of the relay.

The

SHD output will go low when the subscriber goes off

hook. Once

SHD is activated, an internal latch will prohibit the re-ringing of the line until the ringing code is removed and then reapplied.

The state prior to ringing the phone, can not be the Reverse Active State. In the reverse active state the polarity of the voltageon the CRT_REV_

LVM capacitor, will make it appear as if the subscriber is off hook. This subsequently will activate an internal latch prohibiting the ringing of the line.

4-19

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

The GKD_LVM output is disabled (TTL high level) during the ringing state. Reference the Section titled “Ringing the Phone” for more information.

Forward Active State (C3 = 0, C2 = 1, C1 = 0)

In this state, the SLIC is fully functional. The tip voltage is more positive than the ring voltage. The tip and ring output voltages are an unbalanced DC feed, reference Figure 13. Both and

GKD supervisory functions are active. Reference the

section titled “DC Feed Curve” for more inf ormation.

SHD

Test Active State (C3 = 0, C2 = 1, C1 = 1)

Proper operation of the Test Active State requires the previous state be the Forward Active state to determine the on hook or off hook status of the line. In this state, the SLIC can perform two different tests.

If the subscriber is on hook when the state is entered, a loopback test is performed by s witching an internal 600Ω resistor between tip and ring. The current flows through the internal 600Ω is unidirectional via blocking diodes. (Cannot be used in reverse.) When the loopbac k current flo ws , the output will go low and remain there until the state is exited.This is intended to be a short test since the ability to detect subscriber off hook is lost during loopback testing. Reference the section titled “Loopback Tests” for more information.

If the subscriber is off hook when the state is entered, a Line V oltage Measurement test is perf ormed. The output of the GKD_LVM pin is a pulse train. The pulse width of the active low portion of the signal is proportional to the voltage across the tip and ring pins. If the loop length is such that the SLIC is operatingin constantcurrent, the tip to ring voltage canbe used to determine the length of the line under test. The longer the line, the larger the tip to ring voltage and the wider the pulse. This relationship can determine the length of the line for setting gains in the system. Reference the section titled “Operation of Line V oltageMeasurement” for more information.

SHD

Tip Open State (C3 = 1, C2 = 0, C1 = 0)

In this state, the tip output is in a high impedance state (>250kΩ) and the ring output is capable of full operation, i.e. has full longitudinal current capability. The Tip Open/Ground Start state is used to interface to a PBX incoming 2-wire trunk line. When a ground is applied through a resistor to the ring lead, this current is detected and presented as a TTL logic low on the

SHD and GKD_LVM output pins.

Reserved (C3 = 1, C2 = 0, C1 = 1)

This state is undeﬁned and reserved for future use.

Reverse Active State (C3 = 1, C2 = 1, C1 = 0)

In this state, the SLIC is fully functional. The ring voltage is more positive than the tip voltage. The tip and ring output voltages are an unbalanced DC feed, reference Figure 13. The polarity reversal time is determined by the RC time constant of the RSYNC_REV resistor and the CRT_REV_

LVM capacitor.Capacitor CRT_REV_LVM

performs three different functions: Ring trip filtering, polarity reversal time and line v oltage measurement. It is recommended that programming of the rev ersal time be accomplished by changing the value of RSYNC_REV resistor (see Figure 18). The value of RSYNC_REV resistor is limited between 34.8K (10ms) and 73.2k (21ms). Equation 39 gives the formula for programming the reversal time.

RSYNC REV– 3.47kΩ ReversalTime ms()×=

Both

SHD and GKD supervisory functions are active. Reference the section titled “Polarity Reversal” for more information.

(EQ. 39)

Test Reversal Active State (C3 = 1, C2 = 1, C1 = 1)

Proper operation of the Test Reversal Active State requires the previous state be the Reverse Active state to determine the on hook or off hook status of the line.

If the subscriber is on hook when the state is entered, the SLIC’s tip and ring voltages are the same as the Reverse Activestate. The goes off hook and the level high). (Note: operation is the same as the Reverse Active state with the GKD_LVM output disabled.)

If the subscriber is off hook when the state is entered, a Line Voltage Measurement test is performed.

The output of the ofthe active lowportion ofthe signal isproportional tothe voltage across the tip and ring pins. If the loop length is such that the SLIC is operatingin constantcurrent mode,the tip to ring voltage can be used to determine the length of the line under test. The longer the line, the larger the tip to ring voltage and the wider the pulse. This relationship can determine the length of the line for setting gains in the system. Reference the section titled “Operation of

SHD output will go low when the subscriber

GKD_LVM output is disabled (TTL

GKD_LVM pin is a pulse train.The pulse width

Line Voltage Measurement” for more information.

Thermal Shutdown

The UniSLIC14’sthermal shutdown protection is invoked if a fault condition causes the junction temperature of the die to exceed about 175 both detector outputs go low ( of two things can happen.

For marginal faults where loop current is ﬂowing during the time of the over-temperature condition, foldback loop current limiting reduces the loop current by reducing the tip to ring voltage. An equilibrium condition will exist that maintains the junction temperature at about 175 is removed.

For short circuit faults (tip or ring to ground, or to a supply, etc.) that result in an over-temperature condition, the foldback current limiting will try to maintain an equilibrium at about 175 device will thermally shutdown and disconnect tip and ring until the junction temperature falls to approximately 150

o

C. Once the thermal limit is exceeded,

SHD and GKD_LVM) and one

o

C until the fault condition

C. If the junction temperature keeps rising, the

o

C.

4-20

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Supervisory Functions

Switch Hook Detect Threshold

The Switch Hook Detect Threshold is programmed with a single external resistor (R

). The output of the SHD pin goes

D

low when an off hook condition is detected.

Ground Key Detect Threshold

The Ground Key Detect Threshold is set internally and is not user programmable.

Ringing the Phone

The UniSLIC14 family handles all the popular ringing formats with high or low side ring trip detection. High side detection is possible because of the high common mode range on the ring signal detect input pins (DT, DR). To minimize power drain from the ring generator, when the phone is not being rung, the sense resistors are typically 2MΩ. This reduces the current draw from the ring generator to just a few microamps.

When the subscriber goes off hook during ringing, the UniSLIC14 family automatically releases the ring relay and DC feed is applied to the loop. The UniSLIC14 family has very low power dissipation in the on hook active mode. This enables the SLIC (during the ring cadence) to be powered up in the active state, avoiding unnecessary powering up and down of the SLIC. The control logic is designed to facilitate easy implementation of the ring cadence, requiring only one bit change to go from active to ringing and back again.

DT, DR AND RRLY INPUTS

Ring trip detection will occur when the DR pin goes more positive than DT by approximately 4V.

The ring relay driver pin, RRLY, has an internal clamp between it’s output and ground. This eliminates the need to place an external snubber diode across the ring relay.

Reducing Impulse Noise During Ringing

With an increase in digital data lines being installed next to analog lines, the threat from impulse noise on analog lines is increasing. Impulse noise can cause large blocks of high speed data to be lost, defeating most error correcting techniques. The UniSLIC14 family has the capability to reduce impulse noise by closing the ring relay at zero voltage and opening the ring relay at zero current.

The RSYNC_REV pin is designed to allow the ring sync pulse to be present at all times. There is no need to gate the ring sync pulse on and off. The logic control for the RSYNC_REV pin

cannot be an open collector. It must be high (push-pull logic output stage / pull up resistor to VCC), low or being clocked by the ring sync pulse. When the RSYNC_REV pin is high the ring relaypin is disabled. When the RSYNC_REV pin is low the ring relay pin is activated the instant the logic code for ringing is applied.

OPENING THE RING RELAY AT ZERO CURRENT

The ring relay is automatically opened at zero current by the SLIC. The SLIC logic requires zero ringing current in the loop and either a valid switch hook detect (

SHD) or a change in the operating mode (cadence of the ringing signal) to release the ring relay.

UniSLIC14

R

1

50kΩ

RSYNC_REV

FIGURE 18. REDUCING IMPULSE NOISE USING THE

24

RSYNC_REV PIN AND SETTING THE POLARITY REVERSAL TIME

If the subscriber goes off hook during ringing, the output will go low. An internal latch will sense

INPUT FOR THE RING SYNC PULSE

5V

0V

SHD

SHD is low and disable the ring relay at zero ringing current. This prevents the ring signal from being reapplied to the line. To ring the line again, the SLIC musttoggle between logic states. (Note: The previous state can not be the Reverse Active State. In the reverse state, the voltage on the CRT_REV_

LVM capacitor will activate an internal latch prohibiting the ringing of the line.

Figure 19 shows the sequence of events from ringing the phone to ring trip. The ring relay turns on when both the ringing code and ring sync pulse are present (A).

SHD is high at this point. When the subscriber goes off hook the SHD pin goes low and stays low until the ringing control code is removed (B). This prevents the

SHD output from pulsing after ring trip occurs. At the next zero current crossing of the ring signal, ring trip occurs and the ring relay releases the line to allow loop current to ﬂow in the loop (C).

CLOSING THE RING RELAY AT ZERO VOLTAGE

Closing the ring relay at zero voltage is accomplished by providing a ring sync pulse to the RSYNC_REV pin. The ring sync pulse is synchronized to go low at the zero voltage crossing of the ring signal. The resistor R1 in Figure 18 limits the current into the RSYNC_REV pin. If a particular polarity reversal time is required, then make R1 equal to the calculated valuein Equation 39. If a speciﬁc polarity reversal time is not desired, R1 equal to 50kΩ is suggested.

4-21

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

RINGING VOLTAGE

RING SYNC

PULSE

RINGING CODE

APPLIED

SHD OUTPUT

RINGING CURRENT

IN LINE

RELAY DRIVER

FIGURE 19. RINGING SEQUENCE

(A)

(B)

(C)

OFF ON OFF

Operation of Line Voltage Measurement

A few of the SLICs in the UniSLIC14 family feature Line Voltage Measurement (LVM) capability.This feature provides a pulse on the the loop voltage. Knowing the loop voltage and thus the loop length, other basic cable characteristics such as attenuation and capacitance can be inferred. Decisions can be made about gain switching in the CODEC to overcome line losses and veriﬁcation of the 2-wire circuit integrity.

The LVM function can only be activated in the off hook condition in either the forward or reverse operating states. The LVM uses the ring signal supplied to the SLIC as a timebase generator. The loop resistance is determined by monitoring the pulse width of the output signal on the GKD_LVM pin. The output signal on the GKD_LVM pin is a square wave for which the average duration of the low state is proportional to the average voltage between the tip and ring terminals. The loop resistance is determined by the tip to ring voltage and the constant loop current. Reference Figure 20.

Although the logic state changes to the Test Active State when performing this test, the SLIC is still powered up in the active state (forward or reverse) and the subscriber is unaware the measurement is being taken.

FIGURE 20. OPERATION OF THE LINE VOLTAGE

GKD_LVM output pin that is proportional to

UniSLIC14

TIP

RING

GKD_LVM

DR

DT

RING

GEN

MEASUREMENT CIRCUIT

PULSE WIDTH PROPORTIONAL TO

LOOP LENGTH

PULSE

WIDTH

LOOP LENGTH

RING

GEN

FREQ

Polarity Reversal

Most of the SLICs in the UniSLIC14 family feature full polarity reversal. Full polarity reversal means that the SLIC can: transmit, determine the status of the line (on hook and off hook) and provide “silent” polarity reversal. The value of RSYNC_REV resistor is limited between 34.8k (10ms) and

73.2k (21ms). Reference Equation 39 to program the polarity reversal time.

Transhybrid Balance

If a low cost CODEC is chosen that does not have a transmit op-amp, the UniSLIC14 family of SLICs can solve this problem without the need for an additional op-amp. The solution is to use the Programmable Transmit Gain pin (PTG) as an input for the receive signal (V

). When the PTG pin is

RX

connected to a divider network (R1 and R2 Figure 21) and the value of R1 and R2 is much less than the internal 500kΩ resistors, two things happen. First the transmit gain from V

RX

to VTXis reduced by half. This is the result of shorting out the bottom 500kΩ resistor with the much smaller external resistor. And second, the input signal from V

is also decreased in

RX

half by resistors R1 and R2. Transhybridbalance occurs when these two, equal but opposite in phase, signals are cancelled at the input to the output buffer.

V

-

I

500K

X

+

A = 1

500K

UniSLIC14

500K

I

X

500K

5

FIGURE 21. TRANSHYBRID BALANCE USING THE PTG PIN

TX

PTG

R1 R2

V

RX

-

V

TX

+

V

RX

-

Loopback Tests

4-Wire Loopback Test

This feature can be very useful in the testing of line cards during the manufacturing process and in ﬁeld use. The test is unobtrusive, allowing it to be used in live systems. Reference Figure 22.

Most systems do not provide 4-wire loopback test capability because of costly relays needed to switch in external loads. All the SLICs in the UniSLIC14 family can easily provide this function when configured in the Open Circuit logic state. With the PTG pin floating, the signal on the V times the V the amplitude will be approximately the same as the input signal and 180

output is 180o out of phase and approximately 2

TX

input signal. If the PTG pin is grounded, then

RX

o

out of phase.

4-22

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

TIP

RING

2-WIRE LOOPBACK

FIGURE 22. 4-WIRE AND 2-WIRE LOOPBACK TESTS

UniSLIC14

INTERNAL 600Ω

V

TX

PTG

V

RX

4-WIRE LOOPBACK

-

+

DUAL SUPPLY

CODEC/FILTER

2-Wire Loopback Test

Most of the SLICs in the UniSLIC14 family feature 2-Wire loopback testing. This loopback function is only activated when the subscriber is on hook and the logic command to the SLIC is in the Test Active State. (Note: if the subscriber is off hook and in the Test Active State, the function performed is the Line Voltage Measurement.)

During the 2-wire loopback test, a 2kΩ internal resistor is switched across the tip and ring terminals of the SLIC. This allows the

SHD function and the 4-wire to 4-wire AC transmission, right up to the subscriber loop, to be tested. Together with the 4-wire loopback test in the Open Circuit logic state, this 2-wire loopback test allows the complete network (including SLIC) to be tested up to the subscriber loop.

Pulse Metering

The HC55121, HC55142 and the HC55150 are designed to support pulse metering. They offer solutions to the following pulse metering design issues:

1) Providing adequate signal gain and current drive to the subscriber metering equipment to overcome the attenuation of this (12kHz, 16kHz) out of band signal.

2) Attenuating the pulse metering transhybrid signal without severely attenuating the voice band signal to avoid clipping in the CODEC/Filter.

3) Tailoring the overload levels in the SLIC to avoid clipping of the combined voiceband and pulse metering signal.

4) Having the provision of silent polarity reversalas a backup in the case where the loop attenuates the out of band signal too much for it to be detected by the subscriber’s metering equipment.

Adequate Signal Gain

Adequate signal gain and current drive to the subscriber’s metering equipment is made easier by the network shown in Figure 23. The pulse metering signal is supplied to a dedicated high impedance input pin called SPM. The circuit in Figure 23 shows the connection of a network that sets the 2-wire impedance (Z to be approximately 200Ω.If the line impedance (Z to 200Ω at the pulse metering frequencies, then the 4-Wire

), at the pulse metering frequencies,

TR

) is equal

L

to 2-wire gain (V

/ SPM) is equal 4. Thereby lowering the

TR

input signal requirements of the pulse metering signal. Note: The automatic pulse metering 2-wire impedance

matching is independent of the programmed 2-wire impedance matching at voiceband frequencies.

Calculation of the pulse metering gain is achieved by replacing V

/500k in Equation 15 with SPM/125k and

RX

following the same process through to Equation 21. The UniSLIC14 sets the 2-wire input impedance of the SLIC (Z

), including the protection resistors, equal to 200Ω. The

TR

results are shown in Equation 40.

V

TR

-------------

A

=

SPM

=8–

4-2

Z

L

-------------------------

ZL+Z

TR

200

---------------------------

8

– 4–==

200 + 200

(EQ. 40)

Avoiding Clipping in the CODEC/Filter

The amplitude of the returning pulse metering signal is often very large and could easily over drive the input to the CODEC/Filter. By using the same method discussed in section “Transhybrid Balance”, most if not all of the pulse metering signal can be canceled out before it reaches the input to the CODEC/Filter. This connection is shown in Figure 23.

Overload Levels and Silent Polarity Reversal

The pulse metering signal and voice are simultaneously transmitted, and therefore require additional overhead to prevent distortion of the signal. Reference section “Off hook Overhead Voltage” to account for the additional pulse metering signal requirements.

V

-

500K

I

X

500K

1/80K

Z

T

FIGURE 23. PULSE METERING WITH TRANSHYBRID

BALANCE

+

A = 1

I

X

500K

5

SETS 2-WIRE

IMPEDANCE

AT 12-16kHz

EQUAL TO

200Ω

UniSLIC14

125K

Most of the SLICs in the UniSLIC14 family feature full polarity reversal. Full polarity reversal means that the SLIC can: transmit, determine the status of the line (on hook and off hook) and provide “silent” polarity reversal. Reference Equation 39 to program the polarity reversal time.

TX

PTG

R1 R2

VRX= 0

SPM

12/16kHz PULSE METERING INPUT SIGNAL

4-23

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Interface to Dual and Single Supply CODECs

Great care has beentaken to minimize the number ofexternal components required with the UniSLIC14 family while still providing the maximum flexibility. Figures 24A, 24B) shows the connection of the UniSLIC14 to both a dual supply CODEC/Filter and a single supply DSP CODEC/Filter.

To eliminate the DC blocking capacitors between the SLIC and the CODEC/Filter when using a dual supply CODEC/Filter, both the receive and transmit leads of the SLIC are referenced to ground. This leads to a very simple SLIC to CODEC/Filter interface, as shown in Figure 24A.

When using a single supply DSP CODEC/Filter the output and input of the CODEC/Filter are no longer referenced to ground. To achieve maximum voltage swing with a single supply, both the output and input of the CODEC/Filter are referenced to its own V capacitors are once again required. By using the PTG pin of the UniSLIC14 and the externally supplied V of the CODEC/Filter, one of the DC blocking capacitors can be eliminated (Figure 24B).

V

A = 1

V

UniSLIC14

-

+

/2 reference. Thus, DC blocking

CC

TX

RX

FIGURE 24A.

V

OUT

-

+

DUAL SUPPLY

CODEC/FILTER

/2 reference

CC

5V GND

-5V

Power Sharing

Power sharing is a method of redistributing the power away from the SLIC in short loop applications. The total system power is the same, but the die temperature of the SLIC is much lower. Power sharing becomes important if the application has a single battery supply (-48V on hook requirements for faxes and modems) and the possibility of high loop currents (reference Figure 25). This technique would prevent the SLIC from getting too hot and thermally shutting down on short loops.

The power dissipation in the SLIC is the sum of the smaller quiescent supply power and the much larger power that results from the loop current. The power that results from the loop current is the loop current times the voltage across the SLIC. The power sharing resistor (R across the SLIC, and thereby the on-chip power dissipation. The voltage across the SLIC is reduced by the voltage drop across R

. This occurs because RPS is in series with the

PS

loop current and the negative supply. A mathematical veriﬁcation follows: Given: V

= VBL = -48V, Loop current = 30mA, RL (load

BH

across tip and ring) = 600Ω, Quiescent battery power = (48V) (0.8mA) = 38.4mW, Quiescent VCC power = (5V) (2.7mA) = 13.5mW, Power sharing resistor = 600Ω.

1. Withoutpower sharing, the on-chip power dissipation would be 952mW (Equation 41).

2. Withpower sharing, the on-chip power dissipation is 412mW (Equation 42). A power redistribution of 540mW.

On-chip power dissipation without power sharing resistor.

PD VBH()30mA()38.4mW 13.5mW RL()30mA()

PD 952mW=

) reduces the voltage

PS

–++=

(EQ. 41)

2

V

PTG

V

CODECs

TX

RX

FIGURE 24B.

-

500K

FIGURE 24. INTERFACE TO DUAL AND SINGLE SUPPLY

+

A = 1

UniSLIC14

V

REF

OUT

IN

SINGLE SUPPLY

DSP

CODEC/FILTER

Power Management

The UniSLIC14 family provides two distinct power management capabilities:

Power Sharing and Battery Selection

4-24

5V GND

On-chip powerdissipation with 600Ω power sharing resistor.

PD VBH()30mA()38.4mW 13.5mW++=

RL()30mA()

– RPS()30mA()

PD 412mW=

2

–

2

(EQ. 42)

The design trade-off in using the power sharing resistor is loop length vs on-chip power dissipation.

UniSLIC14

TIP

RING

ON SHORT LOOPS, THE MAJORITY OF CURRENT FLOWS OUT THE V

FIGURE 25. POWER SHARING (SINGLE SUPPLY SYSTEMS)

BL

V

-48V -48V

BL

V

BH

R

PS

V

TX

V

RX

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Battery Selection

Battery selection is a technique, for a two battery supply system, where the SLIC automatically diverts the loop current to the most appropriate supply for a given loop length. This results in signiﬁcant power savings and lowers the total power consumption on short loops. This technique is particularly useful if most of the lines are short, and the on hook condition requires a -48V battery. In Figure 26, it can be seen that for long loops the majority of the current comes from the high battery supply (V the low battery supply (V

BL

) and for short loops from

BH

).

Pinouts - 28 Lead PLCC Packages

HC55120

(28 LEAD PLCC)

TOP VIEW

RRLY

PTG

1234

VTXNCVRX

262728

25 24 23 22 21 20 19

AGND RSYNC ILIM ROH RD V

CC

GKD

RING

BGND

TIP

VBH

VBL

RDC_RAC

CRT

ZT

CH

5 6 7 8

9 10 11

40 35

V

2000

BL

1000

BH

900

800

30 25 20

15 10

LOOP CURRENT (mA)

5 0

600

700

575

550

525

LOOP RESISTANCE (Ω)

VBH = -48V VBL = -24V

RILim = 33.2kΩ

500

475

450

400

350

300

250

V

BL

BH

200

FIGURE 26. BATTERY SELECTION (DUAL SUPPLY SYSTEMS)

HC55121

(28 LEAD PLCC)

TOP VIEW

RRLY

PTG

VTX

SPM

262728

VRX

25

AGND RSYNC_REV

24

ILIM

23

ROH

22

RD

21

V

20

CC

19

GKD

RING

BGND

TIP

VBH

VBL

RDC_RAC

CRT_REV

ZT

CH

1234

5 6 7 8

9 10 11

150

100

RING

BGND

TIP

VBH

VBL

RDC_RAC

CRT

12 13 14 15 16 17 18

DT

CDC

HC55130

(28 LEAD PLCC)

TOP VIEW

ZT

CH

5 6 7 8

9 10 11

12 13 14 15 16 17 18

DT

CDC

4-25

DR

RRLY

DR

C3

PTG

1234

C3

C2

C1

SHD

VTXNCVRX

262728

C2

C1

SHD

25 24 23 22 21 20 19

AGND RSYNC ILIM ROH RD V

CC

NC

RING

BGND

TIP

VBH

VBL

RDC_RAC

CRT_REV_

LVM

12 13 14 15 16 17 18

DT

CDC

(28 LEAD PLCC)

ZT

CH

5 6 7 8

9 10 11

12 13 14 15 16 17 18

DT

CDC

C3

DR

HC55140

TOP VIEW

RRLY

PTG

1234

C3

DR

C2

C1

SHD

VTXNCVRX

262728

C2

C1

SHD

AGND

25

RSYNC_REV

24 23

ILIM

22

ROH

21

RD

20

V

CC

19

GKD_LVM

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Pinouts - 28 Lead PLCC Packages (Continued)

HC55142

(28 LEAD PLCC)

TOP VIEW

RRLY

CH

PTG

1234

ZT

VTX

SPM

262728

VRX

ZT

HC55150

(28 LEAD PLCC)

TOP VIEW

RRLY

PTG

CH

VTX

1234

SPM

VRX

262728

RING

5

BGND

6 7

TIP

8

VBH

9

VBL

LVM

10 11

12 13 14 15 16 17 18

DT

CDC

DR

C3

C2

C1

SHD

RDC_RAC

CRT_REV_

Pinouts - 32 Lead PLCC Packages

HC55120

(32 LEAD PLCC)

TOP VIEW

RRLY

RING

BGND

TIP

VBH

VBL

RDC_RAC

CRT

CDC

DT

C4

1234

PTG

C3

TRLY1

C2

ZT

CH

5 6 7 8

9 10 11 12 13

14 15 16 17 18 19 20

C5

DR

C1

TRLY2

VTX

303132

SHD

25

AGND RSYNC_REV

24

ILIM

23

ROH

22

RD

21

V

20

CC

19

GKD_LVM

NC

29

VRX

28

AGND

27

RSYNC

26

ILIM

25

ROH

24

RD

23

V

22

GKD

21

CC

RING

BGND

VBH

VBL

RDC_RAC

CRT_REV_

LVM

RING

BGND

TIP

VBH

VBL

RDC_RAC

CRT_REV

CDC

DT

TIP

5 6 7 8

9 10 11

12 13 14 15 16 17 18

DT

CDC

DR

C3

C2

C1

SHD

AGND

25

RSYNC_REV

24

ILIM

23

ROH

22

RD

21

V

20

CC

LVM

19

HC55121

(32 LEAD PLCC)

TOP VIEW

RRLY

C4

1234

PTG

C3

TRLY1

C2

ZT

CH

5 6 7 8

9 10 11 12 13

14 15 16 17 18 19 20

C5

DR

TRLY2

C1

303132

VTX

SHD

NC

29

VRX

28

AGND

27

RSYNC_REV

26

ILIM

25

ROH

24

RD

23

V

22

CC

GKD

21

4-26

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Pinouts - 32 Lead PLCC Packages

HC55130

(32 LEAD PLCC)

TOP VIEW

CH

RRLY

ZT

1234

PTG

TRLY1

TRLY2

303132

VTX

ZT

HC55140

(32 LEAD PLCC)

TOP VIEW

RRLY

CH

PTG

1234

TRLY1

TRLY2

VTX

303132

RING

BGND

TIP

VBH

VBL

RDC_RAC

CRT

CDC

RING

BGND

TIP

VBH

VBL

RDC_RAC

CRT_REV_

LVM

CDC

DT

NC

SHD

29 28 27 26 25 24 23 22 21

VRX AGND

RSYNC ILIM ROH RD V

CC

NC

CRT_REV_LVM

5 6 7 8

9 10 11 12 13

14 15 16 17 18 19 20

C3

C2

DR

C5

C4

C1

HC55142

(32 LEAD PLCC)

TOP VIEW

RRLY

C4

1234

PTG

C3

TRLY1

C2

ZT

CH

5 6 7 8 9

10

11 12 13

14 15 16 17 18 19 20

C5

DR

TRLY2

C1

303132

VTX

SHD

SPM

29

VRX

28

AGND

27

RSYNC_REV

26

ILIM

25

ROH

24

RD

23

V

22

CC

GKD_LVM

21

RING

BGND

TIP

VBH

VBL

RDC_RAC

CDC

DT

RING

BGND

TIP

VBH

VBL

RDC_RAC

CRT_REV_

LVM

CDC

DT

5 6 7 8

9 10 11 12 13

14 15 16 17 18 19 20

C3

C2

DR

C5

C4

C1

SHD

HC55150

(32 LEAD PLCC)

TOP VIEW

RRLY

C4

1234

PTG

C3

TRLY1

C2

ZT

CH

5 6 7 8

9 10 11 12 13

14 15 16 17 18 19 20

C5

DR

C1

TRLY2

VTX

303132

SHD

NC

29

VRX

28

AGND

27

RSYNC_REV

26

ILIM

25

ROH

24

RD

23

V

22

CC

GKD_LVM

21

SPM

29

VRX

28

AGND

27

RSYNC_REV

26

ILIM

25

ROH

24

RD

23

V

22

CC

LVM

21

4-27

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Pinouts - 28 Lead SOIC Packages

HC55120

(28 LEAD SOIC)

TOP VIEW

HC55121

(28 LEAD SOIC)

TOP VIEW

ZT

PTG

RRLY

CH

RING

BGND

TIP

VBH

VBL

RDC_RAC

CDC

DT DR

CRT

ZT

PTG

RRLY

CH

RING

BGND

TIP

VBH

VBL

RDC_RAC

CDC

DT DR

CRT

1 2 3 4 5 6 7 8

9 10 11 12 13 14

HC55130

(28 LEAD SOIC)

TOP VIEW

1

2

3

4

5

6

7

8

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AGND VTX NC VRX RSYNC ILIM ROH RD V

CC

SHD C1 C2 C3 GKD

AGND VTX NC VRX RSYNC ILIM ROH RD V

CC

SHD C1 C2 C3 NC

RDC_RAC

CRT_REV

RDC_RAC

CRT_REV_

ZT

PTG

RRLY

CH

RING

BGND

TIP VBH VBL

CDC

DT DR

ZT

PTG

RRLY

CH

RING

BGND

TIP VBH VBL

CDC

DT DR

LVM

1 2 3 4 5 6 7 8

9 10 11 12 13 14

HC55140

(28 LEAD SOIC)

TOP VIEW

1

2

3

4

5

6

7

8

9 10 11 12 13 14

28

AGND VTX

27 26

SPM

25

VRX

24

RSYNC_REV

23

ILIM ROH

22 21

RD

20

V

CC

SHD

19

C1

18

C2

17 16

C3 GKD

15

28

AGND VTX

27

NC

26 25

VRX

24

RSYNC_REV

23

ILIM ROH

22 21

RD

20

V

CC

SHD

19 18

C1

17

C2

16

C3 GKD_LVM

15

4-28

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Pinouts - 28 Lead SOIC Packages (Continued)

HC55142

(28 LEAD SOIC)

TOP VIEW

HC55150

(28 LEAD SOIC)

TOP VIEW

RDC_RAC

CRT_REV_

ZT

PTG

RRLY

CH

RING

BGND

TIP

VBH

VBL

CDC

DT DR

LVM

28

1 2 3 4 5 6 7 8

9 10 11 12 13 14

AGND VTX

27 26

SPM

25

VRX

24

RSYNC_REV

23

ILIM ROH

22 21

RD

20

V

CC

SHD

19 18

C1

17

C2

16

C3 GKD_LVM

15

RDC_RAC

CRT_REV_

ZT

PTG

RRLY

CH

RING

BGND

TIP VBH VBL

CDC

DT DR

LVM

1 2 3 4 5 6 7 8

9 10 11 12 13 14

28

AGND VTX

27 26

SPM

25

VRX

24

RSYNC_REV

23

ILIM ROH

22 21

RD

20

V

CC

SHD

19 18

C1

17

C2

16

C3 LVM

15

Pin Descriptions

28

PLCC

10 10 10 RDC_RAC ResistiveFeed/AntiClipping - Performs anticlipping function on constantcurrent application and sets

11 11 14 CRT_REV

12 12 11 CDC Filter Capacitor- The CDC Capacitor removes the VF signals from the battery feed control loop. 13 13 12 DT Tipside of Ring Trip Detector - Ring trip detection is accomplished by connectingan external network

14 14 13 DR Ring Side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external

32

PLCC

28

SOIC SYMBOL DESCRIPTION

1 1 2 PTG Programmable Transmit Gain - The 2-wire to 4-wire transmission gain is 0dB if this pin is left floating

and -6.02dB if tied to ground. The -6.02dB gain option is useful in systems where Pulse Metering is

used. See Figure 23. 2 2 3 RRLY Ring Relay Driver Output - The relay coil may be connected to a maximum of 14V. 3 3 4 CH AC/DC Separation Capacitor - CH is required to properly process the AC current from the DC loop

current. Recommended value 0.1µF. 4 4 1 ZT 2-Wire Impedance Matching Pin - Impedance matching of the 2-wire side is accomplished by placing

an impedance between the ZT pin and ground. See Equation 32. 5 5 5 RING Connects via protection resistor RP to ring wire of subscriber pair. 6 6 6 BGND Battery ground. 7 7 7 TIP Connects via protection resistor RP to tip wire of subscriber pair. 888 VBHHigh Battery Supply (negative with respect to GND). 999 VBLLow Battery Supply (negative with respect to GND, magnitude ≤ VBH).

the slope of the resistive feed curve for constant voltage applications.

Ring Trip, Soft P olarity Reversal and Line Voltage Measurement - A capacitor when placed betw een the

_LVM

CRT_REV_LVM pinand +5V performs 3 mutually exclusive functions. When theSLIC is configured in the

Ringingmodeitprovidesfiltering of the ringing signal to preventfalsedetect. When the SLIC is transitioning

betweentheForwardActiveStateandReverseActiveStateitprovidesSoft Polarity Reversaland performs

charge storage in the Line V oltage Measurement State . Recommended v alue 0.47µF.

to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DT is more

negative than the voltage on DR.

network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DR is

more positive than the voltage on DT.

- 15 - C5 Activates Test Relay TRLY2.

4-29

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Pin Descriptions (Continued)

28

PLCC

15 17 16 C3 TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the

16 18 17 C2 TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the

17 19 18 C1 TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the

18 20 19 SHD Switch Hook Detect - Active during off hook, ground key and loopback. Reference Table 1 for details. 19 21 15 GKD_LVM Ground Key Detector and Line Voltage Measurement - Reference Table 1 for details. 20 22 20 V 21 23 21 RD Loop Current Threshold Programming Pin - A resistor between this pin and ground will determine the

22 24 22 ROH Off Hook Overload Setting Resistor - Used to set combined overhead for voice and pulse metering

23 25 23 ILIM Current Limit Programming Pin - A resistor between this pin and ground will determine the constant

24 26 24 RSYNC_REV Ring Synchronization Input and Reversal Time Setting. A resistor between this pin and GND

25 27 28 AGND Analog ground 26 28 25 VRX Receive Input - Ground referenced 4-wire side. 27 29 26 SPM Pulse Metering Signal Input. If pulse metering is not used, then this pin should be grounded as close

28 30 27 VTX Transmit Output - Ground referenced 4-wire side.

32

PLCC

- 16 - C4 Activates Test Relay TRLY1.

- 31 - TRLY2 Test Relay Driver 2.

- 32 - TRLY1 Test Relay Driver 1.

28

SOIC SYMBOL DESCRIPTION

SLIC. Reference Table 1 for details.

CC

5V Supply.

trigger level for the loop current detect circuit. See Equation 7.

signals. See Equation 10.

current limit of the feed curve. See Equation 11.

determines the polarity reversal time. Synchronization of the closing of the relay at zero voltage is

achieved via a ring sync pulse (5V to 0V) synchronized to the ring signal zero voltage crossing

(Reference Figure 18).

to the device pin as possible.

4-30

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Basic Application Circuit Voice Only 28 Lead PLCC Package

R

11

CODEC/FILTER

-24V

-48V

+5V OR

+12V

RING

TIP

C

+5V

20

V

C

10 12 13

14 11

4

CC

2

RRLY

3

CH

5

RING

6

BGND

7

TIP

8

VBH

9

VBL

RDC_RAC CDC

DT DR

CRT_REV_

C

U2

1

C

2

C

8

C

9

D

1

C7

R

1

R

C

2

3

R

3

+5V

RELAY

R

P

R

P

OPTIONAL

5

C

6

R

12

RING GENERATOR

VBAT

U1

AGND

RSYNC_REV

GKD_LVM

LVM

V

TX

PTG

SPM

V

RX

ZT

ILIM

ROH

RD

SHD

C1 C2

C3

28

1 27

26

25 4 24 23 22

21

18 19

17 16

15

††C10

R

8

R

7

R

6

R

5

R

4

CONTROL LOGIC

†R

9

†R

††C11

10

† PERFORM TRANSHYBRID BALANCE

WHEN USING A NON-DSP CODEC. NOT REQUIRED FOR DSP CODEC.

†† NOT REQUIRED FOR

NON-DSP CODEC’s. REQUIRED FOR DSP CODEC’s

FIGURE 27. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT

TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT VALUE TOLERANCE RATING

U1 - SLIC UniSLIC14 Family N/A N/A U2 - Dual Asymmetrical Transient Voltage Suppressor TISP1072F3 N/A N/A RP (Line Feed Resistors) 30Ω Matched 1% 2.0W R1 (RDC_RAC Resistor) 21kΩ 1% 1/16W R2, R3 2MΩ 1% 1/16W R4 (RD Resistor) 41.2kΩ 1% 1/16W R5 (ROH Resistor) 38.3kΩ 1% 1/16W R6 (RILIM Resistor) 33.2kΩ 1% 1/16W R7 (RSYNC_REV Resistor) 34.8kΩ 1% 1/16W R8 (RZT Resistor) 107kΩ 1% 1/16W R9, R10, R11 20kΩ 1% 1/16W R12 400Ω 5% 2W C1 (Supply Decoupling), C2 0.1µF 20% 10V C5 (Supply Decoupling) 0.1µF 20% 50V C6 (Supply Decoupling) 0.1µF 20% 100V C4, C7, C10, C11 0.47µF 20% 10V C3 4.7µF 20% 50V C8, C9 2200pF 20% 100V D1,Recommended if the VBL supply isnot derived from the VBH Supply 1N4004 - -

Design Parameters: Maximum on hook voltage = 0.775V

, Maximum Off hook Voice = 3.2V

RMS

, Switch Hook Threshold = 12mA, Loop

PEAK

Current Limit = 31mA, Synthesize Device Impedance = 540Ω (600 - 60), with 30Ω protection resistors, impedance across Tip and Ring terminals = 600Ω. Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

4-31

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Basic Application Circuit Pulse Metering 28 Lead PLCC Package

R

11

CODEC/FILTER

12/16kHz PULSE METERING INPUT SIGNAL

+5V OR

+12V

RING

TIP

-24V

-48V

RING GENERATOR V

BAT

C

+5V

20

V

C

2 3

5

6

7 8

9

10 12

13 14

11

4

CC

RRLY CH

RING

BGND

TIP

VBH

VBL

RDC_RAC CDC

DT DR CRT_REV_

C

U2

1

C

2

C

8

C

9

D

1

C7

R

1

R

C

2

3

R

3

+5V

RELAY

R

P

R

P

5

C

6

R

12

OPTIONAL

U1

AGND

RSYNC_REV

GKD_LVM

LVM

V

TX

PTG

SPM

VRX

ZT

ILIM R

OH

RD

SHD

C1 C2

C3

28 1

27

26

25

4 24 23 22

21

18 19

17 16

15

††C10

††C11

R

8

R

7

R

6

R

5

R

4

CONTROL LOGIC

†R

9

†R

10

† PERFORM TRANSHYBRID BALANCE

WHEN USING A NON-DSP CODEC. NOT REQUIRED FOR DSP CODEC.

†† NOT REQUIRED FOR

NON-DSP CODEC’s. REQUIRED FOR DSP CODEC’s

FIGURE 28. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT

TABLE 3. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT VALUE TOLERANCE RATING

U1 - SLIC UniSLIC14 Family N/A N/A U2 - Dual Asymmetrical Transient Voltage Suppressor TISP1072F3 N/A N/A RP (Line Feed Resistors) 30Ω Matched 1% 2.0W R1 (RDC_RAC Resistor) 26.1kΩ 1% 1/16W R2, R3 2MΩ 1% 1/16W R4 (RD Resistor) 41.2kΩ 1% 1/16W R5 (ROH Resistor) 38.3kΩ 1% 1/16W R6 (RILIM Resistor) 33.2kΩ 1% 1/16W R7 (RSYNC_REV Resistor) 34.8kΩ 1% 1/16W R8 (RZT Resistor) 107kΩ 1% 1/16W R9, R10, R11 20kΩ 1% 1/16W R12 400Ω 5% 2W C1 (Supply Decoupling), C2 0.1µF 20% 10V C5 (Supply Decoupling) 0.1µF 20% 50V C6 (Supply Decoupling) 0.1µF 20% 100V C4, C7, C10, C11 0.47µF 20% 10V C3 4.7µF 20% 50V C8, C9 2200pF 20% 100V D1,Recommended if the VBL supply isnot derived from the VBH Supply 1N4004 - -

Design Parameters: Maximum on hook voltage = 0.775V signal = 2.2V

, Switch Hook Threshold = 12mA, Loop Current Limit = 31mA, Synthesize Device Impedance = 540Ω (600 - 60), with 30Ω

RMS

, Maximum off hook voice = 1.1V

RMS

, Maximum simultaneous pulse metering

PEAK

protection resistors, impedance acrossTip and Ring terminals= 600Ω. Where applicable, these component valuesapply to the BasicApplication Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

4-32

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Basic Application Circuit Voice Only 28 Lead SOIC Package

R

11

CODEC/FILTER

-24V

-48V

+5V OR

+12V

RING

TIP

C

+5V

20

V

C

3 4

8

9

10 11

12 13 14

4

CC

RRLY CH

5

RING

6

BGND

7

TIP

V

BH

V

BL

RDC_RAC CDC

DT DR CRT_REV_

C

U2

1

C

2

C

8

C

9

D

1

C7 R

1

R

C

2

3

R

3

+5V

RELAY

R

P

R

P

OPTIONAL

5

C

6

R

12

RING GENERATOR

V

BAT

U1

AGND

RSYNC_REV

GKD_LVM

LVM

V

SPM

V

RX

ILIM

R

OH

RD

SHD

C1 C2

C3

ZT

TX

27

26 25

28 1 24 23 22 21

19 15 18

17 16

††C10

R

8

R

7

R

6

R

5

R

4

CONTROL LOGIC

†R

9

††C11

†R

10

† PERFORM TRANSHYBRID BALANCE

WHEN USING A NON-DSP CODEC. NOT REQUIRED FOR DSP CODEC.

†† NOT REQUIRED FOR

NON-DSP CODEC’s. REQUIRED FOR DSP CODEC’s

FIGURE 29. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT

TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT VALUE TOLERANCE RATING

U1 - SLIC UniSLIC14 Family N/A N/A U2 - Dual Asymmetrical Transient Voltage Suppressor TISP1072F3 N/A N/A RP (Line Feed Resistors) 30Ω Matched 1% 2.0W R1 (RDC_RAC Resistor) 21kΩ 1% 1/16W R2, R3 2MΩ 1% 1/16W R4 (RD Resistor) 41.2kΩ 1% 1/16W R5 (ROH Resistor) 38.3kΩ 1% 1/16W R6 (RILIM Resistor) 33.2kΩ 1% 1/16W R7 (RSYNC_REV Resistor) 34.8kΩ 1% 1/16W R8 (RZT Resistor) 107kΩ 1% 1/16W R9, R10, R11 20kΩ 1% 1/16W R12 400Ω 5% 2W C1 (Supply Decoupling), C2 0.1µF 20% 10V C5 (Supply Decoupling) 0.1µF 20% 50V C6 (Supply Decoupling) 0.1µF 20% 100V C4, C7, C10, C11 0.47µF 20% 10V C3 4.7µF 20% 50V C8, C9 2200pF 20% 100V D1,Recommended if the VBL supply isnot derived from the VBH Supply 1N4004 - -

Design Parameters: Maximum on hook voltage = 0.775V

, Maximum Off hook Voice = 3.2V

RMS

, Switch Hook Threshold = 12mA, Loop

PEAK

Current Limit = 31mA, Synthesize Device Impedance = 540Ω (600 - 60), with 30Ω protection resistors, impedance across Tip and Ring terminals = 600Ω. Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

4-33

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Basic Application Circuit Pulse Metering 28 Lead SOIC Package

R

11

CODEC/FILTER

12/16KHz PULSE METERING INPUT SIGNAL

RING

-24V

-48V

RING GENERATOR

VBAT

+5V OR

+12V

TIP

C

5

RELAY

C

6

R

12

R

P

R

P

OPTIONAL

U2

R

+5V

20

V

C

1

C

2

C

8

C

9

D

1

C7

R

1

2

C

3

R

3

C

+5V

3 4

5

6

7

8

9

10 11 12

13 14

4

CC

RRLY CH

RING

BGND

TIP

V

BH

V

BL

RDC_RAC CDC

DT DR CRT_REV_

U1

AGND

RSYNC_REV

GKD_LVM

LVM

V

TX

PTG

SPM

V

RX

ZT

ILIM

R

OH

RD

SHD

C1 C2

C3

27

2

26

25

28 1 24 23 22 21

19 15 18

17 16

††C10

††C11

R

8

R

7

R

6

R

5

R

4

CONTROL LOGIC

FIGURE 30. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT

†R

9

†R

10

† PERFORM TRANSHYBRID BALANCE

WHEN USING A NON-DSP CODEC. NOT REQUIRED FOR DSP CODEC.

†† NOT REQUIRED FOR

NON-DSP CODEC’s. REQUIRED FOR DSP CODEC’s

TABLE 5. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT VALUE TOLERANCE RATING

U1 - SLIC UniSLIC14 Family N/A N/A U2 - Dual Asymmetrical Transient Voltage Suppressor TISP1072F3 N/A N/A RP (Line Feed Resistors) 30Ω Matched 1% 2.0W R1 (RDC_RAC Resistor) 26.1kΩ 1% 1/16W R2, R3 2MΩ 1% 1/16W R4 (RD Resistor) 41.2kΩ 1% 1/16W R5 (ROH Resistor) 38.3kΩ 1% 1/16W R6 (RILIM Resistor) 33.2kΩ 1% 1/16W R7 (RSYNC_REV Resistor) 34.8kΩ 1% 1/16W R8 (RZT Resistor) 107kΩ 1% 1/16W R9, R10, R11 20kΩ 1% 1/16W R12 400Ω 5% 2W C1 (Supply Decoupling), C2 0.1µF 20% 10V C5 (Supply Decoupling) 0.1µF 20% 50V C6 (Supply Decoupling) 0.1µF 20% 100V C4, C7, C10, C11 0.47µF 20% 10V C3 4.7µF 20% 50V C8, C9 2200pF 20% 100V D1,Recommended if the VBL supply isnot derived from the VBH Supply 1N4004 - -

Design Parameters: Maximum on hookvoltage = 0.775V = 2.2V

, Switch Hook Threshold = 12mA, Loop Current Limit = 31mA, Synthesize Device Impedance = 540Ω (600 - 60), with 30Ω protection

RMS

, Maximum off hook voice= 1.1V

RMS

, Maximum simultaneous pulse meteringsignal

PEAK

resistors, impedance across Tip and Ring terminals = 600Ω. Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

4-34

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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4-35

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Intersil Corporation HC55151, HC55150, HC55143, HC55142, HC55141 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual