Datasheet HC5515 Datasheet (intersil)

®

www.BDTIC.com/Intersil

HC5515

Data Sheet June 6, 2006

ITU CO/PABX SLIC with Low Power Standby

The HC5515 is a subscriber line interface circuit which is interchangeable with Ericsson’s PBL3860 for distributed central office applications. Enhancements include immunity to circuit latch-up during hot plug and absence of false signaling in the presence of longitudinal currents.

The HC5515 is fabricated in a High Voltage Dielectrically Isolated (DI) Bipolar Process that eliminates leakage currents and device latch-up problems normally associated with junction isolated ICs. The elimination of the leakage currents results in improved circuit performance for wide temperature extremes. The latch free benefit of the DI process guarantees operation under adverse transient conditions. This process feature makes the HC5515 ideally suited for use in harsh outdoor environments.

Ordering Information

PART

NUMBER

HC5515CM HC5515CM 0 to 70 28 Ld PLCC N28.45 HC5515CMZ

(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

HC5515CMZ 0 to 70 28 Ld PLCC

TEMP.

RANGE (°C) PACKAGE

(Pb-free)

PKG.

DWG. #

N28.45

FN4235.6

Features

• DI Monolithic High Voltage Process

• Programmable Current Feed (20mA to 60mA)

• Programmable Loop Current Detector Threshold and Battery Feed Characteristics

• Ring Trip Detection

• Compatible with Ericsson’s PBL3860

• Thermal Shutdown

• On-Hook Transmission

• Wide Battery Voltage Range (-24V to -58V)

• Low Standby Power

• -40°C to 85°C Ambient Temperature Range

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Digital Loop Carrier Systems • Pair Gain

• Fiber-In-The-Loop ONUs • POTS

• Wireless Local Loop • PABX

• Hybrid Fiber Coax

• Related Literature

- AN9632, Operation of the HC5523/15 Evaluation Board

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

www.BDTIC.com/Intersil

HC5515

RINGRLY

DT

DR

TIP

RING

HPT

HPR

V

BAT

V

CC

V

EE

AGND BGND

RING RELAY

RING TRIP

DETECTOR

INTERFACE

BIAS

DRIVER

2-WIRE

LOOP CURRENT

DETECTOR

4-WIRE

INTERFACE VF SIGNAL

PATH

DIGITAL

MULTIPLEXER

V

TX

RSN

E0

C1

C2

DET R

D

R

DC

RSG

2

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Temperature, Humidity

Storage Temperature Range . . . . . . . . . . . . . . . . .-65°C to 150°C

Operating Temperature Range. . . . . . . . . . . . . . . .-40°C to 110°C

Operating Junction Temperature Range . . . . . . . .-40°C to 150°C

Power Supply (-40°C ≤ T

Supply Voltage V Supply Voltage V Supply Voltage V

Ground

≤ 85°C)

A

to GND . . . . . . . . . . . . . . . . . . . . 0.5V to 7V

CC

to GND. . . . . . . . . . . . . . . . . . . . . -7V to 0.5V

EE

to GND. . . . . . . . . . . . . . . . . . .-80V to 0.5V

BAT

Voltage between AGND and BGND. . . . . . . . . . . . . -0.3V to 0.3V

Relay Driver

Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to 20V

Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

Ring Trip Comparator

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

BAT

to 0V

Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 5mA

≤ 85°C)

A

> 10s . . . . V

REP

> 10s. . . . V

REP

> 10s. . . V

REP

)

CC CC

to +2V

BAT

-20V to +5V

BAT

-40V to +10V

BAT

-70V to +15V

BAT

Digital Inputs, Outputs (C1, C2, E0, DET

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to V

Output Voltage (DET Not Active) . . . . . . . . . . . . . . . . . .0V to V

Output Current (DET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Tipx and Ringx Terminals (-40°C ≤ T

Tipx or Ringx Voltage, Continuous (Referenced to GND)V Tipx or Ringx, Pulse < 10ms, T Tipx or Ringx, Pulse < 10µs, T Tipx or Ringx, Pulse < 250ns, T

Tipx or Ringx Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V

Thermal Resistance (Typical, Note 1) θ

28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . 53

Continuous Power Dissipation at 70°C

28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W

Package Power Dissipation at 70°C, t < 100ms, t

28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W

Derate above. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18.8mW/°C

PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18.8mW/°C

Maximum Junction Temperature Range . . . . . . . . . .-40°C to 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(PLCC - Lead Tips Only)

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . 543 Transistors, 51 Diodes

REP

> 1s

(°C/W)

JA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ

is measured with the component mounted on an evaluation PC board in free air.

JA

Typical Operating Conditions

These represent the conditions under which the part was developed and are suggested as guidelines.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Case Temperature -40 - 100 °C

with Respect to AGND -40°C to 85°C 4.75 - 5.25 V

V

CC

V

with Respect to AGND -40°C to 85°C -5.25 - -4.75 V

EE

with Respect to BGND -40°C to 85°C -58 - -24 V

V

BAT

Electrical Specifications T

PARAMETER CONDITIONS MIN TYP MAX UNITS

Overload Level 1% THD, Z Longitudinal Impedance (Tip/Ring) 0 < f < 100Hz (Note 3, Figure 2) - 20 35 Ω/Wire

TIP 27

R

L

600Ω

I

DCMET

23mA

FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT) FIGURE 2. LONGITUDINAL IMPEDANCE

V

TRO

RING28RSN

= 0°C to 70°C, VCC = +5V ±5%, V

A

= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified.

R

D

= 600Ω, (Note 2, Figure 1) 3.1 - - V

L

V

TX

19

R

T

600kΩ

E

R

RX

16

300kΩ

RX

= -5V ±5%, V

EE

0 < f < 100Hz

1V

= -48V , AGND = BGND = 0V, R

BAT

A

300Ω

T

A

R

LZT = VT/A

RMS

E

L

C

2.16µF

TIP 27

V

T

V

R

RING28RSN

= R

DC1

DC2

V

TX

19

16

T

LZR = VR/A

= 41.2kΩ,

R

T

600kΩ

R

RX

300kΩ

PEAK

R

3

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

Electrical Specifications T

= 0°C to 70°C, VCC = +5V ±5%, V

A

R

= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified.

D

(Continued)

= -5V ±5%, V

EE

= -48V , AGND = BGND = 0V, R

BAT

DC1

= R

DC2

= 41.2kΩ,

PARAMETER CONDITIONS MIN TYP MAX UNITS

LONGITUDINAL CURRENT LIMIT (TIP/RING)

Off-Hook (Active) No False Detections, (Loop Current),

20 - - mA

LB > 45dB (Note 4, Figure 3A)

On-Hook (Standby), R

E

C

L

2.16µF

= ∞ No False Detections (Loop Current) (Note 5,

368Ω

L

A

39kΩ

-5V

A

TIP 27

R

RING28R

RSN

D

DET

16

DC

14

Figure 3B)

R

DC2

41.2kΩ

R

DC1

41.2kΩ

C

DC

1.5µF

5--mA

368Ω

E

L

C2.16µF

368Ω

A

39kΩ

-5V

A

TIP 27

R

D

RING 28

DET

RSN

R

DC

16

14

R

DC2

41.2kΩ

R

DC1

41.2kΩ

C

DC

1.5µF

FIGURE 3A. OFF-HOOK FIGURE 3B. ON-HOOK

FIGURE 3. LONGITUDINAL CURRENT LIMIT

OFF-HOOK LONGITUDINAL BALANCE

Longitudinal to Metallic IEEE 455 - 1985, R

0.2kHz < f < 4.0kHz (Note 6, Figure 4)

Longitudinal to Metallic R

, RLT = 300Ω, 0.2kHz < f < 4.0kHz

LR

(Note 6, Figure 4)

, RLT = 368Ω

LR

Metallic to Longitudinal FCC Part 68, Para 68.310

53 70 - dB

50 55 - dB

0.2kHz < f < 1.0kHz

1.0kHz < f < 4.0kHz (Note 7) 50 55 - dB Longitudinal to 4-Wire 0.2kHz < f < 4.0kHz (Note 8, Figure 4) 53 70 - dB Metallic to Longitudinal R

, RLT = 300Ω, 0.2kHz < f < 4.0kHz

LR

50 55 - dB

(Note 9, Figure 5)

4-Wire to Longitudinal 0.2kHz < f < 4.0kHz (Note 10, Figure 5) 50 55 - dB

PEAK

Wire

PEAK

Wire

/

R

E

L

C

2.16µF

LT

R

LR

TIP 27

V

TR

RING 28

V

TX

RSN

19

16

FIGURE 4. LONGITUDINAL TO METALLIC AND

LONGITUDINAL TO 4-WIRE BALANCE

2-Wire Return Loss C

= 20nF

HP

TIP IDLE VOLTAGE

Active, I Standby, I

= 0 --1.5- V

L

= 0 -<0 - V

L

RING IDLE VOLTAGE

Active, I Standby, I

= 0 - -46.5 - V

L

= 0 ->-48- V

L

4

R

T

600kΩ

R

RX

300kΩ

LT

2.16µF

V

TX

V

L

300Ω

C

R

LR

300Ω

E

TR

TIP 27

RING28RSN

V

TX

19

R

T

600kΩ

E

R

RX

16

300kΩ

RX

FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO

LONGITUDINAL BALANCE

0.2kHz to 0.5kHz (Note 11, Figure 6) 25 - - dB

0.5kHz to 1.0kHz (Note 11, Figure 6) 27 - - dB

1.0kHz to 3.4kHz (Note 11, Figure 6) 23 - - dB

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

Electrical Specifications T

= 0°C to 70°C, VCC = +5V ±5%, V

A

R

= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified.

D

(Continued)

= -5V ±5%, V

EE

= -48V , AGND = BGND = 0V, R

BAT

DC1

= R

DC2

= 41.2kΩ,

PARAMETER CONDITIONS MIN TYP MAX UNITS

TIP-RING Open Loop Metallic Voltage, V

4-WIRE TRANSMIT PORT (V

TX

TR

)

Overload Level Z

V

= -52V, RSG = 0Ω 43 - 47 V

BAT

> 20kΩ, 1% THD (Note 12, Figure 7) 3.1 - - V

L

PEAK

Output Offset Voltage EG = 0, ZL = ∞ (Note 13, Figure 7) -60 - 60 mV Output Impedance (Guaranteed by Design) 0.2kHz < f < 03.4kHz - 5 20 W 2-Wire to 4-Wire (Metallic to V

Z

D

R

V

S

R

LR

FIGURE 6.

) Voltage Gain 0.3kHz < f < 03.4kHz (Note 14, Figure 7) 0.98 1.0 1.02 V/V

TX

2.16µF

TIP 27

V

M

Z

IN

RING28RSN

TWO-WIRE RETURN LOSS FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT),

V

TX

19

16

R

T

600kΩ

R

RX

300kΩ

R

L

600Ω

E

G

C

I

DCMET

23mA

V

TR

TIP27V

RING28RSN

TX

19

16

R

T

600kΩ

R

RX

300kΩ

V V

TXO TX

OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE VOLTAGE GAIN AND HARMONIC DISTORTION

4-WIRE RECEIVE PORT (RSN)

DC Voltage I

Sum Node Impedance (Gtd by Design) 0.2kHz < f < 3.4kHz - - 20 W

R

X

= 0mA - 0 - V

RSN

Current Gain-RSN to Metallic 0.3kHz < f < 3.4kHz (Note 15, Figure 8) 900 1000 1100 Ratio

FREQUENCY RESPONSE (OFF-HOOK)

2-Wire to 4-Wire 0dBm at 1.0kHz, E

0.3kHz < f < 3.4kHz (Note 16, Figure 9) 4-Wire to 2-Wire 0dBm at 1.0kHz, E

0.3kHz < f < 3.4kHz (Note 17, Figure 9) 4-Wire to 4-Wire 0dBm at 1.0kHz, E

0.3kHz < f < 3.4kHz (Note 18, Figure 9)

RX

G

= 0V

-0.2 - 0.2 dB

INSERTION LOSS

2-Wire to 4-Wire 0dBm, 1kHz (Note 19, Figure 9) -0.2 - 0.2 dB 4-Wire to 2-Wire 0dBm, 1kHz (Note 20, Figure 9) -0.2 - 0.2 dB

GAIN TRACKING (Ref = -10dBm, at 1.0kHz)

2-Wire to 4-Wire +3dBm to +7dBm (Note 21, Figure 9) -0.15 - 0.15 dB 2-Wire to 4-Wire -40dBm to +3dBm (Note 21, Figure 9) -0.1 - 0.1 dB 2-Wire to 4-Wire -55dBm to -40dBm (Note 21, Figure 9) -0.2 - 0.2 dB 4-Wire to 2-Wire -40dBm to +7dBm (Note 22, Figure 9) -0.1 - 0.1 dB

Z

L

5

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

Electrical Specifications T

= 0°C to 70°C, VCC = +5V ±5%, V

A

R

= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified.

D

(Continued)

= -5V ±5%, V

EE

= -48V , AGND = BGND = 0V, R

BAT

DC1

= R

DC2

= 41.2kΩ,

PARAMETER CONDITIONS MIN TYP MAX UNITS

4-Wire to 2-Wire -55dBm to -40dBm (Note 22, Figure 9) -0.2 - 0.2 dB

GRX = ((V

Where: V

and V

- V

)(300k))/(-3)(600)

TR2

is the Tip to Ring Voltage with V

TIP 27

V

TR

RING28R

R

600Ω

TR1

TR2

L

RSN

DC

= 0V

RSN

= -3V

RSN

R

RX

300kΩ

16

R

DC2

14

41.2kΩ

R

DC1

41.2kΩ

1.5µF

V

= 0V

RSN

V

= -3V

RSN

600Ω

C

DC

1/ωC < RL

C

V

TR

TIP27V

RING28RSN

R

L

I

DCMET

E

G

TX

19

16

R

T

600kΩ

R

RX

300kΩ

V

TX

E

RX

FIGURE 8. CURRENT GAIN-RSN TO METALLIC FIGURE 9. FREQUENCY RESPONSE, INSERTION LOSS,

GAIN TRACKING AND HARMONIC DISTORTION

NOISE

Idle Channel Noise at 2-Wire C-Message Weighting (Note 23, Figure 10) - 8.5 - dBrnC

Psophometrical Weighting

- -81.5 - dBrnp

(Note 23, Figure 10)

Idle Channel Noise at 4-Wire C-Message Weighting (Note 24, Figure 10) - 8.5 - dBrnC

Psophometrical Weighting

- -81.5 - dBrnp

(Note 23, Figure 10)

HARMONIC DISTORTION

2-Wire to 4-Wire 0dBm, 1kHz (Note 25, Figure 7) - -65 -54 dB 4-Wire to 2-Wire 0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 9) - -65 -54 dB

BATTERY FEED CHARACTERISTICS

Constant Loop Current Tolerance R

DCX

= 41.2kΩ

Loop Current Tolerance (Standby) I

Open Circuit Voltage (V

TIP

- V

) -40°C to 85°C, (Active) RSG = ∞ 14 16.67 20 V

RING

= 2500/(R

I

L

-40°C to 85°C (Note 27)

= (V

L

BAT

-40°C

to 85°C (Note 28)

+ R

DC1

DC2

-3)/(RL +1800),

),

0.85I

0.75I

L

I

L

I

L

1.15I

1.25I

L

mA

LOOP CURRENT DETECTOR

On-Hook to Off-Hook R Off-Hook to On-Hook R Loop Current Hysteresis R

= 33kΩ, -40°C to 85°C 11 465/R

D

= 33kΩ, -40°C to 85°C 9.5 405/R

D

= 33kΩ, -40°C to 85°C - 60/R

D

D D

D

17.2 mA

15.0 mA

-mA

R

600Ω

TIP27V

L

V

TR V

RING28RSN

TX

19

16

R

T

600kΩ

R

RX

300kΩ

FIGURE 10. IDLE CHANNEL NOISE

6

TX

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

Electrical Specifications T

PARAMETER CONDITIONS MIN TYP MAX UNITS

RING TRIP DETECTOR (DT, DR)

Offset Voltage Source Res = 0 -20 - 20 mV Input Bias Current Source Res = 0 -360 - 360 nA Input Common-Mode Range Source Res = 0 V Input Resistance Source Res = 0, Unbalanced 1 - - MΩ

RING RELAY DRIVER

V

at 25mA IOL = 25mA - 0.2 0.6 V

SAT

Off-State Leakage Current V

DIGITAL INPUTS (E0, C1, C2)

Input Low Voltage, V Input High Voltage, V Input Low Current, I Input Low Current, I Input High Current V

DETECTOR OUTPUT (DET

Output Low Voltage, V Output High Voltage, V Internal Pull-Up Resistor 81525k

POWER DISSIPATION (V

Open Circuit State C1 = C2 = 0 - 26.3 70 mW On-Hook, Standby C1 = C2 = 1 - 37.5 85 mW On-Hook, Active C1 = 0, C2 = 1, R Off-Hook, Active C1 = 0, C2 = 1, R

TEMPERATURE GUARD

Thermal Shutdown 150 - 180 °C

SUPPLY CURRENTS

Open Circuit State (C1, 2 = 0, 0) On-Hook

Standby State (C1, 2 = 1, 1) On-Hook

Active State (C1, 2 = 0, 1) On-Hook

PSRR

V

to 2 or 4-Wire Port (Note 29, Figure 11) - 40 - dB

CC

to 2 or 4-Wire Port (Note 29, Figure 11) - 40 - dB

V

EE

IL

IH

: C1, C2 VIL = 0.4V -200 - - µA

IL

: E0 VIL = 0.4V -100 - - µA

IL

)

OL

OH

BAT

(V

BAT

= 0°C to 70°C, VCC = +5V ±5%, V

A

R

= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified.

D

(Continued)

Source Res = 0, Balanced 3 - - MΩ

OH

IH

IOL = 2mA - - 0.45 V IOH = 100µA2.7--V

= -48V)

= -28V)

I

CC

I

EE

I

BAT

I

CC

I

EE

I

BAT

I

CC

I

EE

I

BAT

= -5V ±5%, V

EE

= 12V - - 10 µA

= 2.4V - - 40 µA

= High Impedance - 110 300 mW

L

= 600Ω -1.11.4W

L

= -48V , AGND = BGND = 0V, R

BAT

+1 - 0 V

BAT

0-0.8V 2-VCCV

-1.32.8mA

-0.62.0mA

- 0.35 1.2 mA

-1.63.5mA

- 0.62 2.0 mA

- 0.55 1.6 mA

-3.79.5mA

-1.14.0mA

-2.25.2mA

DC1

= R

DC2

= 41.2kΩ,

Ω

7

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

Electrical Specifications T

PARAMETER CONDITIONS MIN TYP MAX UNITS

V

to 2 or 4-Wire Port (Note 29, Figure 11) - 40 - dB

BAT

= 0°C to 70°C, VCC = +5V ±5%, V

A

R

= 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified.

D

(Continued)

-48V SUPPLY +5V SUPPL Y

-5V SUPPLY

R

L

600Ω

TIP27V

RING28RSN

FIGURE 11. POWER SUPPLY REJECTION RATIO

100mV

TX

19

16

= -5V ±5%, V

EE

, 50Hz TO 4kHz

RMS

R

T

600kΩ

R

RX

300kΩ

BAT

PSRR = 20 log (V

V

TX

= -48V , AGND = BGND = 0V, R

)

TX/VIN

DC1

= R

Circuit Operation and Design Information

DC2

= 41.2kΩ,

The HC5515 is a current feed voltage sense Subscriber Line Interface Circuit (SLIC). This means that for short loop applications the SLIC provides a programed constant current to the tip and ring terminals while sensing the tip to ring voltage.

The following discussion separates the SLIC’s operation into its DC and AC paths, then follows up with additional circuit and design information.

Constant Loop Current (DC) Path

SLIC in the Active Mode

The DC path establishes a constant loop current that flows out of tip and into the ring terminal. The loop current is programmed by resistors R the R the voltage across R

pin (Figure 12). The RDC voltage is determined by

DC

in the saturation guard circuit. Under

1

constant current feed conditions, the voltage drop across R sets the R flows through R establishes a current (I +R

DC2

voltage to -2.5V. This occurs when current

DC

into the current source I2. The RDC voltage

1

RSN

). This current is then multiplied by 1000, in the loop

current circuit, to become the tip and ring loop currents. For the purpose of the following discussion, the saturation

guard voltage is defined as the maximum tip to ring voltage at which the SLIC can provide a constant current for a given battery and overhead voltage.

, R

DC1

and the voltage on

DC2

) that is equal to V

RDC

/(R

DC1

For loop resistances that result in a tip to ring voltage less than the saturation guard voltage the loop current is defined as:

I

L

R

+

DC1RDC2

where: I R

DC1

= Constant loop current, and

L

and R

DC2

Capacitor CDC between R signals from the battery feed control loop. The value of C

1000×=

= Loop current programming resistors.

DC1

and R

removes the VF

DC2

(EQ. 1)

DC

2.5V

------------------------------------- -

is determined by Equation 2:

DC

×=

⎝⎠

R

DC1

C

1

⎛⎞

T

---------------

---------------+

R

1

DC2

(EQ. 2)

where T = 30ms.

1

NOTE: The minimum CDC value is obtained if R

DC1

= R

DC2

.

Figure 13 illustrates the relationship between the tip to ring voltage and the loop resistance. For a 0Ω loop resistance both tip and ring are at V

/2. As the loop resistance

BAT

increases, so does the voltage differential between tip and ring. When this differential voltage becomes equal to the saturation guard voltage, the operation of the SLIC’s loop feed changes from a constant current feed to a resistive feed. The loop current in the resistive feed region is no longer constant but varies as a function of the loop resistance.

8

FN4235.6

June 6, 2006

I

)

www.BDTIC.com/Intersil

I

RING

TIP

RING

HC5515

+

-

I

TIP

I

RING

-

+

FIGURE 12. DC LOOP CURRENT

LOOP CURRENT

CIRCUIT

SATURATION GUARD

CIRCUIT

A

1

I

1

-5V

V

TX

I

RSN

-

A

2

I

2

-5V

+

R

1

-

17.3kΩ

+

RSN

R

DC

-2.5V

R

SG

-5V

R

RX

R

DC1

C

R

DC2

R

SG

DC

V

= -48V, IL = 23mA, RSG = 4.0kΩ

0

-10

-20

-30

-40

TIP TO RING VOLTAGE (V)

-50

SATURATION

GUARD VOLTAGE

CONSTANT CURRENT

FEED REGION

SATURATION

GUARD VOLTAGE

01.2K

BAT

RESISTIVE FEED

LOOP RESISTANCE (Ω)

FIGURE 13. VTR vs R

REGION

L

V

TIP

V

RING

∞

Figure 14 shows the relationship between the saturation guard voltage, the loop current and the loop resistance. Notice from Figure 14 that for a loop resistance <1.2kΩ (R = 4.0k

Ω) the SLIC is operating in the constant current feed

region and for resistances >1.2kΩ the SLIC is operating in the resistive feed region. Operation in the resistive feed region allows long loop and off-hook transmission by keeping the tip and ring voltages off the rails. Operation in this region is transparent to the customer.

50

40

30

20

10

TIP TO RING VOLTAGE (V)

0

R

L

R

100kΩ

L

V

= -48V, RSG = 4.0kΩ

BAT

V

= -24V, RSG = ∞

BAT

RESISTIVE FEED

REGION

10 20

LOOP CURRENT (mA)

4kΩ

1.5kΩ

FIGURE 14. V

2kΩ 700Ω <400Ω

vs IL and R

TR

CONSTANT CURRENT FEED REGION

SATURATION GUARD VOLTAGE, V

30

<1.2kΩ

RSG = 4.0kΩ100kΩ RSG = ∞Ω

L

TR

= 38V

= 13V

SG

The Saturation Guard circuit (Figure 12) monitors the tip to ring voltage via the transconductance amplifier A

1

. A1 generates a current that is proportional to the tip to ring voltage difference. I1 is internally set to sink all of A1’s current until the tip to ring voltage exceeds 12.5V. When the tip to ring voltage exceeds 12.5V (with no RSG resistor) A1 supplies more current than I

amplifies its input current by a factor of 12 and the current

A

2

through R output current from A voltage across R

becomes the difference between I2 and the

1

2

decreases and the output voltage on RDC

1

can sink. When this happens

1

. As the current from A2 increases, the

decreases. This results in a corresponding decrease in the loop current. The RSG pin provides the ability to increase the saturation guard reference voltage beyond 12.5V. Equation 3 gives the relationship between the RSG resistor value and the programmable saturation guard reference voltage:

5

V

SGREF

12.5

510•

-----------------------------------+=

RSG17300+

(EQ. 3

where: V

= Saturation Guard reference voltage, and

SGREF

RSG = Saturation Guard programming resistor. When the Saturation guard reference voltage is exceeded,

the tip to ring voltage is calculated using Equation 4:

V

TRRL

16.66 5 105• RSG17300+()⁄+

------------------------------------------------------------------------------------

×=

R

LRDC1RDC2

+()600⁄+

(EQ. 4)

where: V

= Voltage differential between tip and ring, and

TR

= Loop resistance.

R

L

For on-hook transmission R

510

•

-----------------------------------+=

16.66

V

TR

The value of R

17300+

R

SG

should be calculated to allow maximum

SG

= ∞, Equation 4 reduces to:

L

5

(EQ. 5)

loop length operation. This requires that the saturation guard reference voltage be set as high as possible without clipping the incoming or outgoing VF signal. A voltage margin of -4V

9

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

on tip and -4V on ring, for a total of -8V margin, is recommended as a general guideline. The value of R

SG

is

calculated using Equation 6:

⎛⎞ ⎜⎟ ⎜⎟

R

---------------------------------------------------------------------------------------------------------------------------------------------- 17300–

=

⎜⎟

SG

⎜⎟ ⎜⎟

V

–()1

BATVMAR

⎝⎠

5105•

R

⎛⎞ ⎜⎟ ⎝⎠

+()

DC1RDC2

----------------------------------------------+

600R

L

16.66V–×

(EQ. 6)

where: V

= Battery voltage, and

BAT

V

= Voltage Margin. Recommended value of -8V to

MAR

allow a maximum overload level of 3.1V

PEAK

.

For on-hook transmission RL = ∞, Equation 6 reduces to:

5

510

----------------------------------------------------------------- - 17300–=

R

SG

V

•

BATVMAR

16.66V––

(EQ. 7)

SLIC in the Standby Mode

Overall system power is saved by confi guring the SLIC in the standby state when not in use. In the standby state the tip and ring amplifiers are disabled and internal resistors are connected between tip to ground and ring to V connection enables a loop current to flow when the phone goes off-hook. The loop current detector then detects this current and the SLIC is configured in the active mode for voice transmission. The loop current in standby state is calculated as follows:

V

--------------------------------

I

≈

L

R

BAT

L

3V–

1800Ω+

BAT

. This

(EQ. 8)

V

= Is the analog ground referenced receive signal,

RX

Z

= Is used to set the 4-wire to 2-wire gain,

RX

E

= Is the AC open circuit voltage, and

G

ZL = Is the line impedance.

(AC) 2-Wire Impedance

The AC 2-wire impedance (ZTR) is the impedance looking into the SLIC, including the fuse resistors, and is calculated as follows:

Let V

TXZT

Z

Substituting in Equation 9 for V

Substituting in Equation 12 for V

Therefore:

Z

Equation 16 can now be used to match the SLIC’s impedance to any known line impedance (Z

= 0. Then from Equation 10:

RX

I

M

------------ -

•=

1000

is defined as:

TR

V

TR

-----------=

TR

I

M

Z

TR

T

V

TX

---------- -

I

M

Z

T

------------ - 2R 1000

1000 ZTR2RF–()•=

•

2R

FIM

-----------------------+=

I

M

+=

F

where: I

= Loop current in the standby state,

L

R

= Loop resistance, and

L

V

= Battery voltage.

BAT

(AC) Transmission Path

Example:

Calculate ZT to make ZTR = 600Ω in series with 2.16µF. R

=20Ω.

F

⎛⎞

Z

T

•=

1000 600

----------------------------------------- 220•–+

⎜⎟ ⎝⎠

jω 2.16• 10

(EQ. 12)

(EQ. 13)

:

TR

(EQ. 14)

:

TX

(EQ. 15)

(EQ. 16)

).

TR

1

6–

•

SLIC in the Active Mode

Figure 15 shows a simplified AC transmission model. Circuit analysis yields the following design equations:

V

TRVTXIM2RF

V

TX

---------- -

RX

-----------+

Z

T

RX

V

TREGIMZL

•+=

I

M

------------ -=

1000

•–=

where: V

= Is the AC metallic voltage between tip and ring,

TR

including the voltage drop across the fuse resistors R VTX = Is the AC metallic voltage. Either at the ground

referenced 4-wire side or the SLIC tip and ring terminals, I

= Is the AC metallic current,

M

R

= Is a fuse resistor,

F

(EQ. 9)

(EQ. 10)

(EQ. 11)

,

F

= 560kΩ in series with 2.16nF.

Z

T

(AC) 2-Wire to 4-Wire Gain

The 2-wire to 4-wire gain is equal to VTX/ VTR. From Equations 9 and 10 with V

V

A

24–

TX

-----------

V

TR

(AC) 4-Wire to 2-Wire Gain

The 4-wire to 2-wire gain is equal to VTR/VRX. From Equations 9, 10 and 11 with E

V

TR

42–

-----------

V

RX

A

ZT = Is used to set the SLIC’s 2-wire impedance,

10

Z

------------------------------------------==

Z

T

Z

-----------–

Z

RX

T

1000⁄ 2RF+

T

•==

= 0:

RX

1000⁄

Z

T

++

L

FZL

--------------------------------------------

------------ - 2R

1000

G

= 0:

(EQ. 17)

(EQ. 18)

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

I

M

TIP

R

F

Z

L

+

Z

+

V

TR

-

TR

+

E

G

-

RING

+

V

TX

-

I

M

R

F

-

HC5515

FIGURE 15. SIMPLIFIED AC TRANSMISSION CIRCUIT

A = 250

V

TX

1

Z

T

A = 4

A = 250

RSN

1000

I

M

+

V

TX

-

Z

RX

+

V

RX

-

For applications where the 2-wire impedance (ZTR, Equation 15) is chosen to equal the line impedance (Z expression for A

Z

A

42–

-----------–

Z

RX

1

T

-- -

•=

2

simplifies to:

4-2

), the

L

(EQ. 19)

(AC) 4-Wire to 4-Wire Gain

The 4-wire to 4-wire gain is equal to VTX/VRX. From Equations 9, 10 and 11 with EG = 0:

Z

V

44–

-----------

V

A

TX RX

Z

T

-----------–

Z

RX

+

L2RF

--------------------------------------------

•==

Z

T

------------ - 2R

++

1000

FZL

(EQ. 20)

Transhybrid Circuit

The purpose of the transhybrid circuit is to remove the receive signal (V an echo on the transmit side. This is accomplished by using an external op amp (usually part of the CODEC) and by the inversion of the signal from the 4-wire receive port (RSN) to the 4-wire transmit port (V circuit. The input signal will be subtracted from the output signal if I

equals I2. Node analysis yields the following equation:

1

V

TX

-----------

R

TX

The value of Z

Z

B

Where VRX/VTX equals 1/ A Therefore:

Z

BRTX

) from the transmit signal (VTX), thereby preventing

RX

). Figure 16 shows the transhybrid

TX

V

RX

-----------+ 0= Z

B

is then:

B

V

RX

-----------

R–

•=

TX

V

TX

.

4-4

Z

T

++

------------ - 2R

•

Z

RX

-----------

Z

T

1000

--------------------------------------------

•= +

Z

L2RF

FZL

(EQ. 21)

(EQ. 22)

(EQ. 23)

Example:

Given: RTX = 20kΩ, ZRX = 280kΩ, ZT = 562kΩ (standard value), R

= 20Ω and Z = 600Ω,

F

The value of ZB = 18.7kΩ

R

FB

I

2

R

TX

I

1

Z

T

Z

RX

Z

B

-

+

V

TX

-

+

V

RX

-

HC5515

V

TX

RSN

CODEC/

FILTER

FIGURE 16. TRANSHYBRID CIRCUIT

Supervisory Functions

The loop current and the ring trip detector outputs are multiplexed to a single logic output pin called DET Table 1 to determine the active detector for a given logic input. For further discussion of the logic circuitry see section titled “Digital Logic Inputs”.

Before proceeding with an explanation of the loop current detector and the longitudinal impedance, it is important to understand the difference between a “metallic” and “longitudinal” loop currents. Figure 17 illustrates 3 different types of loop current encountered.

Case 1 illustrates the metallic loo p cu rre nt . Th e de fi n i ti on of a metallic loop current is when equal currents flow out of tip and into ring. Loop current is a metallic current.

. See

11

FN4235.6

June 6, 2006

)

HC5515

www.BDTIC.com/Intersil

Cases 2 and 3 illustrate the longitudinal loop current. The definition of a longitudinal loop current is a common mode current, that flows either out of or into tip and ring simultaneously . Longitudinal currents in the on-hook state result in equal currents flowing through the sense resistors R R

(Figure 17). And longitudinal currents in the off-hook state

2

and

1

result in unequal currents flowing through the sense resistors R

and R2. Notice that for case 2, longitudinal currents flowing

1

away from the SLIC, the current through R

is the metallic loop

1

current plus the longitudinal current; whereas the current through R

is the metallic loop current minus the longitudinal

2

current. Longitudinal currents are generated when the phone line is influenced by magnetic fields (e.g., power lines).

Loop Current Detector

Figure 17 shows a simplified schematic of the loop current detector. The loop current detector works by sensing the metallic current flowing through resistors R results in a current (I amplifier (gm

) that is equal to the product of gm1 and the

1

metallic loop current. I through resistor R

I

–

TIPIRING

----------------------------------- -

I

RD

The I

600

current results in a voltage drop across RD that is

RD

) out of the transconductance

RD

then flows out the RD pin and

RD

to VEE. The value of IRD is equal to:

D

I

L

--------- -==

300

compared to an internal 1.25V reference voltage. When the voltage drop across R

exceeds 1.25V, and the logic is

D

configured for loop current detection, the DET The hysteresis resistor RH adds an additional voltage

effectively across R

, causing the on-hook to off-hook

D

threshold to be slightly higher than the off-hook to on-hook threshold.

Taking into account the hysteresis voltage, the typical value of R

for the on-hook to off-hook condition is:

D

R

--------------------------------------------------------------------------=

D

I

ON HOOK to OFF– HOOK–

465

and R2. This

1

(EQ. 24)

pin goes low.

(EQ. 25

Taking into account the hysteresis voltage, the typical value of R

for the off-hook to on-hook condition is:

D

R

--------------------------------------------------------------------------=

D

I

OFF H OOK to ON– HOOK–

375

(EQ. 26)

A filter capacitor (CD) in parallel with RD will improve the accuracy of the trip point in a noisy environment. The value of this capacitor is calculated using the following Equation:

T

------- -=

C

D

R

D

(EQ. 27)

where: T = 0.5ms.

Ring Trip Detector

Ring trip detection is accomplished with the internal ring trip comparator and the external circuitry shown in Figure 18. The process of ring trip is initiated when the logic input pins are in the following states: E0 = 0, C1 = 1 and C2 = 0. This logic condition connects the ring trip comparator to the DET output, and causes the Ringrly pin to energize the ring relay. The ring relay connects the tip and ring of the phone to the external circuitry in Figure 18. When the phone is on-hook the DT pin is more positive than the DR pin and the DET output is high. For off-hook conditions DR is more positive than DT and DET

goes low. When DET goes low, indicating that the phone has gone off-hook, the SLIC is commanded by the logic inputs to go into the active state. In the active state, tip and ring are once again connected to the phone and normal operation ensues.

Figure 18 illustrates battery backed unbalanced ring injected ringing. For tip injected ringing just reverse the leads to the phone. The ringing source could also be balanced.

NOTE: The DET output will toggle at 20Hz because the DT input is not completely filtered by C and determine if the DET the off-hook condition is indicated.

. Software can examine the duty cycle

RT

pin is low for more that half the time, if so

gm1(I

+

CASE 1 CASE 2 CASE 3

I

METALLIC

←

I

LONGITUDINAL

←

I

LONGITUDINAL

→

TIP

RING

-

R

1

R

2

-

+

gm

1

CURRENT

COMPARATOR

DIGITAL MULTIPLEXER

HC5515

FIGURE 17. LOOP CURRENT DETECTOR

12

METALLIC

LOOP

)

R

H

+

-

1.25V

V

+

REF

R

D

I

RD

C

R

D

-

V

EE

-5V

DET

FN4235.6

June 6, 2006

R

www.BDTIC.com/Intersil

RT

RING

RELAY

C

R

TIP

E

RING

3

RT

RG

R

4

R

1

R

2

V

BAT

RINGRLY

DT

DR

COMPARATOR

-

+

RING TRIP

HC5515

DET

FIGURE 18. RING TRIP CIRCUIT FOR BATTERY BACKED

RINGING

Longitudinal Impedance

The feedback loop described in Figure 19(A, B) realizes the desired longitudinal impedances from tip to ground and from ring to ground. Nominal longitudinal impedance is resistive and in the order of 22Ω.

In the presence of longitudinal currents this circuit attenuate s the voltages that would otherwise appear at the tip and ring terminals, to levels well within the common mode range of the SLIC. In fact, longitudinal currents may exceed the programmed DC loop current without disturbing the SLIC’s VF transmission capabilities.

The function of this circuit is to maintain the tip and ring voltages symmetrically around V longitudinal currents. The differential transconductance amplifiers G

and GR accomplish this by sourcing or sinking

T

the required current to maintain V When a longitudinal current is injected onto the tip and ring

inputs, the voltage at VC moves from it’s equilibrium value V

/2. When VC changes by the amount DVC, this change

BAT

appears between the input terminals of the differential

I

LONG

I

LONG

/2, in the presence of

BAT

I

LONG

I

LONG

∆V

C

at V

T

+

R

-

/2.

BAT

I

TIP

+

T

∆I

1

-

R

LARGE

+

V

C

-

R

LARGE

∆I

2

RING

HC5515

I

R

FIGURE 19A. FIGURE 19B.

FIGURE 19. LONGITUDINAL IMPEDANCE NETWORK

HC5515

∆I

1

G

T

V

BAT

G

R

∆I

2

transconductance amplifiers GT and GR. The output of GT and GR are the differential currents DI1 and DI2, which in turn feed the differential inputs of current sources IT and IR respectively. IT and IR have current gains of 250 single ended and 500 differentially, thus leading to a change in IT and IR that is equal to 500(DI) and 500(DI2).

The circuit shown in Figure 19(B) illustrates the tip side of the longitudinal network. The advantages of a differential input current source are: improved noise since the noise due to current source 2I

is now correlated, power savings due

O

to differential current gain and minimized offset error at the Operational Amplifier inputs via the two 5kΩ resistors.

Digital Logic Inputs

Table 1 is the logic truth table for the TTL compatible logic input pins. The HC5515 has an enable input pin (E0) and two control inputs pins (C1, C2).

The enable pin E0 is used to enable or disable the DET output pin. The DET

pin is enabled if E0 is at a logic level 0

and disabled if E0 is at a logic level 1. A combination of the control pins C1 and C2 is used to select

1 of the 4 possible operating states. A description of each operating state and the control logic follow:

Open Circuit State (C1 = 0, C2 = 0)

In this state the SLIC is effectively off. All detectors and both the tip and ring line drive amplifiers are powered down, presenting a high impedance to the line. Power dissipation is at a minimum.

Active State (C1 = 0, C2 = 1)

The tip output is capable of sourcing loop current and for open circuit conditions is about -4V from ground. The ring output is capable of sinking loop current and for open circuit conditions is about V normal. The loop current detector is active, E0 determines if the detector is gated to the DET

TIP

V

RING

R

LARGE

C

R

LARGE

/2

+4V. VF signal transmission is

BAT

output.

TIP CURRENT SOURCE

WITH DIFFERENTIAL INPUTS

20Ω

5kΩ

∆I

1

2I

0

TIP DIFFERENTIAL

TRANSCONDUCTANCE AMPLIFIER

-

+

∆I

1

V

/2

BAT

13

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

Ringing State (C1 = 1, C2 = 0)

The ring relay driver and the ring trip detector are activated. Both the tip and ring line drive amplifiers are powered down. Both tip and ring are disconnected from the line via the external ring relay.

Standby Sta te (C1 = 1, C2 = 1)

Both the tip and ring line drive amplifiers are powered down. Internal resistors are connected between tip to ground and ring to V

to allow loop current detect in an off-hook condition.

BAT

The loop current and ground key detectors are both active, E0 determines if the detector is gated to the DET

output.

AC Transmission Circuit Stability

To ensure stability of the AC transmission feedback loop two compensation capacitors C Figure 20 (Application Circuit) illustrates their use. Recommended value is 2200pF.

AC-DC Separation Capacitor, C

The high pass filter capacitor connected between pins HPT and HPR provides the separation between circuits sensing tip to ring DC conditions and circuits processing AC signals. A 10nf C 3dB break point at 48Hz. Where:

f

3dB

will position the low end frequency response

HP

-----------------------------------------------------=

1

• CHP•()

2 π• R

HP

and CRC are required.

TC

HP

(EQ. 28)

operating conditions and allows negative surges to be returned to system ground.

The fuse resistors (R nondestructive power dissipaters during surge and fuses when the line in exposed to a power cross.

) serve a dual purpose of being

F

Power-Up Sequence

The HC5515 has no required power-up sequence. This is a result of the Dielectrically Isolated (DI) process used in the fabrication of the part. By using the DI process, care is no longer required to insure that the substrate be kept at the most negative potential as with junction isolated ICs.

Printed Circuit Board Layout

Care in the printed circuit board layout is essential for proper operation. All connections to the RSN pin should be made as close to the device pin as possible, to limit the interference that might be injected into the RSN terminal. It is good practice to surround the RSN pin with a ground plane.

The analog and digital grounds should be tied together at the device.

where R

= 330kΩ.

HP

Thermal Shutdown Protection

The HC5515’s thermal shutdown protection is invoked if a fault condition on the tip or ring causes the temperature of the die to exceed 160°C. If this happens, the SLIC goes into a high impedance state and will remain there until the temperature of the die cools down by about 20°C. The SLIC will return back to its normal operating mode, providing the fault condition has been removed.

Surge Voltage Protection

The HC5515 must be protected against surge voltages and power crosses. Refer to “Maximum Ratings” TIPX and RINGX terminals for maximum allowable transient tip and ring voltages. The protection circuit shown in Figure 20 utilizes diodes together with a clamping device to protect tip and ring against high voltage transients.

Positive transients on tip or ring are clamped to within a couple of volts above ground via diodes D normal operating conditions D and out of the circuit.

Negative transients on tip and ring are clamped to within a couple of volts below ground via diodes D help of a Surgector. The Surgector is required to block conduction through diodes D

and D2 are reverse biased

1

and D4 under normal

3

and D2. Under

1

and D4 with the

3

14

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

SLIC Operating States

TABLE 1. LOGIC TRUTH TABLE

E0 C1 C2 SLIC OPERATING STATE ACTIVE DETECTOR DET

0 0 0 Open Circuit No Active Detector Logic Level High 0 0 1 Active Loop Current Detector Loop Current Status 0 1 0 Ringing Ring Trip Detector Ring Trip Status 0 1 1 Standby Loop Current Detector Loop Current Status

1 0 0 Open Circuit No Active Detector 1 0 1 Active Loop Current Detector 1 1 0 Ringing Ring Trip Detector 1 1 1 Standby Loop Current Detector

Logic Level High

OUTPUT

Notes

2. Overload Level (Two-Wire port) - The overload level is specified at the 2-wire port (V 4-wire receive port (E increase the amplitude of E

. Reference Figure 1.

V

TRO

RX

3. Longitudinal Impedance - The longitudinal impedance is computed using the following equations, where TIP and RING voltages are referenced to ground. L

are defined in Figure 2.

A

T

(TIP) L

(RING) L

where: E

= VT/AT,

ZT

= VR/AR,

ZR

= 1V

L

(0Hz to 100Hz).

RMS

4. Longitudinal Current Limit (Off-Hook Active) - Off-Hook (Active, C

= 1, C2 = 0) longitudinal current limit is determined

1

by increasing the amplitude of E longitudinal balance drops below 45dB. DET (no false detection).

5. Longitudinal Current Limit (On-Hook Standby) - On-Hook (Active, C by increasing the amplitude of E

= 1, C2 = 1) longitudinal current limit is determined

1

longitudinal balance drops below 45dB. DET (no false detection).

6. Longitudinal to Metallic Balance - The longitudinal to metallic balance is computed using the following equation:

BLME = 20 • log (E Figure 4.

L/VTR

7. Metallic to Longitudinal FCC Part 68, Para 68.310 - The metallic to longitudinal balance is defined in this spec.

8. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire balance is computed using the following equation:

BLFE = 20 • log (E

L/VTX

9. Metallic to Longitudinal Balance - The metallic to longitudinal balance is computed using the following equation:

BMLE = 20 • log (E

where: E

TR, VL

TR/VL

and ERX are defined in Figure 5.

10. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal balance is computed using the following equation:

) with the signal source at the

TR0

). I

RX

= 30mA, RSG = 4kΩ,

DCMET

until 1% THD is measured at

, LZR, VT, VR, AR and

ZT

(Figure 3A) until the 2-wire

L

(Figure 3B) until the 2-wire

L

pin remains low

pin remains high

), where: EL and VTR are defined in

),: EL and VTX are defined in Figure 4.

), ERX = 0,

BFLE = 20 • log (E

where: E

and ETR are defined in Figure 5.

RX, VL

), ETR = source is removed.

RX/VL

11. Two-Wire Return Loss - The 2-wire return loss is computed using the following equation:

r = -20 • log (2V

where: Z impedance of the line, nominally 600Ω. (Reference Figure 6).

= The desired impedance; e.g., the characteristic

D

M/VS

).

12. Overload Level (4-Wire port) - The overload level is specified at the 4-wire transmit port (V the 2-wire port, I

= 23mA, ZL = 20kΩ, RSG = 4kΩ (Refer-

DCMET

ence Figure 7). Increase the amplitude of E measured at V the 4-wire port is equal to 1.

. Note that the gain from the 2-wire port to

TXO

) with the signal source (EG) at

TXO

until 1% THD is

G

13. Output Offset Voltage - The output offset voltage is specified with the following conditions: E and is measured at VTX. EG, I in Figure 7. Note: I resistor between tip and ring.

DCMET

= 0, I

G DCMET

is established with a series 600Ω

14. Two-Wire to Four-Wire (Metallic to V

2-wire to 4-wire (metallic to V using the following equation.

= (VTX/VTR), EG = 0dBm0, VTX, VTR, and EG are defined

G

2-4

in Figure 7.

) voltage gain is computed

TX

= 23mA, ZL = ∞

DCMET

, VTX and ZL are defined

) Voltage Gain - The

TX

15. Current Gain RSN to Metallic - The current gain RSN to

Metallic is computed using the following equation:

[(R

K = I V

RDC

M

and V

DC1

+ R

RSN

)/(V

RDC

- V

RSN

DC2

are defined in Figure 8.

)] K, IM, R

DC1

, R

DC2

16. Two-Wire to Four-Wire Frequency Response - The 2-wire to 4-wire frequency response is measured with respect to

= 0dBm at 1.0kHz, ERX = 0V, I

E

G

DCMET

= 23mA. The

frequency response is computed using the following equation:

= 20 • log (VTX/VTR), vary frequency from 300Hz to

F

2-4

3.4kHz and compare to 1kHz reading.

, VTR, and EG are defined in Figure 9.

V

TX

17. Four-Wire to Two-Wire Frequency Response - The 4-wire to 2-wire frequency response is measured with respect to

= 0dBm at 1.0kHz, EG = 0V, I

E

RX

frequency response is computed using the following equation:

= 20 • log (VTR/ERX), vary frequency from 300Hz to

F

4-2

DCMET

= 23mA. The

,

15

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

3.4kHz and compare to 1kHz reading.

and ERX are defined in Figure 9.

V

TR

18. Four-Wire to Four-Wire Frequency Response - The 4-wire to 4-wire frequency response is measured with respect to

= 0dBm at 1.0kHz, EG = 0V, I

E

RX

frequency response is computed using the following equation:

= 20 • log (VTX/ERX), vary frequency from 300Hz to

F

4-4

3.4kHz and compare to 1kHz reading.

and ERX are defined in Figure 9.

V

TX

DCMET

= 23mA. The

19. Two-Wire to Four-Wire Insertion Loss - The 2-wire to 4-wire insertion loss is measured with respect to E input signal, E

RX

= 0, I

= 23mA and is computed using

DCMET

= 0dBm at 1.0kHz

G

the following equation:

= 20 • log (VTX/VTR)

L

2-4

where: V fuse resistors, R insertion loss is for R

, VTR, and EG are defined in Figure 9. (Note: The

TX

, impact the insertion loss. The specified

F

= 0).

F

20. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire insertion loss is measured based upon E input signal, E

= 0, I

G

= 23mA and is computed using

DCMET

= 0dBm, 1.0kHz

RX

the following equation:

= 20 • log (VTR/ERX),

L

4-2

where: V

and ERX are defined in Figure 9.

TR

21. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire gain tracking is referenced to measurements taken for

= -10dBm, 1.0kHz signal, ERX = 0, I

E

G

DCMET

= 23mA and is

computed using the following equation.

= 20 • log (VTX/VTR) vary amplitude -40dBm to +3dBm, or

G

2-4

-55dBm to -40dBm and compare to -10dBm reading.

and VTR are defined in Figure 9.

V

TX

22. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire gain tracking is referenced to measurements taken for

= -10dBm, 1.0kHz signal, EG = 0, I

E

RX

computed using the following equation:

= 20 • log (VTR/ERX) vary amplitude -40dBm to +3dBm, or

G

4-2

-55dBm to -40dBm and compare to -10dBm reading.

and ERX are defined in Figure 9. The level is specified at

V

TR

DCMET

= 23mA and is

the 4-wire receive port and referenced to a 600Ω impedance level.

23. Two-Wire Idle Channel Noise - The 2-wire idle channel noise

is specified with the 2-wire port terminated in 600Ω (RL)

at V

TR

and with the 4-wire receive port grounded (Reference Figure 10).

24. Four-Wire Idle Channel Noise - The 4-wire idle channel noise

is specified with the 2-wire port terminated in 600Ω (RL).

at V

TX

The noise specification is with respect to a 600Ω impedance level at V

. The 4-wire receive port is grounded (Reference

TX

Figure 10).

25. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic distortion is measured with the following conditions.

= 0dBm at 1kHz, I

E

G

V

. (Reference Figure 7).

TX

= 23mA. Measurement taken at

DCMET

26. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic distortion is measured with the following conditions. E 0dBm0. Vary frequency between 300Hz and 3.4kHz, I 23mA. Measurement taken at V

. (Reference Figure 9).

TR

RX

DCMET

=

27. Constant Loop Current - The constant loop current is calculated using the following equation:

= 2500 / (R

I

L

DC1

+ R

DC2

).

28. Standby State Loop Current - The standby state loop current is calculated using the following equation:

= [|V

I

L

29. Power Supply Rejection Ratio - Inject a 100mV (50Hz to 4kHz) on V computed using the following equation:

PSRR = 20 • log (V

| - 3] / [RL +1800], TA = 25°C.

BAT

, VCC and VEE supplies. PSRR is

BAT

). VTX and VIN are defined in Figure 11.

TX/VIN

RMS

signal

=

Pin Descriptions

PLCC SYMBOL DESCRIPTION

1RING

SENSE

2 BGND Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.

4V

CC

5 RINGRLY Ring relay driver output. 6V 7R

BAT

SG

8 NC This pin is used during manufacturing. This pin is to be left open for proper SLIC operation. 9 E0 TTL compatible logic input. Enables the DET

11 DET Detector output. TTL comp atible logic output. A zero logic level indicates that the selected detector was triggered (see

12 C2 TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing

Internally connected to output of RING power amplifier.

Internally separate from AGND but it is recommended that it is connected to the same potential as AGND. +5V power supply.

Battery supply voltage, -24V to -56V. Saturation guard programming resistor pin.

output when set to logic level zero and disables DET output when set to

a logic level one.

Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET an open collector with an internal pull-up of approximately 15kΩ to V

CC.

or Standby) of the SLIC.

16

output is

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

Pin Descriptions (Continued)

PLCC SYMBOL DESCRIPTION

13 C1 TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing

14 R

15 AGND Analog ground. 16 RSN Receive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that flows

18 V 19 V

20 HPR RING side of AC/DC separation capacitor C

21 HPT TIP side of AC/DC separation capacitor C

22 RD Loop current programming resistor. Resistor R

23 DT Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in

25 DR Input to ring trip comparator . Ring trip detection is accomplished by connecting an external network to a comparator in

DC

EE

TX

or Standby) of the SLIC. DC feed current programming resistor pin. Constant current feed is programmed by resistors R

connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to AGND to isolate the AC signal components.

between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into the RSN pin. The constant current programming resistors and the networks for program receive gain and 2-wire impedance all connect to this pin.

-5V power supply. Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming the

2-wire input impedance connects between this pin and RSN.

. C

is required to properly separate the ring AC current from the DC

HP

is required to properly separate the tip AC current from the DC loop

HP

sets the trigger level for the loop current detect circuit. A filter capacitor

D

loop current. The other end of C

current. The other end of C

is also connected between this pin and VEE.

C

D

the SLIC with inputs DT and DR.

is connected to HPT.

HP

is connected to HPR.

HP

. C

DC1

and R

DC2

26 TIP 27 TIPX Output of tip power amplifier. 28 RINGX Output of ring power amplifier.

3, 10 17,

24

SENSE

N/C No internal connection.

Internally connected to output of tip power amplifier.

17

FN4235.6

June 6, 2006

Pinout

www.BDTIC.com/Intersil

HC5515

(PLCC)

TOP VIEW

RINGRLY

V

BAT

R

SG

NC

E0

N/C

DET

VCCN/C

5

6

7

8

9

10

11

12 13 14 15 16 17 18

C2

C1

BGND

1234

DC

R

SENSE

RING

AGND

RINGX

RSN

TIPX

N/C

TIP

262728

V

SENSE

EE

DR

25

N/C

24

DT

23

RD

22

HPT

21

HPR

20

V

19

TX

18

FN4235.6

June 6, 2006

Application Circuit

www.BDTIC.com/Intersil

HC5515

(V

BAT

R

RT

R

3

PTC

TIP

PTC

RING

RINGING

+ 90V

RMS

)

U1 SLIC (Subscriber Line Interface Circuit)

U2 Combination CODEC/Filter e.g.

C

DC

C

HP

C

RT

, CRC2200pF, 20%, 100V

C

TC

Relay Relay, 2C Contacts, 5V or 12V Coil

D

- D5IN4007 Diode

1

Surgector SGT27S10

PTC Polyswitch TR600-150

D

, RF2Line Resistor, 20Ω, 1% Match, 2 W

R

F1

C

R

F1

D

R

F2

+5V RELAY

OR

12V

RT

4

3

4

R

1

R

2

V

BAT

NOTE 31

Surgector

G

D

5

R

D

-5V

D

1

C

TC

C

D

2

AK

D

6

RC

V

BAT

R

-5V

HC5515

CD22354A or Programmable CODEC/ Filter, e.g. SLAC

1.5µF, 20%, 10V 10nF, 20%, 100V (Note 2)

0.39µF, 20%, 100V

Diode, 1N4454

6

Carbon column resistor or thick film on ceramic

SG

21 HPT

22 RD 23 DT

25 DR 27 TIPX

2 BGND

4 V

CC

28 RINGX

6 V

BAT

5 RINGRLY

7 R

SG

CHP (NOTE 32)

U

HPR 20

1

V

TX

VEE 18

RSN 16

AGND 15

R

DC

C1 13

C2 12

DET

R1, R3200kΩ, 5%, 1/4W

910kΩ, 5%, 1/4W

R

2

1.2MΩ, 5%, 1/4W

R

4

R

18.7kΩ,1%, 1/4W

B

39kΩ, 5%, 1/4W

R

D

, R

R

DC1

41.2kΩ, 5%, 1/4W

DC2

R

20.0kΩ, 1%, 1/4W

FB

280kΩ, 1%, 1/4W

R

RX

562kΩ, 1%, 1/4W

R

T

R

20kΩ, 1%, 1/4W

TX

150Ω, 5%, 2W

R

RT

R

SGVBAT

V

BAT

19

14

11

E

9

O

E

8

1

= -28V, R = -48V, R

-5V

R

T

R

DC2

= ∞

SG

= 4.0kΩ, 1/4W 5%

SG

R

FB

U

R

TX

R

B

R

RX

R

DC1

C

DC

2

-

+

CODEC/FILTER

NOTES:

30. It is recommended that the anodes of D

31. To meet the specified 25dB 2-wire return loss at 200Hz, C

and D4 be shorted to ground through a battery referenced surgector (SGT27S10).

3

needs to be 20nF, 20%, 100V.

HP

FIGURE 20. APPLICATION CIRCUIT

19

FN4235.6

June 6, 2006

HC5515

www.BDTIC.com/Intersil

Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)

0.048 (1.22) PIN (1) IDENTIFIER

0.020 (0.51) MAX 3 PLCS

C

L

D1

D

0.026 (0.66)

0.032 (0.81)

0.045 (1.14) MIN

0.050 (1.27) TP

0.042 (1.07)

0.056 (1.42)

EE1

VIEW “A” TYP.

C

L

A

0.013 (0.33)

0.021 (0.53)

0.025 (0.64) MIN

0.004 (0.10) C

0.025 (0.64)

0.045 (1.14)

D2/E2

A1

-C-

VIEW “A”

0.020 (0.51) MIN

SEATING PLANE

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line.

4. To be measured at seating plane contact point.

-C-

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

N28.45 (JEDEC MS-018AB ISSUE A)

R

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

INCHES MILLIMETERS

SYMBOL

NOTESMIN MAX MIN MAX

A 0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D 0.485 0.495 12.32 12.57 D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5

E 0.485 0.495 12.32 12.57 E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5

N28 286

Rev. 2 11/97

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN4235.6

June 6, 2006

Datasheet HC5515 Datasheet (intersil)

Specifications and Main Features

Frequently Asked Questions

User Manual