Datasheet HC5503PRC Datasheet (intersil)

®

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HC5503PRC

Data Sheet June 2004

Low Cost SLIC For Large Telecom
Switches

The HC5503PRC is a low cost SLIC optimized for large
Telecom switches. It combines a flexible voltage feed
architecture with the Intersil latch-free DI bonded wafer
process, to provide a low component count, carrier class
solution at very low cost. The re-configurable design permits
simple, economical solutions for campus-wide call center
and PBX applications. External components can be used in
conjunction with the high battery voltage capability to meet
the complex impedance and long loop drive requirements of
Central Office switches, worldwide.

Ordering Information

TEMP.

PART NUMBER

HC5503PRCB 0 to 70 24 Ld SOIC M24.3
HC5503PRCBZ

(Note)
HC5503PRCBZ96

(Note)
HC5503PRCR 0 to 70 32 Ld 7x7 QFN L32.7x7
HC5503PRCRZ

(Note)
HC5503PRCRZ96

(Note)

NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.

RANGE (°C) PACKAGE

0 to 70 24 Ld SOIC (Pb-free) M24.3

0 to 70 24 Ld SOIC Tape & Reel

(Pb-free)

0 to 70 32 Ld 7x7 QFN

(Pb-free)

0 to 70 32 Ld 7x7 QFN

Tape & Reel (Pb-free)

PKG.

DWG. #

M24.3

L32.7x7

L32.7x7

FN4806.3

Features

• Wide Operating Battery Range (-40V to -58V)

• Single Additional +5V Supply

• 30mA Short Loop Current Limit

• Ring Relay Driver

• Switch Hook and Ring Trip Detect

• Low On-Hook Power Consumption

• On-Hook Transmission

• ITU-T Longitudinal Balance Performance

• Loop Power Denial Function

• Thermal Protection

• Supports Tip, Ring or Balanced Ringing Schemes

• Low Profile SO and QFN Surface Mount Packaging

• Pb-free Available

Applications

• Central Office, PBX, Call Centers

• Related Literature

- AN571, Using Ring Sync with HC-5502A and HC-5504
SLICs

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 1999, 2003, 2004. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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HC5503PRC

RD

RFS

C

TIP

TF

RING

RF

V

BAT

V

CC

AGND
BGND

DGND

RING RELAY

DRIVER

RING TRIP

BIAS

DETECTOR

2-WIRE

INTERFACE

LOOP CURRENT

DETECTOR

THERMAL LIMIT

2

4-WIRE

INTERFACE
VF SIGNAL

PATH

LOGIC

INTERFACE

TX

RX

SHD

RS
RC

PD

C1
OUT

+

-

+IN

-IN

2

HC5503PRC

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Absolute Maximum Ratings Thermal Information

Maximum Continuous Supply Voltages

(V

-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V

B

+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V

(V

B

+ - VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V

(V

B

Relay Drive Voltage (V

). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V

RD

Operating Conditions

Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Relay Driver Voltage (V
Positive Supply Voltage (V
Negative Supply Voltage (V

High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V

Low Level Logic Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V

Subscriber Loop Resistance . . . . . . . . . . . . . . . . . . . 200Ω - 1800Ω

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.

is measured with the component mounted on an evaluation PC board in free air.

2. θ

JA

for the QFN package is measured in free air with the component mounted on a high effective thermal conductivity test board with direct

3. θ

JA

attach features including conductive thermal vias. See Tech Brief TB379 and TB389 for additional information and board layout consideration

) . . . . . . . . . . . . . . . . . . . . . . . .5V to 12V

RD

+). . . . . . . . . . . . . . . . . . 4.75V to 5.25V

B

-) . . . . . . . . . . . . . . . . . . .-40V to -58V

B

Thermal Resistance (Typical, Note 2, 3)

24 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

32 Lead 7x7 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Die Characteristics

Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI

θ

JA

(°C/W)

Electrical Specifications Unless Otherwise Specified, V

Parameters. T

PARAMETER CONDITIONS MIN TYP MAX UNITS

On Hook Power Dissipation I
Off Hook Power Dissipation R
On Hook I
Off Hook IB+R
On Hook I
Off Hook I
Off Hook Loop Current RL = 1800Ω (I
Off Hook Loop Current R
Fault Currents

TIP to Ground -27-mA
RING to Ground -55-mA
TIP to RING -30-mA

TIP and RING to Ground -69-mA
Ring Relay Drive V
Ring Relay Driver Off Leakage V
DC Ring Trip Threshold 8.1 10.8 13.5 mA
Switch Hook Detection Threshold 5.0 7.5 10 mA
Loop Current During Power Denial R
Dial Pulse Distortion (Note 4) 0 - 0.5 ms
Receive Input Impedance (Note 4) - 110 - kΩ
Transmit Output Impedance (Note 4) - 10 20 Ω

+R

B

-R

B

-R

B

OL

= 25°C. Min-Max Parameters are Over Operating Temperature Range

A

= 0 (Note 4) - 113 - mW

LONG

= 600Ω, I

L

= ∞, I

L

LONG

= 600Ω, I

L

= ∞, I

L

LONG

= 600Ω, I

L

= 200Ω, I

L

IOL = 62mA - 0.2 0.5 V

= 12V, RC = 1 = HIGH, TA = 25°C - - 100 µA

RD

= 200Ω -3.2-mA

L

- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50Ω, RS = 100Ω, Typical

B

= 0 (Notes 3, 4) - 750 - mW

LONG

= 0 - 1.4 - mA

= 0 - 2.8 - mA

LONG

= 0 - 2.2 - mA

= 0 - 31 - mA

LONG

= 0) 18 - - mA

LOOP

= 0 (Note 3) 25 30 35 mA

LONG

3

HC5503PRC

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Electrical Specifications Unless Otherwise Specified, V

Parameters. T

PARAMETER CONDITIONS MIN TYP MAX UNITS

2-Wire Return Loss (Referenced to 600Ω + 2.16µF), RP = RS = 150Ω

LO - 15.5 - dB

SR

L

ER

L

HI -31-dB

SR

L

Longitudinal Balance 1V

2-Wire Off Hook (Note 4) 53 58 - dB

2-Wire On Hook (Note 4) 53 58 - dB

4-Wire Off Hook 50 58 - dB
Insertion Loss At 1kHz, 0dBm Input Level, Referenced 600Ω,

2-Wire to 4-Wire, 4-Wire to 2-Wire - ±0.05 ±0.2 dB
Frequency Response 200 - 3400Hz Referenced to Absolute Loss at 1kHz and

Idle Channel Noise R

2-Wire to 4-Wire, 4-Wire to 2-Wire -15dBrnC

Absolute Delay R

2-Wire to 4-Wire, 4-Wire to 2-Wire --2µs
Trans Hybrid Loss Balance Network Set Up for 600Ω Termination at 1kHz,

Overload Level V

2-Wire to 4-Wire, 4-Wire to 2-Wire 1.5 - - V
Level Linearity

2-Wire to 4-Wire, 4-Wire to 2-Wire (Note 4)

Power Supply Rejection Ratio R

+ to 2-Wire 15 - - dB

V

B

+ to Transmit 15 - - dB

V

B

- to 2-Wire 15 - - dB

V

B

VB- to Transmit 15 - - dB

+ to 2-Wire 200 - 16kHz, RL = 600Ω, RP = RS = 150Ω 30 - - dB

V

B

+ to Transmit 30 - - dB

V

B

- to 2-Wire 30 - - dB

V

B

- to Transmit 30 - - dB

V

B

Logic Input Current (RS, RC
Logic Inputs

Logic ‘0’ V

Logic ‘1’ V
Logic Outputs

Logic ‘0’ V

Logic ‘1’ V

IL
IH

OL
OH

, PD)0V ≤ VIN ≤ 5V - - ±100 µA

= 25°C. Min-Max Parameters are Over Operating Temperature Range (Continued)

A

(Note 4)

200Hz - 3400Hz, (Note 4) IEEE Method

RMS

0°C ≤ T

R

0dBm Signal Level, R

R

At 1kHz, (Note 4) Referenced to 0dBm Level,
R

30 - 60Hz, R

I
I

≤ 75°C, RP = RS = 150Ω

A

P=RS

= RS = 150Ω (Note 4)

P

= RS = 150Ω (Note 4)

P

= RS = 150Ω (Note 4)

P

+ = +5V, RP = RS = 150Ω (Note 4)

B

= RS = 150Ω

P

+3 to -40dBm - - ±0.05 dB

-40 to -50dBm - - ±0.1 dB

-50 to -55dBm - - ±0.3 dB
= RS = 150Ω (Note 4)

P

800µA, VB+ = 5V - 0.1 0. 5 V

LOAD

40µA, VB+ = 5V 2.7 - 5.0 V

LOAD

- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50Ω, RS = 100Ω, Typical

B

-24-dB

= 150Ω

- ±0.02 ±0.05 dB

--89-85dBm0p

30 40 - dB

--0.8V

2.0 - 5.5 V

= 600Ω

L

= RS = 150Ω (Note 4)

P

PEAK

4

HC5503PRC

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Electrical Specifications Unless Otherwise Specified, V

Parameters. T

PARAMETER CONDITIONS MIN TYP MAX UNITS

UNCOMMITTED OP AMP SPECIFICATIONS

Input Offset Voltage - ±5-mV
Input Offset Current - ±10 - nA
Input Bias Current -20-nA
Differential Input Resistance (Note 4) - 1 - MΩ
Output Voltage Swing R
Output Resistance A
Small Signal GBW (Note 4) - 1 - MHz

NOTES:

4. I

5. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial

= Longitudinal Current.

LONG

design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification
compliance.

= 25°C. Min-Max Parameters are Over Operating Temperature Range (Continued)

A

= 10K, VB+ = 5V - ±3-V

L

= 1 (Note 4) - 10 - Ω

VCL

- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50Ω, RS = 100Ω, Typical

B

PEAK

Pin Descriptions

24 PIN

DIP/SOIC

1 28 TIP An analog input connected to the TIP (more positive) side of the subscriber loop through a sense resistor

2 31 RING An analog input connected to the RING (more negative) side of the subscriber loop through a sense

3 32 RFS Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal is inserted

41V
53C

6 4 DG Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and

7 5 RS Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a

86RD
9 7, 8 TF Tip Feed - A low impedance analog output connected to the TIP terminal through a sense resistor (R

10 9, 10 RF Ring Feed - A low impedance analog output connected to the RING terminal through a sense resistor

11 11 V

12 12 BG Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into

13 13 SHD

14 14,19 NC Used during production test. Leave disconnected.

7 x 7
QFN SYMBOL DESCRIPTION

) and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone

(R

S

and for loop monitoring purposes.

resistor (R
telephone and for loop monitoring purposes.

into the line at this node and RF is isolated from RFS via a relay.

+ Positive Voltage Source - Most positive supply. VB+ is typically.

B

Capacitor #1 - An external capacitor to be connected between this terminal and analog ground. Required

1

for proper operation of the loop current limiting function, and for filtering V

outputs on the SLIC microcircuit.

positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS
terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing
and for Ring injected systems, on the positive going zero crossing. This ensures that the ring relay
activates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not
required, the pin should be tied to 5V.

Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized.

Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink
longitudinal current.

(R

S

sink longitudinal current.

- Negative Voltage Source - Most negative supply. VB- is typically -48V with an operational range of -42V

B

to -58V. Frequently referred to as “battery”.

this ground terminal.
Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop

currents exceeding the switch hook threshold.

) and a ring relay contact. Functions with the Tip terminal to receive voice signals from the

S

). Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and

-. Typical value is 0.3µF, 30V.

B

).

S

5

HC5503PRC

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Pin Descriptions (Continued)

24 PIN

DIP/SOIC

15 15 PD Power Denial - A low active TTL - Compatible logic input. When enabled, the ring feed voltage collapses

16 16 RC

17 NC Leave disconnected.
18 20 OUT The analog output of the spare operational amplifier.
19 21 -IN The inverting analog input of the spare operational amplifier.
20 22 +IN The non-inverting analog input of the spare operational amplifier.
21 23 RX Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive

22 25 C

23 26 AG Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX)

24 27 TX Transmit Output, Four Wire Side - A low impedance analog output proportional to the loop current.

NOTE: All grounds (AG, BG, and DG) must be applied before V
to run separate grounds off a line card, the AG must be applied first.

7 x 7
QFN SYMBOL DESCRIPTION

to the tip feed voltage (~4V). The DC feed is disabled, but the AC transmission is maintained. The switch

) is not necessarily valid, and the relay driver (RD) output is disabled.

= 0) or the subscriber is not already off- hook (SHD = 0).

+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes

B

2, 17,

18,24, 29,

30,

hook detect (SHD
Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output

goes low on the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial
state (PD

coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and
Ring feed terminals.

Capacitor #2 - An external capacitor to be connected between this terminal and analog ground. This

2

capacitor is required for the proper operation of ring trip detection. Recommended value 0.82µF ±10%
10V non-polarized.

and receive input (RX) terminals.

Transhybrid balancing must be performed beyond this output to completely implement two to four wire
conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output
varies with loop current, capacitive coupling to the next stage is essential.

NC No internal connection.

6

Functional Diagram

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HC5503PRC

RFS

R

S

R

S

RING

TIP

PD

RS
RC
RD

TF

V

BG

RF

-

B

RING SYNC

RING COMMAND

R

1/2 RING

TIP

2-WIRE

LOOP

RING

RING

VOLTAGE

RS: 100Ω; 1/2W to 2W depending on surge requirements
R

:50Ω; 1/2W to 2W depending on surge requirements

P

RELAY

SECONDARY

PROTECTION

VB-

1/2 RING

RELAY

VB-

P

R

P

POWER DENIAL

RING
TRIP

RING

CONTROL

BATTERY

FEED

LOOP

CURRENT

LIMITER

SLIC MICROCIRCUIT

MONITORING

+1

LINE

DRIVERS

-1

LOOP

DIFF
AMP

+

OP
AMP

SHD

SWITCH HOOK
DETECTION

TX

TRANSMIT
OUTPUT

OUT

+IN

+

-IN

RX

RECEIVE
INPUT

7

HC5503PRC

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SLIC FUNCTIONAL SCHEMATIC

SOIC PIN NUMBERS SHOWN

TF

9

TIP

1

RING
FEED

SENSE

3

RING

2

RF

10

VB+

V

BAT

R

R
R
R

R

R

R
R
R

R

R

RING FEED

V

BAT

TIP FEED

I

B4

7

8

10
9

22

3

4

1

2

16

15

A-300

AMP

I

B5

21 22 11 12 23 6 4

RX C2 V

R

+

A-400

AMP

17

IB1IB2IB3IB4IB5IB6IB7I

V

B2

BAT ANA DIG

BAT

GND GND GND

VOLTAGE AND CURRENT

BIAS NETWORK

-

R

12

VB+

V
R

+

BAT
23

-

QD3Q

VB+

R

-

D36

+

R

11

V

BAT

+

-

V

BAT/2

V

B2

21

A-200
LONG’L
I/V A MP

I

B7

R

5

A-100
TRANSV’L
I/V AMP

V

I

B6

REFERENCE

VB+

VB+

BAT

R

R

20

V

BAT

R

6

14

R

18

R

19

VB+

VB+

IB9I

V

B8

BAT

RING TRIP DETECTOR

+

SWITCH HOOK

VB+

+

Q

D27

LOAD CURRENT
LIMITING

B10IB11

V

BAT

I

B8

DETECTOR

I

B6

I

B2

5V

V

-

Q

D28

V

-

+

20 19 1 8

+ -

V

B1

V

B2

V

B3

V

B4

V

B5

5V

B4

GND SHORTS

CURRENT

LIMITING

I

B1

A-500
OP AMP

I

B3

5V

- +

V

B3

V

BAT

V

B1

THERMAL

LIMITING

V

B5

B5

OUT

VB+

V

BAT

I

VB+

B10

GK

STTL
AND LOGIC
INTERFACE

SH

RFC

V

BAT

NC

14

NC

17

SHD

13

RC

16

PD

15

R

13

V

BAT

TXC1 RS RD

V

BAT

8

87245

HC5503PRC

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LOGIC GATE SCHEMATIC

GK

SH

TO

R

10

TTL

TO

STTL

21

LOGIC BIAS

5

11 14

6

A

B

C

SCHOTTKY LOGIC

8

97

DELAY

RELAY

DRIVER

3

12

13

STTL

C
B
A

TO

TTL

SHDRDPDRCRS

2

1

4

16

15

TTL

TO

STTL

TTL

TO

STTL

Surge Protection

The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.

The voltage withstand capability of pins ‘Tip’, ‘Ring’ and
‘RFs’ is ±450V with respect to ground, as shown in Table 1.

TABLE 1.

TEST

PARAMETER

Longitudinal Surge 10µs Rise/

Metallic Surge 10µs Rise/

T/GND
R/GND

50/60Hz Current
T/GND
R/GND

CONDITION

1000µs Fall

1000µs Fall
10µs Rise/

1000µs Fall
11 Cycles

Limited to
10A

RMS

PERFORMANCE

(MAX) UNITS

±450 (Plastic) V

±450 (Plastic) V

±450 (Plastic) V

315 (Plastic) V

PEAK

PEAK

PEAK

RMS

This device is intended for use with an appropriate
secondary protection circuit scheme.

The SLIC will withstand longitudinal currents up to a
maximum or 30mA

RMS

, 15mA

per leg, without any

RMS

performance degradation.

9

Small Outline Plastic Packages (SOIC)

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HC5503PRC

N

INDEX
AREA

123

-A­D

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

E

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

H

α

µ

A1

0.10(0.004)

L

h x 45

o

C

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 ­h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is ca utioned to verify that data she ets are current before pl acing orders. Information fur nished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or othe rwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

10

HC5503PRC

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Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)

2X

0.15

C

E1/2

E1

A2

A

A1

8

E2

9
CORNER
OPTION 4X

A1

A

E/2

9

/ /

9

(Ne-1)Xe

REF.

7
8

C

L

E

B

0.10 C

0.08

e

0.152XB

C

L1

C

L

10

A

6

INDEX

AREA

AREA

2X

2X

SEATING PLANE

(DATUM B)

(DATUM A)

INDEX
AREA

FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE

0.15

6

CC

C

4X

C

4X P

4X P

NX L

e

1
2
3

B

AC0.15

0

8

C

L

D

9

N

BOTTOM VIEW

D1

D1/2

N

TOP VIEW

SIDE VIEW

NX b

D2

D2

2

e
(Nd-1)Xe

REF.

NX b

5

L1

TERMINAL TIP

D/2

5

SECTION "C-C"

0.10 BAMC
7

NX k

N

1
2

3

L

10

A3

E2/2

L32.7x7

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKC ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 ­A1 - - 0.05 ­A2 - - 1.00 9
A3 0.20 REF 9

b 0.23 0.28 0.38 5, 8

D 7.00 BSC ­D1 6.75 BSC 9
D2 4.55 4.70 4.85 7, 8

E 7.00 BSC ­E1 6.75 BSC 9
E2 4.55 4.70 4.85 7, 8

e 0.65 BSC -

k0.25---

L 0.50 0.60 0.75 8
L1 - - 0.15 10

N322
Nd 8 3
Ne 8 3

P--0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present
when Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

NOTESMIN TYP MAX

Rev. 4 8/03

11