Intersil Corporation HA-5114, HA-5104, HA-5102 Datasheet

HA-5102, HA-5104, HA-5114

Data Sheet April 1999

Dual and Quad, 8MHz and 60MHz, Low
Noise Operational Amplifiers

Low noise and high performance are key words describing
HA-5102, HA-5104 and HA-5114. These general purpose
amplifiers offer an array of dynamic specifications ranging
from a 3V/µs slew rate and 8MHz bandwidth (5102/04) to
20V/µs slew rate and 60MHz gain-bandwidth-product
(HA-5114). Complementing these outstanding parameters is
a very low noise specification of 4.3nV/√

Fabricated using the Intersil high frequency DI process,
these operational amplifiers also offer excellent input
specifications such as a 0.5mV offset voltage and 30nA
offset current. Complementing these specifications are
108dB open loop gain and 60dB channel separation.
Consuming a very modest amount of power (90mW/
package for duals and 150mW/package for quads), HA­5102/04/14 also provide 15mA of output current.

This impressive combination of features make this series of
amplifiers ideally suited for designs ranging from audio
amplifiers and active filters to the most demanding signal
conditioning and instrumentation circuits.

These operational amplifiers are available in dual or quad
form with industry standard pinouts allowing for immediate
interchangeability with most other dual and quad operational
amplifiers.

Hz at 1kHz.

File Number 2925.4

Features

• Low Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3nV/√Hz

• Bandwidth. . . . . . . . . . . . . . . . . . . . 8MHz (Compensated)

60MHz (Uncompensated)

• Slew Rate. . . . . . . . . . . . . . . . . . . . 3V/µs (Compensated)

20V/µs (Uncompensated)

• Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 0.5mV

• Available in Duals or Quads

Applications

• High Q, Active Filters

• Audio Amplifiers

• Instrumentation Amplifiers

• Integrators

• Signal Generators

• For Further Design Ideas, See Application Note AN554

Pinouts

HA-5102 (PDIP, CERDIP)

TOP VIEW

OUT1

-IN1

+IN1

1
2

-

+

3
4

V-

8

V+

7

OUT2

6

-IN2

-

+

5

+IN2

HA-5102 Dual, Comp. HA-5104 Quad, Comp.
HA-5114 Quad, Uncomp.

Refer to the /883 data sheet for military product.

Ordering Information

TEMP.RANGE

PART NUMBER

HA3-5102-5 0 to 75 8 Ld PDIP E8.3
HA7-5102-2 -55 to 125 8 Ld CERDIP F8.3A
HA1-5104-2 -55 to 125 14 Ld CERDIP F14.3
HA1-5104-5 0 to 75 14 Ld CERDIP F14.3
HA3-5104-5 0 to 75 14 Ld PDIP E14.3
HA9P5104-9 -40 to 85 16 Ld SOIC M16.3
HA3-5114-5 0 to 75 14 Ld PDIP E14.3
HA9P5114-9 -40 to 85 16 Ld SOIC M16.3

(oC) PACKAGE PKG. NO

HA-5104 (PDIP, CERDIP)

HA-5114 (PDIP)

TOP VIEW

OUT1

-IN1

+IN1

V+

+IN2

-IN2

OUT2

1

1

2

-

+

3
4
5

+

-

6

2

7

14

4

13

-

+

12
11
10

+

-

3

HA5104/5114 (SOIC)

TOP VIEW

OUT1

-IN1

+IN1

V+

+IN2

-IN2

OUT2

NC

1

14

2

-

+

3
4
5

+

-

6

23

7
8

16
15

-

+

14
13
12

+

­11

10

9
8

9

OUT4

-IN4
+IN4
V­+IN3

-IN3
OUT3

OUT4

-IN4
+IN4
V­+IN3

-IN3
OUT3
NC

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 1999

HA-5102, HA-5104, HA-5114

Absolute Maximum Ratings Thermal Information

Supply Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . 40V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V

Output Short Circuit Duration (Note 3). . . . . . . . . . . . . . . . Indefinite

SUPPLY

Operating Conditions

Temperature Range

HA-5102/5104-2. . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

HA-5102/5104/5114-5 . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC

HA-5104/5114-9. . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Maximumpower dissipation, including output load, must be designed tomaintainthe maximum junction temperature below 175oC for hermetic
packages, and below 150oC for plastic packages.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

3. Any one amplifier may be shorted to ground indefinitely.

Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)

8 Lead PDIP Package . . . . . . . . . . . . . 92 N/A

8 Lead CERDIP Package. . . . . . . . . . . 135 50

14 Lead CERDIP Package. . . . . . . . . . 80 30

14 Lead PDIP Package . . . . . . . . . . . . 86 N/A

SOIC Package (HA-5104, HA-5114) . . 96 N/A
Maximum Junction Temperature (Note 1, Hermetic Package) . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications V

PARAMETER

INPUT CHARACTERISTICS

Offset Voltage 25 - 0.5 2.0 - 0.5 2.5 - 0.5 2.5 mV

Offset Voltage Average Drift Full - 3 - - 3 - - 3 - µV/oC
Bias Current 25 - 130 200 - 130 200 - 130 200 nA

Offset Current 25 - 30 75 - 30 75 - 30 75 nA

Input Resistance 25 - 500 - - 500 - - 500 - kΩ
Common Mode Range Full ±12 - - ±12 - - ±12 - - V

TRANSFER CHARACTERISTICS

Large Signal Voltage Gain,
(V

= ±5V, RL = 2kΩ)

OUT

Common Mode Rejection Ratio (VCM= ±5.0V) Full 86 95 - 86 95 - 80 95 - dB
Small Signal Bandwidth, HA-5102/5104 (AV = 1) 25 - 8 - - 8 - - 8 - MHz
Gain Bandwidth Product, HA-5114 (AV = 10) 25 - 60 - - 60 - - 60 - MHz
Channel Separation (Note 4) 25 - 60 - - 60 - - 60 - dB

OUTPUT CHARACTERISTICS

Output Voltage Swing (RL = 10kΩ) Full ±12 ±13 - ±12 ±13 - ±12 ±13 - V

(RL = 2kΩ) Full ±10 ±12 - ±10 ±12 - ±10 ±12 - V
Output Current, (V
Full Power Bandwidth (Note 5) HA-5102/5104 25 16 47 - 16 47 - 16 47 - kHz

= ±5V) Full ±10 ±15 - ±10 ±15 - ±7 ±15 - mA

OUT

HA-5114 25 191 318 - 191 318 - 191 318 - kHz

= ±15V, Unless Otherwise Specified

SUPPLY

TEMP.

(oC)

Full - - 2.5 - - 3.0 - - 3.0 mV

Full - - 325 - - 325 - - 500 nA

Full - - 125 - - 125 - - 125 nA

25 100 250 - 100 250 - 80 250 - kV/V

Full 100 - - 100 - - 80 - - kV/V

HA-5102-2, -5

HA-5104-2, -5

HA-5114 -5

HA-5104-9
HA-5114-9

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

2

HA-5102, HA-5104, HA-5114

Electrical Specifications V

PARAMETER

Output Resistance 25 - 110 - - 110 - - 110 - Ω

STABILITY

Minimum Stable Closed Loop
Gain

TRANSIENT RESPONSE (Note 6)
Rise Time HA-5102/5104 25 - 108 200 - 108 200 - 108 200 ns

Overshoot HA-5102/5104 25 - 20 35 - 20 35 - 20 35 %

Slew Rate HA-5102/5104 25 1 3 - 1 3 - 1 3 - V/µs

Settling Time (Note 7) HA-5102/5104 25 - 4.5 - - 4.5 - - 4.5 - µs

NOISE CHARACTERISTICS (Note 8)
Input Noise Voltage f = 10Hz 25 - 9 25 - 9 25 - 9 25 nV/√Hz

Input Noise Current f = 10Hz 25 - 5.1 15 - 5.1 15 - 5.1 15 pA/√Hz

Broadband Noise Voltage f = DC to 30kHz 25 - 870 - - 870 - - 870 - nV

POWER SUPPLY CHARACTERISTICS

Supply Current (All Amps) 25 - 3.0 5.0 - 5.0 6.5 - 5.0 6.5 mA
Power Supply Rejection Ratio, (∆VS = ±5V) Full 86 100 - 86 100 - 80 100 - dB

NOTES:

4. Channel separation value is referred to the input of the amplifier. Input test conditions are: f = 10kHz; VIN = 100mV

5. Full power bandwidth is guaranteed by equation: .

6. Refer to Test Circuits section of the data sheet.

7. Settling time is measured to 0.1% of final value for a 1V input step, and AV= -10 for HA-5114, and a 10V input step, AV=-1for
HA-5102/5104.

8. The limits for these parameters are guaranteed based on lab characterization, and reflect lot-to-lot variation.

HA-5102/5104 Full 1 - - 1 - - 1 - - V/V
HA-5114 Full 10 - - 10 - - 10 - - V/V

HA-5114 25 - 48 100 - 48 100 - 48 100 ns

HA-5114 25 - 30 40 - 30 40 - 30 40 %

HA-5114 25 12 20 - 12 20 - 12 20 - V/µs

HA-5114 25 - 0.6 - - 0.6 - - 0.6 - µs

f = 1kHz 25 - 4.3 6.0 - 4.3 6.0 - 4.3 6.0 nV/√Hz

f = 1kHz 25 - 0.57 3 - 0.57 3 - 0.57 3 pA/√Hz

= ±15V, Unless Otherwise Specified (Continued)

SUPPLY

TEMP.

(oC)

Full power bandwidth

HA-5102-2, -5

Slew Rate

---------------------------- -=

2πV

PEAK

HA-5104-2, -5

HA-5114 -5

HA-5104-9
HA-5114-9

; RS = 1kΩ.

PEAK

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

RMS

3

Test Circuits and Waveforms

2kΩ

HA-5102, HA-5104, HA-5114

HA-5102, HA-5104

IN

2kΩ

-

+

1kΩ

Vertical = 5V/Div., Horizontal = 5µs/Div. (AV = -1)

50pF

INPUT

OUTPUT

OUT

+5V

0V

-5V

+5V

0V

-5V

IN

OUTPUT

200mV

INPUT

0V

Vertical = 40mV/Div., Horizontal = 50ns/Div. (AV = +1)

+

-

2kΩ

FIGURE 1. LARGE SIGNAL RESPONSE CIRCUIT FIGURE 2. SMALL SIGNAL RESPONSE CIRCUIT

HA-5114

50pF

INPUT

OUTPUT

+0.5V

0V

-0.5V

+5V

0V

-5V

OUTPUT

INPUT

Input = 0.5V/Div., Output = 5V/Div., Time = 500ns/Div. Input = 10mV/Div., Output = 50mV/Div., Time = 50ns/Div.

4

200mV

0V

HA-5102, HA-5104, HA-5114

Test Circuits and Waveforms (Continued)

+15V

IN

+

-

1.8kΩ

50pF

200Ω

NOTE: AV = +10.

FIGURE 3. LARGEAND SMALL SIGNAL RESPONSE

CIRCUIT (AV = +10)

Simplified Schematic

V+

OUT

2N4416

5kΩ

500Ω (NOTE 9)

V

IN

200Ω (NOTE 9)

2kΩ

5kΩ

+15V

+

-

-15V

2kΩ

TO
OSCILLOSCOPE

2kΩ

V

OUT

50pF

NOTES:

9. AV = -1 (HA-5102/5104), AV = -10 (HA-5114).

10. Feedback and summing resistors should be 0.1% matched.

11. Clipping diodes are optional, HP5082-2810 recommended.

FIGURE 4. SETTLING TIME CIRCUIT

OUTPUT

V-

-INPUT+INPUT

5

Typical Performance Curves

15

VS = ±15V, TA = 25oC

HIGH

10

TYPICAL

LOW

5

NOISE VOLTAGE (nV/√Hz)

HA-5102, HA-5104, HA-5114

10

VS = ±15V, TA = 25oC

5.0

1.0

0.5

NOISE CURRENT (pA/√Hz)

0

10 100 1K

FREQUENCY (Hz)

FIGURE 5. INPUT NOISE VOLTAGE DENSITY

VS = ±15V, TA = 25oC, 50µV/Div., 1s/Div., AV = 1000V/V

Input Noise = 0.232µV

P-P

FIGURE 7. 0.1Hz TO 10Hz NOISE

0.1
10 100 1K

FREQUENCY (Hz)

FIGURE 6. INPUT NOISE CURRENT DENSITY

VS = ±15V, TA = 25oC, 500µV/Div., 1s/Div., AV = 1000V/V

Total Output Noise = 2.075µV

P-P

FIGURE 8. 0.1Hz TO 1MHz NOISE

2.0

1.5

1.0

0.5

INPUT OFFSET VOLTAGE (mV)

0

-60 20 1201008060400-20-40

V

= ±15V

S

TEMPERATURE (oC)

FIGURE 9. VIO vs TEMPERATURE

6

2.0

1.5

1.0

0.5

OFFSET VOLTAGE (mV)

0

08 1816141210642

TA = 25oC

SUPPLY VOLTAGE (±V)

FIGURE 10. VIO vs V

S

HA-5102, HA-5104, HA-5114

Typical Performance Curves (Continued)

4
2

VS = ±15V

0

-2

-4

-6

-8

-10

-12

-14

-16

-18

-20

INPUT OFFSET CURRENT (nA)

-22

-24

-26

-60 20 1201008060400-20-40
TEMPERATURE (oC)

FIGURE 11. IIO vs TEMPERATURE FIGURE 12. I

5

VS = ±15V, I

4

3

OUT

= 0

100

VS = ±15V

90
80
70
60
50
40
30

INPUT BIAS CURRENT (nA)

20
10

0

-60 20 1201008060400-20-40

5

TA = 25oC, I

4

3

OUT

= 0

TEMPERATURE (

vs TEMPERATURE

BIAS

o

C)

2

1

TOTAL SUPPLY CURRENT (mA)

0

-60 20 1201008060400-20-40

TEMPERATURE (oC)

2

1

TOTAL SUPPLY CURRENT (mA)

0

08 1816141210642

SUPPLY VOLTAGE (±V)

FIGURE 13. ICC vs TEMPERATURE (HA-5104/14) FIGURE 14. ICC vs VS (HA-5102)

5

VS = ±15V, ∆VO = ±10V, RL = 2kΩ

V/V)

5

4

3

2

1

OPEN LOOP VOLTAGE GAIN (10

0

-60 20 1201008060400-20-40
TEMPERATURE (

o

C)

5.5
VO = ±10V, VS = ±15V

5.0

V/V)

5

4.0

3.0

OPEN LOOP VOLTAGE GAIN (10

2.0

1K 10K8K6K4K2K

LOAD RESISTANCE (Ω)

125oC

25oC

-55oC

FIGURE 15. A

vs TEMPERATURE FIGURE 16. A

VOL

7

vs LOAD RESISTANCE

VOL

HA-5102, HA-5104, HA-5114

Typical Performance Curves (Continued)

290

TA = 25oC, RL = 2kΩ

280
270
260
250
240
230
220
210
200
190
180
170

OPEN LOOP GAIN (kV/V)

160
150
140
130

08 1816141210642

FIGURE 17. A

45

VS = ±15V, TA = 25oC

40

35

SUPPLY VOLTAGE (±V)

vs V

VOL

V

OUT

S

= -15V

13

TA = 25oC, RL = 2kΩ

12
11
10

9
8
7
6
5
4
3

MAX OUTPUT SWING (±V)

2
1
0

08 1816141210642

0

-20

-40

SUPPLY VOLTAGE (±V)

FIGURE 18. V

OUT

vs V

S

30

OUTPUT CURRENT (mA)

25

20

0 200 45040035030025015010050

V

= +15V

OUT

TIME (SECONDS)

-60

CMRR (dB)

-80

-100
1K 1M100K10K

FREQUENCY (Hz)

FIGURE 19. OUTPUT SHORT CIRCUIT CURRENT vs TIME FIGURE 20. CMRR vs FREQUENCY

0

-20

-40

-60

-80

POWER SUPPLY REJECTION (dB)

-100

+PSRR

-PSRR

1M100K10K1K

FREQUENCY (Hz)

6

VS = ±15V, RL = 2kΩ, CL = 50pF

0

-3

-6

-12

VOLTAGE GAIN (dB)

-18

-24

10K

125oC

GAIN

125oC

PHASE

FREQUENCY (Hz)

-55oC

PHASE

-55oC
GAIN

225

135

45

0

-45

PHASE SHIFT (DEGREES)

-135

-225

40M10M1M100K

FIGURE 21. PSRR vs FREQUENCY FIGURE 22. HA-5104/02 UNITY GAIN FREQUENCY RESPONSE

8

HA-5102, HA-5104, HA-5114

Typical Performance Curves (Continued)

25

A

VCL

20
15
10

5
0

-5

-10

VOLTAGE GAIN (dB)

-15

-20

-25

= +10, TA = 25oC, RL = 2kΩ, CL = 50pF

GAIN

PHASE

1M100K10K1K 10M 100M100

FREQUENCY (Hz)

0
45
90
135

PHASE SHIFT (DEGREES)

180

120
100

80
60

HA-5102/5104

40
20

VOLTAGE GAIN (dB)

0

HA-5102/5104
PHASE

GAIN

VS= ±15V, TA = 25oC,

R

L

HA-5114
GAIN

HA-5114
PHASE

FREQUENCY (Hz)

= 2kΩ, CL = 50pF

1M100K10K1K 10M 100M100

FIGURE 23. HA-5114 FREQUENCY RESPONSE FIGURE 24. OPEN LOOP GAIN vs FREQUENCY

60

VS = ±15V, TA = 25oC, RL = 2kΩ

50

40

30

20

OVERSHOOT (%)

10

1.1
RL = 2kΩ, CL = 50pF, VS = ±15V

1.0

0.9

0.8

0.7

SLEW RATE (NORMALIZED)

0
45
90
135

PHASE SHIFT (DEGREES)

180

0

10 100 1K 10K

LOAD CAPACITANCE (pF)

FIGURE 25. SMALL SIGNAL OVERSHOOT vs C

1.1

1.0

0.9

0.8

0.7

RISE TIME (NORMALIZED)

0.6

-60 20 1201008060400-20-40

LOAD

FIGURE 27. RISE TIME vs TEMPERATURE

0.6

-60 20 1201008060400-20-40

FIGURE 26. SLEW RATE vs TEMPERATURE

RL = 2kΩ, CL = 50pF, VS = ±15V

TEMPERATURE (

o

C)

TEMPERATURE (oC)

9

HA-5102, HA-5104, HA-5114

Die Characteristics

DIE DIMENSIONS:

98.4 mils x 67.3 mils x 19 mils
2500µm x 1710µm x 483µm

METALLIZATION:

Type: Al, 1% Cu
Thickness: 16k

Å ±2kÅ

Metallization Mask Layout

V- +IN1 -IN1 OUT1

HA-5102

PASSIVATION:

Type: Nitride (Si
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ

SUBSTRATE POTENTIAL (POWERED UP):

Unbiased

TRANSISTOR COUNT:

93

PROCESS:

Bipolar Dielectric Isolation

) over Silox (SiO2, 5% Phos.)

3N4

+IN2 -IN2 OUT2 V+

10

Die Characteristics

HA-5102, HA-5104, HA-5114

DIE DIMENSIONS:

95 mils x 99 mils x 19 mils
2420µm x 2530µm x 483µm

METALLIZATION:

Type: Al, 1% Cu
Thickness: 16k

Å ±2kÅ

PASSIVATION:

Type: Nitride (Si
Silox Thickness: 12k

) over Silox (SiO2, 5% Phos.)

3N4

Å ±2kÅ

Nitride Thickness: 3.5kÅ ±1.5kÅ

Metallization Mask Layout

-IN2

OUT2
OUT3

SUBSTRATE POTENTIAL (POWERED UP):

Unbiased

TRANSISTOR COUNT:

175

PROCESS:

Bipolar Dielectric Isolation

HA-5104

+IN2 V+ +IN1

-IN1

OUT1

OUT4

-IN3

-IN2

OUT2

OUT3

-IN3

-IN4

+IN4V-+IN3

HA-5114

+IN2 V+ +IN1

-IN1

OUT1

OUT4

-IN4

11

+IN4V-+IN3

HA-5102, HA-5104, HA-5114

Dual-In-Line Plastic Packages (PDIP)

N

D1

-C-

E1

-B-

A2

A

L

A

1

e

C

e

e

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

1 2 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. ControllingDimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbolsaredefinedin the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. DimensionsA, A1 and L are measured withthepackage seated
in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru­sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).

6. E and are measured with the leads constrained to be per-

e

pendicular to datum .

A

-C-

7. eB and eC are measured at the lead tips with the leads uncon­strained. eC must be zero or greater.

8. B1 maximum dimensions do not includedambarprotrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4

E

A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

C

L

A

C

B

B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 ­D 0.355 0.400 9.01 10.16 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89

NOTESMIN MAX MIN MAX

Rev. 0 12/93

12

HA-5102, HA-5104, HA-5114

Dual-In-Line Plastic Packages (PDIP)

N

D1

-C-

E1

-B-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

1 2 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict betweenEnglish
and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols aredefinedin the “MOSeries Symbol List”in Section 2.2of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpen-

e

dicular to datum .

A

-C-

7. eB and eC are measured at the lead tips with the leads uncon­strained. eC must be zero or greater.

8. B1maximumdimensionsdonot includedambarprotrusions.Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -

1.14mm).

E14.3 (JEDEC MS-001-AA ISSUE D)

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.15 1.77 8

C 0.008 0.014 0.204 0.355 -

D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N14 149

NOTESMIN MAX MIN MAX

Rev. 0 12/93

13

HA-5102, HA-5104, HA-5114

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

c1

LEAD FINISH

-A-

-B-

bbb C A - B

S

BASE

PLANE

SEATING

PLANE

S1

b2

b

ccc C A - BMD

D

A

A

e

S

S

NOTES:

1. Index area:A notch ora pinoneidentification markshall belocat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 andc1apply to leadbasemetal only. Dimension
M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle.Forthis configuration dimension b3 replaces
dimension b2.

5. This dimension allows for off-center lid, meniscus, andglass
overrun.

6. Dimension Q shall be measured from the seating plane to the
base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH

-D­BASE

E

D

S

S

Q

A

-C­L

METAL

b1

M

(b)

SECTION A-A

α

(c)

M

eA

eA/2

aaa C A - B

M

c

D

S

S

F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)

8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.200 - 5.08 -

b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 ­b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3

D - 0.405 - 10.29 5

E 0.220 0.310 5.59 7.87 5

e 0.100 BSC 2.54 BSC -

eA 0.300 BSC 7.62 BSC -

eA/2 0.150 BSC 3.81 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6

S1 0.005 - 0.13 - 7

o

α

90

105

o

90

o

105
aaa - 0.015 - 0.38 ­bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3

N8 88

NOTESMIN MAX MIN MAX

o

Rev. 0 4/94

-

14

HA-5102, HA-5104, HA-5114

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

LEAD FINISH

c1

-A-

-B-

bbb C A - B

S

BASE

PLANE

SEATING

PLANE

S1

b2

b

ccc C A - BMD

D

A

A

e

S

S

NOTES:

1. Index area:A notch ora pinoneidentification markshall belocat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 andc1apply to leadbasemetal only. Dimension
M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle.Forthis configuration dimension b3 replaces
dimension b2.

5. This dimension allows for off-center lid, meniscus, andglass
overrun.

6. Dimension Q shall be measured from the seating plane to the
base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

-D­BASE

E

D

S

S

Q

A

-C­L

METAL

b1

M

(b)

SECTION A-A

α

(c)

M

eA

eA/2

aaa C A - B

M

c

D

S S

F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)

14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.200 - 5.08 -

b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 ­b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3

D - 0.785 - 19.94 5
E 0.220 0.310 5.59 7.87 5

e 0.100 BSC 2.54 BSC ­eA 0.300 BSC 7.62 BSC -

eA/2 0.150 BSC 3.81 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6

S1 0.005 - 0.13 - 7

o

α

90

105

o

90

o

105
aaa - 0.015 - 0.38 ­bbb - 0.030 - 0.76 ­ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3

N14 148

NOTESMIN MAX MIN MAX

o

Rev. 0 4/94

-

15

HA-5102, HA-5104, HA-5114

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45

o

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”,as measured 0.36mm (0.014 inch)or greater above
the seating plane,shall not exceed a maximum valueof0.61mm (0.024
inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensionsare
not necessarily exact.

A1

C

0.10(0.004)

M16.3 (JEDEC MS-013-AA ISSUE C)

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 ­h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly ,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

16

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
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Republic of China
TEL: [phone]
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