Intersil Corporation HA457 Datasheet

HA457

Data Sheet August 1999

95MHz, Low Power, AV = 2, 8 x 8 Video
Crosspoint Switch

The HA457 is an 8 x 8 video crosspoint switch suitable for
high performance video systems. Its high level of integration
significantly reduces component count, board space, and
cost. The crosspoint switch contains a digitally controlled
matrix of 64 fully buffered switches that connect eight video
input signalsto any, or all, matrix outputs. Each matrix output
connects to an internal, high-speed (275V/µs), gain of two
buffer capable of driving 150Ω to ±2.5V.

The HA457 will directly drive a double terminated video
cable with some degradation of differential gain and phase.
Applications demanding the best composite video
performance should drive the cable with a unity gain video
buffer, such as the HFA1412 quad buffer (see Figure 7).

This crosspoint’s three-state output capability makes it
feasible to parallel multiple HA457s and form larger switch
matrices.

File Number 4231.2

Features

• Pin Compatible, Cable Driving Upgrade for HA456 and
MAX456

• Fully Buffered Inputs and Outputs (A

= +2)

V

• Routes Any Input Channel to Any Output Channel

• Switches Standard and High Resolution Video Signals

• Serial or Parallel Digital Interface

• Expandable for Larger Switch Matrices

• Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 95MHz

• High Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . 275V/µs

• Low Crosstalk at 10MHz . . . . . . . . . . . . . . . . . . . . -55dB

Applications

• Video Switching and Routing

• Security and Video Editing Systems

Ordering Information

TEMP.

PART NUMBER

HA457CN 0 to 70 44 Ld MQFP Q44.10x10
HA457CM 0 to 70 44 Ld PLCC N44.65

RANGE (oC) PACKAGE PKG. NO.

Pinouts

DGND

DGND

EDGE/

LEVEL

A0

IN1

NC

IN2

NC

IN3

IN4

IN5

HA457 (MQFP)

TOP VIEW

IN0A1A2

44 43 42 41 40

1

2
3
4
5
6
7
8
9

10
11

12 13 14 15 16 17

V+

IN6

D0/SER IN

IN7

PAR
SER/

D1/SER OUT

NCV+OUT0D2OUT1

39 38 37 36 35 34

V-

NC

WR

CE

LATCH

CE

2221201918

D3

33
32
31
30
29

28
27
26
25
24
23

OUT7

OUT2
V-

OUT3
AGND
OUT4

NC
AGND
OUT5

AGND
OUT6
V+

EDGE/

A0

IN1

NC

IN2

DGND

NC

IN3

DGND

IN4

LEVEL

IN5

HA457 (PLCC)

IN0A1A2

7
8

9
10
11
12
13
14
15
16
17

V+

IN6

TOP VIEW

D0/SER IN

D1/SER OUT

123456

V-

IN7

PAR
SER/

NCV+OUT0D2OUT1

44 43 42 41 40

NC

WR

262524232221201918

LATCH

CE

D3

2827

CE

39
38
37

36
35
34
33
32
31
30
29

OUT7

OUT2
V­OUT3

AGND
OUT4
NC

AGND
OUT5
AGND

OUT6
V+

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 1999

Functional Block Diagram

IN0 IN2 IN3 IN4 IN5 IN6 IN7IN1

HA457

OUTPUT

BUFFERS

= 2)

(A

V

HA457

8 x 8

SWITCH

MATRIX

SLAVE REGISTER

EN0:7

EN7

-

+

EN0

-

+

LATCH
EDGE/

LEVEL

OUT0

OUT7

SER/PAR

D0/SER IN

MASTER REGISTER

A0 A1 A2 D2 D3

2

WR
CE

CE

D1/SER OUT

HA457

Pin Descriptions

PIN

NAME FUNCTIONMQFP PLCC

3, 6, 17, 28, 39 1, 9, 12, 23, 34 NC No connect. Not internally connected.

40 2 D1/ SER OUT Parallel Data Bit input D1 for parallel programming mode. Serial Data Output (MSB of shift

register) for cascading multiple HA457s in serial programming mode. Simply connect
Serial Data Out of one HA457 to Serial Data In of another HA457 to daisy chain multiple
devices.

41 3 D0/SER IN Parallel Data Bit input D0 for parallel programming mode. Serial Data Input (input to shift

register) for serial programming mode.

42, 43, 1 4, 5, 7 A2, A1, A0 OutputChannelAddressBits.These inputs select the output being programmed in parallel

programming mode.

44, 2, 4, 7, 9, 11,

13, 15

5, 8 11, 14 DGND Digital Ground. Connect both DGND pins to AGND.

10 16 EDGE/LEVEL A user strapped input that defines whether synchronous channel switching is edge or level

12, 23, 38 18, 29, 44 V+ Positive supply voltage. Connect all V+ pins together and decouple each pin to AGND

14 20 SER/PAR A user strapped input that defines whether the serial (SER/PAR=1) or parallel

16, 32 22, 38 V- Negative supply voltage. Connect both V- pins together and decouple each pin to AGND

18 24 WR WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from

19 25 LATCH Synchronous channel switch control input. If EDGE/LEVEL = 1, data is loaded from the

6, 8, 10, 13,

15, 17, 19, 21

IN0-IN7 Analog Video Input Lines.

controlled. With this pin strapped high, the slave register loads from the master register
(thus changing the switch matrix state) on the rising edge of the LATCH signal. If it is
strapped low (level mode), the slave register is transparent while LATCH is low, passing
datadirectlyfromthe master registertotheswitch state decoders. StrappingEDGE/LEVEL
and LATCH low causes the channel switch to execute on the WR rising edge (not
recommended for serial mode operation).

(Figure 6).

(SER/PAR=0) digital programming interface is being utilized.

(Figure 6).

SER IN on the WR rising edge. In parallel mode, the Master Register loads with D3:0 (iff
D3:0=0000 through 1000), or theappropriateactionis taken (iff D3:0=1011 through1111),
on the WR rising edge (see Table 1).

Master Register to the Slave Register on the rising edge of LATCH. If EDGE/LEVEL = 0,
data is loaded from the Master to the Slave Register while LATCH = 0. In parallel mode,
commands 1011 through 1110 execute asynchronously, on the WR rising edge,
regardless of the state of LATCH or EDGE/LEVEL. Parallel mode command 1111
executes a software “Latch” (see Table 1).

20 26 CE Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.

21 27 CE Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.

22, 24, 26, 29,

31, 33, 35, 37

25, 27, 30 31, 33, 36 AGND Analog Ground.

34 40 D3 Parallel Data Bit Input D3 when SER/PAR = 0. D3 is unused with serial programming.

36 42 D2 Parallel Data Bit Input D2 when SER/PAR = 0. D2 is unused with serial programming.

28, 30, 32, 35,

37, 39, 41, 43

OUT7-OUT0 Analog Video Outputs.

3

HA457

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V

Positive Supply Voltage (V+) Referred to AGND . . . . . . . . . . . . . 6V

Negative Supply Voltage (V-) Referred to AGND. . . . . . . . . . . . -6V

DGND Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AGND ±1V

Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±V

SUPPLY

Digital Input Voltage. . . . . . . . . . . . . . (V+ + 0.3V) to (DGND - 0.3V)

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7). . . 1.6kV

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . .±4.5V to ±5.5V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA(oC/W)

PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . .175oC

Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature, Soldering 10s . . . . . . . . . . . . . 300oC

(Lead Tips Only)

Electrical Specifications V

= ±5V, AGND = DGND = 0V, RL = 400Ω (Note 2), Unless Otherwise Specified.

SUPPLY

(NOTE 3)

PARAMETER TEST CONDITIONS

Voltage Gain V

=-0.75Vto+0.75V, Worst Case

IN

Switch Configuration,
RL = 150Ω

TEST

LEVEL

TEMP

(oC) MIN TYP MAX UNITS

A 25 1.93 1.97 2.10 V/V
A Full - - -

Channel-to-Channel Gain Mismatch A 25 - 0.04 0.1 V/V

A Full - - -

Supply Current All Outputs Enabled, R

VIN = 0V,
Total for All V+ (3) or V- (2) Pins

Disabled Supply Current All Outputs Disabled, R

Total for All V+ (3) or V- (2) Pins

= Open,

L

= Open,

L

A 25 - 68 80 mA
A Full - 71 83

A 25 - 47 65 mA

A Full - 47 67
Input Voltage Range A Full ±2 ±2.5 - V
Analog Input Current V
Input Noise (R

=75Ω) DC to 40MHz B 25 - 0.15 - mV

S

= 0V A Full - 1.6 12 µA

IN

≥10kHz B 25 - 22 - nV/√Hz
Analog Input Resistance DC C 25 - 4 - MΩ
Analog Input Capacitance (Input Connected to

One Output or All Outputs, Note 6)
Input Offset Voltage V

Channel-to-Channel Input Offset Voltage
Mismatch

PLCC Package B 25 - 3.2 - pF

MQFP Package B 25 - 2.5 - pF

= 0V, Worst Case Switch

IN

Configuration

A 25 -18 -12 5 mV
A Full -20 -15 6
A25-411mV

A Full - 8 ­Input Offset Voltage Drift B Full - 20 - µV/
Output Voltage Swing V

= ±1.33V, RL = 150Ω A25±2.45 ±2.6 - V

IN

A Full - - - V
Output Resistance Enabled, DC B 25 - 0.25 - Ω

Output Disabled A 25 1.5 2 - kΩ

Output Capacitance
(Output Disabled)

Power Supply Rejection Ratio DC, V
Digital Input Current (Note 5) V

PLCC Package B 25 - 3.5 - pF
MQFP Package B 25 - 2.9 - pF

= ±4.5V to ±5.5V, VIN = 0V A Full 45 53 - dB

S

= 0V or 5V A Full - - 1 µA

IN

RMS

o

C

4

HA457

Electrical Specifications V

= ±5V, AGND = DGND = 0V, RL = 400Ω (Note 2), Unless Otherwise Specified. (Continued)

SUPPLY

(NOTE 3)

PARAMETER TEST CONDITIONS

TEST

LEVEL

TEMP

(oC) MIN TYP MAX UNITS

Digital Input Low Voltage A Full - - 0.8 V
Digital Input High Voltage A 25 2.0 - - V

A Full 2.2 - - V
SER OUT Logic Low Voltage Serial Mode, I
SER OUT Logic High Voltage Serial Mode, I
SER OUT Leakage Current Output Disabled, V

= 1.6mA A Full - - 0.4 V

OL

= -0.4mA A Full 3.0 - - V

OH

= 2.5V A 25 - 0.2 5 µA

OUT

A Full - 1 10 µA
AC CHARACTERISTICS (Note 4)

-3dB Bandwidth (Note 6) V

Slew Rate (Note 6) V
All Hostile Crosstalk (Note 6) 10MHz, V

All Hostile Off Isolation (Note 6) 10MHz, V

= 200mV

OUT

= 1V

V

OUT

= 2V

V

OUT

= 2V

V

OUT

= 4V

OUT

10MHz, V

10MHz, V

P-P
P-P

, RL= 150Ω B 25 - 50 - MHz

P-P

, RL = 150Ω B 25 - 275 - V/µs

P-P

= 1V

IN

= 1V

IN

= 1V

IN

= 1V

IN

Differential Phase NTSC or PAL, R

NTSC or PAL, R
NTSC or PAL, R

Differential Gain NTSC or PAL, R

NTSC or PAL, R
NTSC or PAL, R

P-P

, RL= 150Ω B 25 - -55 - dB

P-P

, RL = 1kΩ B 25 - -58 - dB

P-P

, RL = 150Ω B 25 - 95 - dB

P-P

, RL = 1kΩ B 25 - 75 - dB

P-P

= 150Ω B 25 - 0.5 - DEG

L

= 1kΩ B 25 - 0.05 - DEG

L

≥ 10kΩ B 25 - 0.05 - DEG

L

= 150Ω B 25 - 0.05 - %

L

= 1kΩ B 25 - 0.05 - %

L

≥ 10kΩ B 25 - 0.02 - %

L

B 25 - 95 - MHz

B 25 - 75 - MHz

B 25 - 60 - MHz

TIMING CHARACTERISTICS (See Figure 8 for more information)
Write Pulse Width High (t
Write Pulse Width Low (t
Chip-Enable Setup Time to Write (t
Chip-Enable Hold Time From Write (t
Data and Address Setup Time to Write (t

) A Full 20 - - ns

WH

) A Full 20 - - ns

WL

) A Full 5 - - ns

CS

) A Full 5 - - ns

CH

) Parallel Mode A Full 20 - - ns

DS

Serial Mode A Full 20 - - ns
Data and Address Hold Time From Write (t
Latch Pulse Width (t
Latch Delay From Write (t
LATCH Edge to Output Disabled (t
LATCH Edge to Output Enabled (t

) A Full 40 - - ns

L

) A Full 40 - - ns

D

OFF

ON

Output Break-Before-Make Delay
(t

ON -tOFF

)

) A Full 25 - - ns

DH

) Serial Mode B Full - 30 - ns

) Serial Mode B Full - 185 - ns

Serial Mode B Full - 155 - ns

NOTES:

2. For the lowest crosstalk, and the best composite video performance, use R

≥ 1kΩ.

L

3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.

4. See AC Test Circuits (Figure 1 through Figure 4).

5. Excludes D1/SER OUT which is a bidirectional terminal and thus falls under the higher Output Leakage limit.

6. See Typical Performance Curves for more information.

5