intersil EL9200, EL9201, EL9202 DATA SHEET

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®

EL9200, EL9201, EL9202

Data Sheet April 7, 2005

Programmable V

The EL9200, EL9201, and EL9202 represent programmable
V

amplifiers for use in TFT-LCD displays. Featuring 1,

COM

2, and 4 channels of V
device features just a single programmable current source
for adding offset to one V
programmable using a single wire interface to one of 128
levels. The value is stored on an internal EEPROM memory.

The EL9200 is available in the 12-pin DFN package and the
EL9201 and EL9202 are available in 24-pin QFN packages.
All are specified for operation over the -40°C to +85°C
temperature range.

COM

amplification, respectively, each

COM

output. This current source is

COM

Typical Block Diagram

R

F

A

VDD

V

SD

CE

VS+

EEPROM

INN

V

-

+

OUT

INP

GND

FN7438.0

Features

• 128 step adjustable sink current

• EEPROM memory

• 2-pin adjustment and disable

• Single, dual or quad amplifiers

- 44MHz bandwidth

- 80V/µs slew rate

- 60mA continuous output

- 180mA peak output

• Up to 18V operation

• 2.6V to 3.6V logic control

• Pb-free available (RoHS compliant)

R

G

A

VDD

R

1

R

2

Applications

•TFT-LCD V

-LCD-TVs

- LCD monitors

COM

supplies for

CTL

CONTROL

GND SET

UP/DOWN
COUNTER

ANALOG

POT

R

SET

I

OUT

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2005. All Rights Reserved.

Pinouts

1

VINA-

EL9200

(12-PIN DFN)

TOP VIEW

EL9200, EL9201, EL9202

EL9201

(24-PIN QFN)

TOP VIEW

NC

GND

NC

VINA+

VINA-

24

23

22

21

20

12

VS+

NC

1

19

NC

VOUTA

1

EL9202

(24-PIN QFN)

TOP VIEW

VINA-

VINA+

24

23

VS+

VINB+

VINB-

22

21

20

19

VOUTB

GND

VINA+

IOUT

AVD D

GND

2

3

4

5

6

THERMAL

PAD

11

10

9

8

7

VOUTA

SET

CE

CTL

VSD

NC

VINB+

IOUT

NC

AVD D

GND

11

VSD

18

VOUTA

17

VS+

16

VOUTB

15

VINB-

14

SET

13

CE

12

CTL

VOUTD

VIND-

NC

VIND+

AVD D

CTL

2

3

8

CE

THERMAL

PAD

9

10

NC

SET

4

5

6

7

11

IOUT

12

NC

18

17

16

15

14

13

VOUTC

VINC-

NC

VINC+

GND

AVD D

2

3

8

NC

THERMAL

PAD

9

10

NC

NC

4

5

6

7

Ordering Information

PART NUMBER PACKAGE

EL9200IL 12-Pin DFN - MDP0047 EL9201ILZ

EL9200IL-T7 12-Pin DFN 7” MDP0047 EL9201ILZ-T7

EL9200IL-T13 12-Pin DFN 13” MDP0047 EL9201ILZ-T13

EL9200ILZ
(See Note)

EL9200ILZ-T7
(See Note)

EL9200ILZ-T13
(See Note)

12-Pin DFN

(Pb-Free)

12-Pin DFN

(Pb-Free)

12-Pin DFN

(Pb-Free)

EL9201IL 24-Pin QFN - MDP0046 EL9202ILZ

EL9201IL-T7 24-Pin QFN 7” MDP0046 EL9202ILZ-T7

EL9201IL-T13 24-Pin QFN 13” MDP0046 EL9202ILZ-T13

REEL PKG. DWG. # PART NUMBER PACKAGE

24-Pin QFN

(See Note)

(Pb-Free)

24-Pin QFN

(See Note)

(Pb-Free)

24-Pin QFN

(See Note)

(Pb-Free)

- MDP0047 EL9202IL 24-Pin QFN - MDP0046

7” MDP0047 EL9202IL-T7 24-Pin QFN 7” MDP0046

13” MDP0047 EL9202IL-T13 24-Pin QFN 13” MDP0046

24-Pin QFN

(See Note)

(Pb-Free)

24-Pin QFN

(See Note)

(Pb-Free)

24-Pin QFN

(See Note)

(Pb-Free)

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

TAPE &

TAPE &

REEL PKG. DWG. #

- MDP0046

7” MDP0046

13” MDP0046

- MDP0046

7” MDP0046

13” MDP0046

2

FN7438.0

April 7, 2005

EL9200, EL9201, EL9202

Absolute Maximum Ratings (T

V

+ Supply Voltage between VS+ and GND . . . . . . . . . . . . . .18V

S

Supply Voltage between V

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 65mA

Input Voltages to GND

SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V

CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V

and GND . . . . . . . . . . . . . . . . . . . .4V

SD

= 25°C)

A

A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V

VDD

ESD Rating - HBM for Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV

Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

Output Voltages to GND

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

= 3V, VS+ = 15V, A

SD

= TC = T

J

VDD

A

= 15V, R

= 24.9kΩ, and TA = 25°C unless otherwise specified

SET

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

V

S+

I

S+

Supply Voltage 4.5 16.5 V

Quiescent Current EL9200 3.8 4.8 mA

EL9201 7.6 9.6 mA

EL9202 10.5 16 mA

V

SD

Logic Supply Voltage For programming 3 3.6 V

For operation 2.6 3.6 V

I

SD

Quiescent Logic Current CE = 3.6V 50 µA

CE = GND 25 µA

Program (charge pump current) (Note 1) 23 mA

Read (Note 1) 3 mA

I

ADD

CTL

CTL

CTL

CTL

CTL

CTL

CTL

IH

IL

IHRPW

ILRPW

IHMPW

ILMPW

MTC

Supply Current Note 2 25 µA

CTL High Voltage 2.6V < VSD < 3.6V 0.7*V

CTL Low Voltage 2.6V < VSD < 3.6V 0.2*V

SD

SD

0.8*V

0.3*V

SD

SD

CTL High Rejected Pulse Width 20 µs

CTL Low Rejected Pulse Width 20 µs

CTL High Minimum Pulse Width 200 µs

CTL Low Minimum Pulse Width 200 µs

CTL Minimum Time Between Counts 10 µs

V

V

ICTL CTL Input Current CTL = GND 10 µA

CTL

CE

CE

CE

CTL

CTL

P

T

EE

SET

CAP

IL

IH

ST

PROM

PT

WC

DN

CTL = V

SD

CTL Input Capacitance 10 pF

CE Input Low Voltage 2.6V < VSD < 3.6V 0.4 V

CE Input High Voltage 2.6V < VSD < 3.6V 1.6 V

CE Minimum Start Up Time (Note 1) 1 ms

CTL EEPROM Program Voltage 2.6V < VSD < 3.6V (Note 2) 4.9 15.75 V

CTL EEPROM Programming Signal

> 4.9V 200 µs

Time

Programming Time 100 ms

EE Write Cycles Guaranteed by design 1000 cycles

SET Differential Nonlinearity Monotonic over-temperature ±1LSB

10 µA

3

FN7438.0

April 7, 2005

EL9200, EL9201, EL9202

Electrical Specifications V

= 3V, VS+ = 15V, A

SD

VDD

= 15V, R

= 24.9kΩ, and TA = 25°C unless otherwise specified

SET

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

SET

ZSE

SET

FSE

I

SET

SET

ER

A

to SET A

VDD

OUT

ST

V

OUT

SET Zero-Scale Error Note 3 ±2LSB

SET Full-Scale Error Note 3 ±8LSB

SET Current Through R

SET External Resistance To GND, A

To GND, A

to SET Voltage Attenuation 1:20 V/V

VDD

(Note 1) 120 µA

SET

= 20V (Note 1) 10 200 kΩ

VDD

= 4.5V (Note 1) 2.25 45 kΩ

VDD

OUT Settling Time To ±0.5 LSB error band (Note 1) 20 µs

OUT Voltage Range (Note 1) V

SET

+

13 V

0.5V

OUT

VD

OUT Voltage Drift (Note 1) 10 mV

AMPLIFIER CHARACTERISTICS

INPUT CHARACTERISTICS

V

OS

TCV

OS

I

B

R

IN

C

IN

CMRR Common-Mode Rejection Ratio For V

A

VOL

Input Offset Voltage VCM = 0V 3 15 mV

Average Offset Voltage Drift (Note 1) 7 µV/°C

Input Bias Current VCM = 0V 2 60 nA

Input Impedance 1GΩ

Input Capacitance 2pF

from -5.5V to +5.5V 50 70 dB

IN

Open-Loop Gain -4.5V ≤ V

≤ +4.5V 60 70 dB

OUT

OUTPUT CHARACTERISTICS

V

V

I

SC

I

OUT

OL

OH

Output Swing Low RL = 1.5kΩ to 0 0.09 0.15 V

Output Swing High 14.85 14.9 V

Short-Circuit Current ±150 ±180 mA

Output Current ±65 mA

POWER SUPPLY PERFORMANCE

PSRR Power Supply Rejection Ratio V

is moved from 4.5V to 15.5V 55 80 dB

S+

DYNAMIC PERFORMANCE

SR Slew Rate (Note 4) -4.0V ≤ V

t

S

Settling to +0.1% (AV = +1) (AV = +1), V

≤ 4.0V, 20% to 80% 60 80 V/µs

OUT

= 2V step 80 ns

OUT

BW -3dB Bandwidth 44 MHz

GBWP Gain-Bandwidth Product 32 MHz

PM Phase Margin 50 °

CS Channel Separation f = 5MHz (EL9201 & EL9202 only) 110 dB

d

G

d

P

Differential Gain (Note 5) RF = RG = 1kΩ and V

Differential Phase (Note 5) RF = RG = 1kΩ and V

= 1.4V 0.17 %

OUT

= 1.4V 0.24 °

OUT

NOTES:

1. Simulated and determined via design and not directly tested

2. Tested at A

VDD

= 20V

3. Wafer sort only

4. NTSC signal generator used

4

FN7438.0

April 7, 2005

EL9200, EL9201, EL9202

Pin Descriptions

PIN IN/OUT DESCRIPTION EQUIVALENT CIRCUIT

VINX- Input Amplifier X inverting input, where:

VINX+ Input Amplifier X non-inverting input, where:

VS+ Supply Op amp supply; bypass to GND with 0.1µF capacitor

VOUTX Output Amplifier X output, where:

X = A for EL9200
X = A, B for EL9201
X = A, B, C, D for EL9202

Reference Circuit 1
X = A for EL9200
X = A, B for EL9201
X = A, B, C, D for EL9202

X = A for EL9200
X = A, B for EL9201
X = A, B, C, D for EL9202

CIRCUIT 1

V

S+

GND

V

S+

NC - No connect; not internally connected

GND Supply Ground connection

IOUT Output Adjustable sink current output pin; the current sinks into the

OUT pin is equal to the DAC setting times the maximum
adjustable sink current divided by 128; see SET pin function
description for the maxim adjustable sink current setting

SET Output Maximum sink current adjustment point; connect a resistor

from SET to GND to set the maximum adjustable sink
current of the OUT pin; the maximum adjustable sink
current is equal to (A

/20) divided by R

VDD

SET

CE Input Counter enable pin; connect CE to VDD to enable counting

of the internal counter; connect CE to GND to inhibit
counting

CTL Input Internal counter up/down control and internal EEPROM

programming control input; if CE is high, a mid-to-low
transition increments the 7-bit counter, raising the DAC
setting, increasing the OUT sink current, and lowering the
divider voltage at OUT; a mid-to-high transition decrements
the 7-bit counter, lowering the DAC setting, decreasing the
OUT sink current, and increasing the divider voltage at
OUT; applying 4.9V and above with appropriately arranged
timing will overwrite EEPROM with the contents in the 7-bit
counter; see EEPROM Programming section for details

AVDD Supply analog voltage supply; bypass to GND with 0.1µF

capacitor

VSD Supply System power supply input; bypass to GND with 0.1µF

capacitor

GND

GND

CIRCUIT 2

5

FN7438.0

April 7, 2005