intersil EL9110 DATA SHEET

®

EL9110

Data Sheet November 30, 2007

Differential Receiver/Equalizer

The EL9110 is a single channel differential receiver and
equalizer. It contains a high speed differential receiver with 5
programmable poles. The outputs of these pole blocks are
then summed into an output buffer. The equalization length
is set with the voltage on a single pin. The EL9110 also
contains a three-statable output, enabling multiple devices to
be connected in parallel and used in a multiplexing
application.

The gain can be adjusted up or down by 6dB using the
V

control signal. In addition, a further 6dB of gain can

GAIN

be switched in to provide a matched drive into a cable.
The EL9110 has a bandwidth of 150MHz and consumes just

33mA on ±5V supply. A single input volt age is used to set the
compensation levels for the required length of cable.

The EL9110 is available in the 16 Ld QSOP package and is
specified for operation over the full -40°C to +85°C
temperature range.

Ordering Information

PART

NUMBER

EL9110IU 9110IU 16 Ld QSOP MDP0040
EL9110IU-T7* 9110IU 16 Ld QSOP MDP0040
EL9110IU-T13* 9110IU 16 Ld QSOP MDP0040
EL9110IUZ

(Note)
EL9110IUZ-T7*

(Note)
EL9110IUZ-T13*

(Note)
*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING PACKAGE PKG. DWG. #

9110IUZ 16 Ld QSOP

(Pb-free)

9110IUZ 16 Ld QSOP

(Pb-free)

9110IUZ 16 Ld QSOP

(Pb-free)

MDP0040

MDP0040

MDP0040

Features

• 150MHz -3dB bandwidth

• CAT-5 compensation

- 75MHz @ 1000ft

- 125MHz @ 500ft

• 33mA supply current

• Differential input range 3.2V

• Common mode input range ±4.5V

• ±5V supply

• Output to within 1.5V of supplies

• Available in 16 Ld QSOP package

• Pb-free available (RoHS compliant)

Applications

• Twisted-pair receiving/equalizer

• KVM (Keyboard/Video/Mouse)

• VGA over twisted-pair

• Security video

Pinout

EL9110

(16 LD QSOP)

TOP VIEW

CTRL_REF

CMOUT

LOGIC_REF

1

VCTRL

2

3

VINP

VINM

4

VS-

5

6

VGAIN

7

8 9

16

15

14

13

12

11

10

FN7305.5

CMEXT

VS+

ENBL

VSA+

VOUT

VSA-

0V

X2

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2003, 2005, 2007. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

EL9110

Absolute Maximum Ratings (T

Supply Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . . .12V

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . V

= +25°C) Thermal Information

A

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

- -0.5V to VS+ +0.5V

S

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

= VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, Unless Otherwise Specified

SA+

PARAMETER DESCRIPTION CONDITIONS

= TC = T

J

A

MIN

(Note 1) TYP

MAX

(Note 1) UNIT

AC PERFORMANCE

BW Bandwidth (See Figure 1) 150 MHz
SR Slew Rate V
THD Total Harmonic Distortion 10MHz 1V

= -1V to +1V , VG = 0.35, VC = 0, RL = 75 + 75Ω 1.5 V/ns

IN

out, VG = 0.35V, X2 gain, VC = 0 -50 dBc

P-P

DC PERFORMANCE

V

OS

Offset Voltage (bin #1) X2 gain, no equalization -250 -10 +250 mV
Offset Voltage (bin #2) CPI9049 mV

INPUT CHARACTERISTICS

CMIR Common-mode Input Range Common-mode extension off -4/+3.5 V
CMIRx Extended CMIR Common-mode extension on ±4.5 V
O

NOISE

Output Noise VG = 0.35, X2 gain, 75 + 75Ω load, VC = 0.6 25 mV

RMS
CMRR Common-mode Rejection Ratio Measured at 10kHz 60 dB
CMRR+ Common-mode Rejection Ratio Measured at 10MHz 50 dB
CMBW CM Amplifier Bandwidth 10K || 10pF load 50 MHz
CM
C

INDIFF

R

INDIFF

C

INCM

R

INCM

+I

IN

-I

IN

V

INDIFF

SLEW

CM Slew Rate Measured @ +1V to -1V 100 V/µs
Differential Input Capacitance Capacitance V
Differential Input Resistance Resistance V
CM Input Capacitance Capacitance V
CM Input Resistance Resistance V
Positive Input Current DC bias @ V
Negative Input Current DC bias @ V
Differential Input Range V

INP

- V

INM

INP

INP
INP
INP

INP

INP

to V

INM

to V

INM

= V

to ground 1.2 pF

INM

= V

to ground 1 2.8 MΩ

INM

= V

= 0V 1 µA

INM

= V

= 0V 1 µA

INM

12.4 MΩ

600 fF

when slope gain falls to 0.9 2.5 3.2 V

OUTPUT CHARACTERISTICS

V

O

I

OUT

R

OUTCM

DiffGain Differential Gain V

Output Voltage Swing RL = 150Ω ±3.5 V
Output Drive Current RL = 10Ω, V

V

= 0.35

G

INP

= 1V, V

= 0V, X2 = gain,

INM

50 60 mA

CM Output Resistance at 100kHz 30 Ω

= 0, VG = 0.35, X2 = 5, RL = 75 + 75Ω 0.85 1.0 1.1

C

SUPPLY

I

SON

I

SOFF

Supply Current V
Supply Current V

ENBL
ENBL

= 5, V
= 0, V

= 0 27 38 mA

INM

= 0 0.4 0.8 mA

INM

2

FN7305.5

November 30, 2007

EL9110

Electrical Specifications V

PARAMETER DESCRIPTION CONDITIONS

= VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, Unless Otherwise Specified (Continued)

SA+

MIN

(Note 1) TYP

MAX

(Note 1) UNIT

PSRR Power Supply Rejection Ratio DC to 100kHz, ±5V supply 60 dB

LOGIC CONTROL PINS

V

HI

V

LOW

I

LOGICH

I

LOGICL

Logic High Level VIN - V
Logic Low Level VIN - V

LOGIC
LOGIC

Logic High Input Current VIN = 5V, V
Logic Low Input Current VIN = 0V, V

ref for guaranteed high level 1.35 V
ref for guaranteed low level 0.8 V

= 0V 50 µA

LOGIC

= 0V 15 µA

LOGIC

NOTE:

1. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.

Pin Descriptions

PIN NUMBER PIN NAME PIN TYPE PIN FUNCTION

1 CTRL_REF Input Reference voltage for V
2 VCTRL Input Control voltage (0 to 1V) to set equalization
3 VINP Input Positive differential input
4 VINM Input Negative differential input
5 VS- Power -5V to core of chip
6 CMOUT Output Output of common mode voltage present at inputs
7 VGAIN Input Control voltage to set overall gain (0V to 1V)
8 LOGIC_REF Input Reference voltage for all logic signals

9 X2 Logic Input Logic signal; low - gain = 1, high - gain = 2
10 0V 0V reference for output voltage
11 VSA- Power -5V to output buffer
12 VOUT Output Single-ended output voltage reference to pin 10
13 VSA+ Power +5V to output buffer
14 ENBL Logic Input Logic signal to enable pin; low - disabled, high - enabled
15 VS+ Power +5V to core of chip
16 CMEXT Logic Input Logic signal to enable CM range extension; active high

GAIN

and V

CTRL

pins

3

FN7305.5

November 30, 2007

Typical Performance Curves

EL9110

5

V

= 0V

GAIN

= 0V

V

CTRL

R

LOAD

X2 = OFF

= 150Ω

FREQUENCY (Hz)

3

1

-1

GAIN (dB)

-3

-5
1M 10M 100M

-40
V

= 0V

GAIN

= 0V

V

CTRL

V

-45

-50

-55

THD (dBc)

-60

-65

= +5V

SS

V

= -5V

EE

= 150Ω

R

LOAD

X2 = OFF
INPUT = 0dBm

0.1M 1M 10M 100M
FREQUENCY (Hz)

FIGURE 1. FREQUENCY RESPONSE FIGURE 2. TOTAL HARMONIC DISTORTION

0

V

200mV/DIV

-20

-40

-60

CMRR (dBc)

CTR

V

GAIN

X2 = ON

= 0V

= 0.35V

-80

-100

2ns/DIV

100k 1M 10M 100M

FREQUENCY (Hz)

FIGURE 3. RISE TIME FIGURE 4. COMMON MODE REJECTION

4

V

= 0.35V

GAIN

= 0V

V

CTRL

R

LOAD

X2 = ON

= 150Ω

FREQUENCY (Hz)

2

0

-2

GAIN (dB)

-4

-6
100k 1M 10M 100M

-20
V

= -5V

EE

= 0V

V

CTRL

= 0V

V

GAIN

-40
INPUTS ON GND

-60

-80

-PSRR (dB)

-100

-120
100 100k1k 1M

10 10k 10M 100M

FREQUENCY (Hz)

FIGURE 5. CM AMPLIFIER BANDWIDTH FIGURE 6. PSRR vs FREQUENCY

4

FN7305.5

November 30, 2007

Typical Performance Curves (Continued)

EL9110

0

V

= 5V

CC

= 0V

V

CTRL

-20

-40

-60

+PSRR (dB)

-80

-100
10 10k 10M 100M

= 0V

V

GAIN

INPUTS ON GND

100 100k1k 1M

FREQUENCY (Hz)

FIGURE 7. PSRR vs FREQUENCY FIGURE 8. GAIN AS THE FUNCTION OF V

50

10ns/DIV

30

V

= 0mV

CTRL

10

-10

GROUP DELAY (ns)

-30

V

= 900mV

CTRL

-50
1M 100M

10M 200M

FREQUENCY (Hz)

100mV STEP

FIGURE 9. GROUP DELAY AS THE FUNCTION OF THE

FREQUENCY REPONSE CONTROL VOLTAGE
(V

)

CTRL

10dB/DIV

60

GAIN (dB)

50
40
30
20
10

0

-10

-20
100mV STEP

1M

10M 100M

FREQUENCY (Hz)

V

CTR

V

= 800mV

CTRL

= 0mV

CTRL

JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD

1.4

1.2

1

791mW

0.8

0.6

0.4

POWER DISSIPATION (W)

0.2

0

0 255075100 150

Q

S

O

P

θ

AMBIENT TEMPERATURE (°C)

1

J

6

A

=

1

5

8

°

C

/

W

12585

FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD

1.8

1.6

1.4

1.116W

1.2
1

0.8

0.6

0.4

POWER DISSIPATION (W)

0.2
0

0 255075100 150

Q

S

O

θ

P

1

J

AMBIENT TEMPERATURE (°C)

6

A

=

1

1

2

°

C

/

W

12585

FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE

5

FN7305.5

November 30, 2007

EL9110

Applications Information

Logic Control

The EL9110 has three logical input pins, Chip Enable
(ENBL), Common Mode Extend (CMEXT), and Switch Gain
(X2). The logic circuits all have a nominal threshold of 1.1V
above the potential of the logic reference pin. In most
applications it is expected that this chip will run from a +5V,
0V, -5V supply system with logic being run between 0V and
+5V . In this case the logic reference voltage should be tied to
the 0V supply. If the logic is referenced to the -5V rail, then
the logic reference should be connected to -5V. The logic
reference pin sources about 60µA and this will rise to about
200µA if all inputs are true (positive).

The logic inputs all source up to 10µA when they are held at
the logic reference level. When taken positive, the inputs
sink a current dependent on the high level, up to 50µA for a
high level 5V above the reference level.

The logic inputs, if not used, should be tied to the
appropriate voltage in order to define their state.

Control Reference and Signal Reference

Analog control voltages are required to set the equalizer and
contrast levels. These signals are voltages in the range 0V
to 1V, which are referenced to the control reference pin. It is
expected that the control reference pin will be tied to 0V and
the control voltage will vary from 0V to 1V. It is; however,
acceptable to connect the control reference to any potential
between -5V and 0V to which the control voltages are
referenced.

The control voltage pins themselves are high impedance.
The control reference pin will source between 0µA and
200µA depending on the control voltages being applied.

The control reference and logic reference effectively remove
the necessity for the 0V rail and operation from ±5V (or 0V
and 10V) only is possible. However we still need a further
reference to define the 0V level of the single ended output
signal. The reference for the output signal is provided by the
0V pin. The output stage cannot pull fully up or down to
either supply so it is important that the reference is
positioned to allow full output swing. The 0V reference
should be tied to a 'quiet ground' as any noise on this pin is
transferred directly to the output. The 0V pin is a high
impedance pin and draws dc bias currents of a few µA and
similar levels of AC current.

Common Mode Extension

The common mode extension circuitry extends the range of
input common mode voltage before the input differential
amplifier is overloaded. It does this by reducing the voltage
equally at both inputs of the first differential amplifier as the
common mode signal rises towards the supply. Similarly,
when the common mode input signal goes low, the inputs to
the first differential amplifier are raised whilst preserving the

differential signal and maintain the amplifier within its
common mode operating range.

This operation may not always be desirable. A problem
occurs because the EL9110 sinks or sources a common
mode current though its input pins to create the common
mode offset voltage. Assuming the system has been set up
so that the differential line has a well-balanced impedance,
then a problem will only occur when the common mode
impedance to ground is not low. This will occur in systems
where the inputs to the EL9110 are AC coupled. In such
systems it is recommended that the common mode
extension be disabled. In systems where the differential
input signal is directly coupled and has its common mode
level defined by a low impedance line driver, the common
mode extension circuitry can extend the total common mode
range by 2V to 3V.

Equalizing

When transmitting a signal across a twisted pair cable, it is
found that the high frequency (above 1MHz) information is
attenuated more significantly than the information at low
frequencies. The attenuation is predominantly due to
resistive skin effect losses and has a loss curve which
depends on the resistivity of the conductor, surface condition
of the wire and the wire diameter. For the range of high
performance twisted pair cables based on 24awg copper
wire (Cat 5 etc.) these parameters vary only a little between
cable types, and in general cables exhibit the same
frequency dependence of loss. (The lower loss cables can
be compared with somewhat longer lengths of their more
lossy brothers.) This enables a single equalizing law
equation to be built into the EL9110.

With a control voltage applied between pins 2 and 1, the
frequency dependence of the equalization is shown in
Figure 8. The equalization matches the cable loss up to
about 100MHz. Above this, system gain is rolled off rapidly
to reduce noise bandwidth. The roll-off occurs more rapidly
for higher control voltages, thus the system (cable +
equalizer) bandwidth reduces as the cable length increases.
This is desirable, as noise becomes an increasing issue as
the equalization increases.

The cable loss for 100m, 200m, and 300m of CAT 5 cable,
based on manufacturer's loss curves is shown in Figure 14.

Thus:

• 100m requires V

• 200m requires V
and:

• 300m requires V

= 0.2V

C

= 0.6V

C

= 1.0V approximately

C

Contrast

By varying the voltage between pins 7 and 1, the gain of the
signal path can be changed in the ratio 4:1. The gain change
varies almost linearly with control voltage. For normal

6

FN7305.5

November 30, 2007

operation it is anticipated the X2 mode will be selected and
the output load will be back matched. A unity gain to the
output load will then be achieved with a gain control voltage
of about 0.35V. This allows the gain to be trimmed up or
down by 6dB to compensate for any gain/loss errors that
affect the contrast of the video signal. Figure 12 shows an
example plot of the gain to the load with gain control voltage.

2.0

1.8

1.6

1.4

1.2

GAIN (V)

1.0

0.8

0.6

0.4

00.8

FIGURE 12. VARIATION OF GAIN WITH GAIN CONTROL

VOLTAGE

0.4 1.0
V

0.60.2

GAIN

Circuit and Layout Recommendation

The interconnection cable is a transmission line therefore for
proper function it should be treated like transmission line, a
refection-free termination is necessary.

A reflection-free termination is a real "ohmic" resistor with as
less as possible reactive parasitic.

The traces of the layout, up to the point where of the
termination resistor placed, are part of the transmission line
which also includes the cable's connector. A connector with
a better controlled impedance is an obligation for good
picture quality. The termination resistor should be placed
close to the inputs of the device's pins (pin 3 and pin 4.) The
small capacitance differential and common mode
capacitance of the input pins of the device makes it possible
to connect parallel to the termination resistor.

The cable will work as an antenna for all the RF spectrum
which is "in the air" where the cable is used. The spectrum,
particularly its common mode components, could and will
contain high energy level of transients which are above the
built-in protection level of the device and easily could
damage its inputs. Using a transient protection circuit
according to the given application is recommended.

70

60

50

40

30

20

ATTENUATION (dB)

10

0

0.01M 0.10M 1M 10M 100M

FIGURE 13. CAT-5 CABLE ATTENUATION CHARACTERISTICS

300M

200M

100M

50M

FREQUENCY (Hz)

Since the used signal's bandwidth is in the range of 100MHz,
for layout and power supply bypassing the roles of RF
design should be applied.

The following picture is taken from the DB9110 demo­board's layout. For better visibility the ground plain is
removed.

The ground plane is shown in Figure 14.

7

FN7305.5

November 30, 2007

The accompanying circuit diagram is shown in Figure 15.

R

330Ω

1µF

R

6

R

5

R

9

R

7

11

C

5

CTRL

1

_REF
VCTRL

2

VINP

3

VINM

4

CMEXT

VS+

ENBL

VSA+

16

15

C
1µF

C

7

6

1nF

14

13

Block Diagram

C

1nF

VS-

5

VOUT

12

TP7

CMOUT

6

VGAIN

C

R

10

12

330Ω

C

9

8

1µF

1µF

7

LOGIC

8 9

_REF

VSA-

0V

X2

11

10

C
1nF

11

FIGURE 15. CIRCUIT DIAGRAM

BIAS

CIRCUITRY

+

CONTROL

ASP

8

GAIN

ASP

VS- & VSA- connected to -5V

+ & VSA+ connected to +5V

V

S

FN7305.5

November 30, 2007

Typical Application

V

CTRL

0.1µF

EL9110

CTRL

1

_REF

2

VCTRL

CMEXT

VS+

16

15

+5V

CM

OUT

100

-5V

0.1µF

0.1µF

3

VINP

4

VINM

5

VS-

6

CMOUT

7

VGAIN
LOGIC

8 9

_REF

ENBL

VSA+

VOUT

VSA-

0V

X2

14

13

12

11

10

+5V

0.1µF

75

-5V

+5V

9

FN7305.5

November 30, 2007

EL9110

Quarter Size Outline Plastic Packages Family (QSOP)

E E1

0.010 C A B

C

SEATING
PLANE

0.004 C

A

N

1

B

L1

c

SEE DETAI L "X"

D

PIN #1
I.D. MARK

e

0.007 C A B

(N/2)+1

A

(N/2)

MDP0040

QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY

INCHES

SYMBOL

A 0.068 0.068 0.068 Max. ­A1 0.006 0.006 0.006 ±0.002 ­A2 0.056 0.056 0.056 ±0.004 -

b 0.010 0.010 0.010 ±0.002 -

c 0.008 0.008 0.008 ±0.001 -

D 0.193 0.341 0.390 ±0.004 1, 3

E 0.236 0.236 0.236 ±0.008 -

H

E1 0.154 0.154 0.154 ±0.004 2, 3

e 0.025 0.025 0.025 Basic -

L 0.025 0.025 0.025 ±0.009 -

b

L1 0.041 0.041 0.041 Basic -

N 16 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not
included.

2. Plastic interlead protrusions of 0.010” maximum per side are not
included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

TOLERANCE NOTESQSOP16 QSOP24 QSOP28

Rev. F 2/07

GAUGE
PLANE

L

0.010

4°±4°

A2

A1

DETAIL X

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

10

FN7305.5

November 30, 2007