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EL8302
Data Sheet May 6, 2005
500MHz Rail-to-Rail Amplifier
The EL8302 represents a triple rail-to-rail amplifier with a 3dB bandwidth of 500MHz and slew rate of 600V/µs.
Running off a very low supply current of 5.6mA per channel,
the EL8302 also features inputs that go to 0.15V below the
V
- rail.
S
The EL8302 includes a fast-acting disable/power-down
circuit. With a 25ns disable and a 200ns enable, the EL8302
is ideal for multiplexing applications.
The EL8302 is designed for a number of general purpose
video, communication, instrumentation, and industrial
applications. The EL8302 is available in an 16-pin SO and
16-pin QSOP packages and is specified for operation over
the -40°C to +85°C temperature range.
Pinout
EL8302
(16-PIN SO, QSOP)
TOP VIEW
Features
• 500MHz -3dB bandwidth
• 600V/µs slew rate
• Low supply current = 5.6mA per amplifier
• Supplies from 3V to 5.5V
• Rail-to-rail output
• Input to 0.15V below V
-
S
• Fast 25ns disable
•Low cost
• Pb-Free available (RoHS compliant)
Applications
• Video amplifiers
• Portable/hand-held products
• Communications devices
FN7348.2
INA+
1
CEA
2
VS-
3
CEB
4
INB+
5
NC
6
CEC
7
INC+
8 9
16
INA-
-
15
14
13
12
11
10
OUTA
VS+
OUTB
INB-
NC
OUTC
INC-
+
+
-
+
-
Ordering Information
PAR T
NUMBER PACKAGE TAPE & REEL PKG. DWG. #
EL8302IS 16-Pin SO - MDP0027
EL8302IS-T7 16-Pin SO 7” MDP0027
EL8302IS-T13 16-Pin SO 13” MDP0027
EL8302ISZ
(See Note)
EL8302ISZ-T7
(See Note)
EL8302ISZ-T13
(See Note)
EL8302IU 16-Pin QSOP - MDP0040
EL8302IU-T7 16-Pin QSOP 7” MDP0040
EL8302IU-T13 16-Pin QSOP 13” MDP0040
EL8302IUZ
(See Note)
EL8302IUZ-T7
(See Note)
EL8302IUZ-T13
(See Note)
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
16-Pin SO
(Pb-free)
16-Pin SO
(Pb-free)
16-Pin SO
(Pb-free)
16-Pin QSOP
(Pb-free)
16-Pin QSOP
(Pb-free)
16-Pin QSOP
(Pb-free)
- MDP0027
7” MDP0027
13” MDP0027
- MDP0040
7” MDP0040
13” MDP0040
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL8302
Absolute Maximum Ratings (T
Supply Voltage from V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
+ to VS-. . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
S
Electrical Specifications V
= 25°C)
A
+ + 0.3V to VS- -0.3V
S
= TC = T
J
= 5V, VS- = GND, TA = 25°C, V
S+
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
A
= 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified
CM
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
V
OS
TCV
OS
IB Input Bias Current V
I
OS
TCI
OS
CMRR Common Mode Rejection Ratio V
CMIR Common Mode Input Range V
R
IN
C
IN
AVOL Open Loop Gain V
Offset Voltage -7 -0.8 +7 mV
Offset Voltage Temperature Coefficient Measured from T
= 0V -10 -6 µA
IN
Input Offset Current V
Input Bias Current Temperature
= 0V 0.1 0.6 µA
IN
Measured from T
Coefficient
= -0.15V to +3.5V 70 95 dB
CM
MIN
MIN
to T
to T
MAX
MAX
3µV/°C
2nA/°C
- -0.15 VS+ - 1.5 V
S
Input Resistance Common Mode 7 MΩ
Input Capacitance 0.5 pF
= +1.5V to +3.5V, RL = 1kΩ to GND 75 100 dB
OUT
V
= +1.5V to +3.5V, RL = 150Ω to
OUT
GND
80 dB
OUTPUT CHARACTERISTICS
R
OUT
V
OP
V
ON
I
OUT
Output Resistance AV = +1 30 mΩ
Positive Output Voltage Swing RL = 1kΩ 4.85 4.9 V
R
= 150Ω 4.65 4.7 V
L
Negative Output Voltage Swing RL = 150Ω 150 200 mV
R
= 1kΩ 50 70 mV
L
Linear Output Current 65 mA
ISC (source) Short Circuit Current RL = 10Ω 50 80 mA
I
(sink) Short Circuit Current RL = 10Ω 90 150 mA
SC
POWER SUPPLY
PSRR Power Supply Rejection Ratio V
I
S-ON
I
S-OFF
Supply Current - Enabled per Amplifier 5.6 6.2 mA
Supply Current - Disabled per Amplifier 40 90 µA
+ = 4.5V to 5.5V 70 95 dB
S
ENABLE
t
EN
t
DS
V
IH-ENB
V
IL-ENB
Enable Time 200 ns
Disable Time 25 ns
ENABLE Pin Voltage for Power-up 0.8 V
ENABLE Pin Voltage for Shut-down 2 V
2
EL8302
Electrical Specifications V
= 5V, VS- = GND, TA = 25°C, V
S+
= 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified
CM
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
I
IH-ENB
I
IL-ENB
ENABLE Pin Input Current High 8.6 µA
ENABLE Pin Input for Current Low 0.01 µA
AC PERFORMANCE
BW -3dB Bandwidth A
= +1, RF = 0Ω, CL = 1.5pF 500 MHz
V
A
= -1, RF = 1kΩ, CL = 1.5pF 140 MHz
V
A
= +2, RF = 1kΩ, CL = 1.5pF 165 MHz
V
AV = +10, RF = 1kΩ, CL = 1.5pF 18 MHz
BW ±0.1dB Bandwidth A
Peak Peaking A
= +1, RF = 0Ω, CL = 1.5pF 36 MHz
V
= +1, RL = 1kΩ, CL = 1.5pF 1 dB
V
GBWP Gain Bandwidth Product 200 MHz
PM Phase Margin R
SR Slew Rate A
t
R
t
F
Rise Time 2.5V
Fall Time 2.5V
= 1kΩ, CL = 1.5pF 55 °
L
= 2, RL = 100Ω, V
V
, 20% - 80% 4 ns
STEP
, 20% - 80% 2 ns
STEP
= 0.5V to 4.5V 500 600 V/µs
OUT
OS Overshoot 200mV step 10 %
t
PD
t
S
dG Differential Gain A
dP Differential Phase A
e
N
i
+ Positive Input Noise Current f = 10kHz 1.7 pA/√Hz
N
i
- Negative Input Noise Current f = 10kHz 1.3 pA/√Hz
N
e
S
Propagation Delay 200mV step 1 ns
0.1% Settling Time 200mV step 15 ns
= +2, RF = 1kΩ, RL = 150Ω 0.01 %
V
= +2, RF = 1kΩ, RL = 150Ω 0.01 °
V
Input Noise Voltage f = 10kHz 12 nV/√Hz
Channel Separation f = 100kHz 95 dB
Pin Descriptions
PIN NAME FUNCTION
1, 5, 8 INA+, INB+, INC+ Non-inverting input for each channel
2, 4, 7 CEA
3 VS- Negative power supply
6, 11 NC Not connected
9, 12, 16 INC-, INB-, INA- Inverting input for each channel
10, 13, 15 OUTC, OUTB, OUTA Amplifier output for each channel
14 VS+ Positive power supply
, CEB, CEC Enable and disable input for each channel
3
Typical Performance Curves
EL8302
5
VS=5V
4
=1
A
V
=1kΩ
R
3
L
C
=1.5pF
L
2
1
0
-1
GAIN (dB)
-2
-3
-4
-5
1M 10M 100M
V
V
FREQUENCY (Hz)
OP-P
OP-P
=1V
=2V
V
OP-P
=200mV
1G
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGE LEVELS
5
VS=5V
4
C
=1.5pF
L
=1kΩ
R
3
L
NORMALIZED GAIN (dB)
2
1
0
-1
-2
-3
-4
-5
1M
AV=5
AV=10
10M 100M
AV=2
FREQUENCY (Hz)
AV=1
1G
5
3
1
-1
VS=5V
-3
A
=2
NORMALIZED GAIN (dB)
V
=1kΩ
R
L
=1.5pF
C
L
-5
100K 1M 10M 100M 1G
RF=RG=1kΩ
RF=RG=500Ω
FREQUENCY (Hz)
RF=RG=2kΩ
FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE
vs R
AND R
F
4
VS=5V
C
=1.5pF
L
=1kΩ
R
2
L
=1kΩ
R
F
0
-2
-4
NORMALIZED GAIN (dB)
-6
100K 1M 10M 100M 1G
G
AV=-1
AV=-5
AV=-10
FREQUENCY (Hz)
FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS NON-INVERTING GAINS
5
VS=5V
4
=1
A
V
C
=1.5pF
3
L
=200mV
V
OP-P
2
1
0
-1
GAIN (dB)
-2
-3
-4
-5
1M
RL=100Ω
R
=500Ω
L
10M 100M
FREQUENCY (Hz)
RL=1kΩ
1G
FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR
VAR IOU S R
LOAD
4
FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS INVERTING GAINS
11
VS=5V
A
=2
V
=1.5pF
C
9
L
=1kΩ
R
F=RG
7
5
GAIN (dB)
3
1
100K 1M 10M 100M 1G
RL=500Ω
RL=1kΩ,
150Ω
FREQUENCY (Hz)
FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE vs
VARIOUS R
LOAD
Typical Performance Curves (Continued)
EL8302
5
VS=5V
4
=1
A
V
R
=1kΩ
3
L
=200mV
V
OP-P
2
1
0
-1
GAIN (dB)
-2
-3
-4
-5
1M
10M 100M 1G
FREQUENCY (Hz)
CL=4.8pF
CL=3.7pF
CL=1.5pF
FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE vs C
110
70
30
-10
GAIN (dB)
-50
RL=1kΩ
RL=150Ω
RL=150Ω
RL=1kΩ
405
315
225
135
45
PHASE (°)
16
VS=5V
14
=2
A
V
=1kΩ
R
12
L
=1kΩ
R
F=RG
10
8
6
4
GAIN (dB)
2
0
-2
-4
1M 10M
FREQUENCY (Hz)
L
FIGURE 8. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS C
-10
VS=5V
=1
A
V
=1kΩ
R
-30
L
-50
-70
GAIN (dB)
-90
CL=20pF
CL=13.5pF
CL=10pF
CL=1.5pF
L
100M
CL=28.5pF
1G
-90
1K 10K 1M 100M 1G
100K 10M
FREQUENCY (Hz)
-45
FIGURE 9. OPEN LOOP GAIN AND PHASE vs FREQUENCY
-10
-30
-50
-70
PSRR (dB)
-90
-110
1K 10K 10M 100M
PSRR-
PSRR+
100K 1M
FREQUENCY (Hz)
FIGURE 11. POWER SUPPLY REJECTION
RATIO vs FREQUENCY
-110
1K 10K 100K 100M 1G
1M 10M
FREQUENCY (Hz)
FIGURE 10. DISABLED OUTPUT ISOLATION FREQUENCY
RESPONSE
550
500
RL=1kΩ
450
400
350
300
250
BANDWIDTH (MHz)
200
150
100
=1.5pF
C
L
3 3.5 4.5 5 5.5
AV=1
AV=2
4
V
(V)
S
FIGURE 12. SMALL SIGNAL BANDWIDTH vs
SUPPLY VOLTAGE
5
Typical Performance Curves (Continued)
EL8302
100
10
1
IMPEDANCE (Ω)
0.1
0.01
10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 13. OUPUT IMPEDANCE vs FREQUENCY
-15
-35
-55
-75
CMRR (dB)
100M
2.5
RL=1kΩ
=1.5pF
C
L
2
1.5
1
PEAKING (dB)
0.5
0
3 3.5 4.5 5 5.5
4
AV=1
AV=2
V
(V)
S
FIGURE 14. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE
10
8
6
(mA)
S
I
4
-95
-115
100K 1M 10M 100M
FREQUENCY (Hz)
FIGURE 15. COMMON-MODE REJECTION RATIO vs
FREQUENCY
-60
VS=5V
VS=5V
=1kΩ
R
=1kΩ
R
L
L
C
=1.5p
=1.5pF
C
L
L
-70
F
A
=2
V
-80
H
DISTORTION (dBc)
-90
H
-100
15
z
H
M
1
@
2
D
5
@
3
D
3
D
H
z
H
M
V
H
M
0
1
@
HD3@1MHz
342
(V)
OP-P
D
H
D
H
z
z
H
M
0
1
@
2
z
H
M
5
@
2
FIGURE 17. HARMONIC DISTORTION vs OUTPUT VOLTAGE
2
0
01 34 5.5
20.5 1.5 3.5 4.5 52.5
V
(V)
S
FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE (PER
AMPLIFIER)
-70
-75
-80
-85
VS=5V
f=5MHz
-90
DISTORTION (dBc)
-95
VO=1V
V
-100
100 2K
for AV=1
P-P
=2V
for AV=2
O
P-P
(Ω)
R
LOAD
H
D
2
@
A
=
V
2
H
D
2
@
A
=
V
1
H
D
3
@
A
=
2
V
H
D
3
@
A
=
1
V
1K
FIGURE 18. HARMONIC DISTORTION vs LOAD RESISTANCE
6
Typical Performance Curves (Continued)
EL8302
-50
VS=5V
=1kΩ
R
L
-60
=1.5pF
C
L
V
=1V
for AV=1
O
P-P
=2V
O
P-P
3
D
H
for AV=2
2
=
V
@A
2
D
H
A
@
CH2-->CH3
H
2
=
V
D
H
FREQUENCY (MHz)
CH2-->CH1
CH2-->CH1
FREQUENCY (Hz)
1
=
A
@
2
V
D
1
=
A
V
@
3
10
VOLTAGE NOISE (nV/√Hz)
FIGURE 20. VOLTAGE AND CURRENT NOISE vs FREQUENCY
CH3-->CH2
CH1-->CH2
CH1<=>CH3
FIGURE 22. LARGE SIGNAL TRANSIENT
V
-70
-80
DISTORTION (dBc)
-90
-100
140
FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
CHANNEL SEPARATION (dB)
-90
-100
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09
FIGURE 21. CHANNEL SEPARATION vs FREQUENCY
1K
100
e
N
10
IN+ IN-
CURRENT NOISE (pA/√Hz),
1
10 100 10K 100K 10M
V
=5V, AV=1, RL=1kΩ TO 2.5V, CL=1.5pF
S
3.5
2.5
1.5
1K 1M
FREQUENCY (Hz)
2ns/DIV
RESPONSE - RISING
V
=5V, AV=1, RL=1kΩ to 2.5V, CL=1.5pF
S
3.5
2.5
1.5
2ns/DIV
FIGURE 23. LARGE SIGNAL TRANSIENT
RESPONSE - FALLING
7
VS=5V, AV=1, RL=1kΩ TO 2.5V, CL= 1.5pF
V
V
IN
OUT
10ns/DIV
2.6
2.5
2.4
2.6
2.5
2.4
FIGURE 24. SMALL SIGNAL TRANSIENT REPONSE
Typical Performance Curves (Continued)
EL8302
VS=5V, AV=5, RL=1kΩ TO 2.5V
5
2.5
0
FIGURE 25. OUTPUT SWING
CH1
ENABLE
INPUT
2µs/DIV
VS=5V, AV=5, RL=1kΩ TO 2.5V
5
2.5
0
FIGURE 26. OUTPUT SWING
ENABLE
INPUT
CH1
2µs/DIV
CH2
V
OUT
CH1, CH2, 1V/DIV, M=100ns
FIGURE 27. ENABLED RESPONSES
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1
909mW
0.8
0.6
633mW
0.4
0.2
POWER DISSIPATION (W)
0
0 255075100 150
S
O
1
θ
6
J
(
0
A
=
.
1
1
5
1
0
0
”
°
)
C
/
W
Q
S
O
θ
P
J
1
A
=
6
1
5
8
°
C
/
W
AMBIENT TEMPERATURE (°C)
12585
FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
CH2
V
OUT
CH1, CH2, 0.5V/DIV, M=20ns
FIGURE 28. DISABLED RESPONSE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2
1.250W
1
0.8
893mW
0.6
0.4
POWER DISSIPATION (W)
0.2
0
0 255075100 150
S
O
1
6
θ
(
0
J
.
A
1
=
5
8
0
0
”
°
)
C
/
W
Q
S
θ
O
P
J
A
1
=
6
1
1
2
°
C
/
W
AMBIENT TEMPERATURE (°C)
12585
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
8
Simplified Schematic Diagram
EL8302
V
S+
IN+
I
1
R
R
1
Q
1
I
2
3
R
2
Q
IN-
2
V
BIAS2
R
6
Q
5
Q
3
R
4
Description of Operation and Application
Information
Product Description
The EL8302 is wide bandwidth, single supply, low power and
rail-to-rail output voltage feedback operational amplifiers.
The amplifiers are internally compensated for closed loop
gain of +1 of greater. Connected in voltage follower mode
and driving a 1kΩ load, the EL8302 has a -3dB bandwidth of
500MHz. Driving a 150Ω load, the bandwidth is about
350MHz while maintaining a 600V/us slew rate. The EL8302
is available with a power down pin for each channel to
reduce power to 30µA typically while the amplifier is
disabled.
Input, Output and Supply Voltage Range
The EL8302 has been designed to operate with a single
supply voltage from 3V to 5.0V. Split supplies can also be
used as long as their total voltage is within 3V to 5.0V. The
amplifiers have an input common mode voltage range from
0.15V below the negative supply (V
the positive supply (V
+ pin). If the input signal is outside the
S
above specified range, it will cause the output signal to be
distorted.
The output of the EL8302 can swing rail to rail. As the load
resistance becomes lower, the ability to drive close to each
rail is reduced. For the load resistor 1kΩ, the output swing is
about 4.9V at a 5V supply. For the load resistor 150Ω, the
output swing is about 4.6V.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the output pin to the inverting
input pin. For gains greater than +1, the feedback resistor
forms a pole with the parasitic capacitance at the inverting
- pin) to within 1.5V of
S
R
7
V
Q
6
BIAS1
DIFFERENTIAL TO
SINGLE ENDED
DRIVE
GENERATOR
Q
4
R
5
V
S-
R
8
Q
7
OUT
Q
8
R
9
input. As this pole becomes smaller, the amplifier’s phase
margin is reduced. This causes ringing in the time domain
and peaking in the frequency domain. Therefore, R
some maximum value that should not be exceeded for
optimum performance. If a large value of R
must be used, a
F
small capacitor in the few pF range in parallel with R
help to reduce the ringing and peaking at the expense of
reducing the bandwidth.
As far as the output stage of the amplifier is concerned, the
output stage is also a gain stage with the load. R
appear in parallel with R
for gains other than +1. As this
L
F
combination gets smaller, the bandwidth falls off.
Consequently, R
also has a minimum value that should not
F
be exceeded for optimum performance. For gain of +1, R
is optimum. For the gains other than +1, optimum response
is obtained with R
between 300Ω to 1kΩ.
F
The EL8302 has a gain bandwidth product of 200MHz. For
gains ≥5, its bandwidth can be predicted by the following
equation:
Gain BW× 200MHz=
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency response as DC levels are changed at the output.
This is especially difficult when driving a standard video load
of 150Ω, because the change in output current with DC level.
Special circuitry has been incorporated in the EL8302 to
reduce the variation of the output impedance with the current
output. This results in dG and dP specifications of 0.01%
and 0.01°, while driving 150Ω at a gain of 2. Driving high
impedance loads would give a similar or better dG and dP
performance.
has
F
can
F
and RG
F
=0
9
EL8302
Driving Capacitive Loads and Cables
The EL8302 can drive 5pF loads in parallel with 1kΩ with
less than 5dB of peaking at gain of +1. If less peaking is
desired in applications, a small series resistor (usually
between 5Ω to 50Ω) can be placed in series with the output
to eliminate most peaking. However, this will reduce the gain
slightly. If the gain setting is greater than 1, the gain resistor
R
can then be chosen to make up for any gain loss which
G
may be created by the additional series resistor at the
output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier’s output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL8302 can be disabled and placed its output in a high
impedance state. The turn off time is about 25ns and the turn
on time is about 200ns. When disabled, the amplifier’s
supply current is reduced to 30µA typically, thereby
effectively eliminating the power consumption. The
amplifier’s power down can be controlled by standard TTL or
CMOS signal levels at the ENABLE
signal is relative to V
- pin. Letting the ENABLE pin float or
S
applying a signal that is less than 0.8V above V
pin. The applied logic
- will enable
S
the amplifier. The amplifier will be disabled when the signal
at ENABLE
pin is 2V above VS-.
Output Drive Capability
The EL8302 does not have internal short circuit protection
circuitry. They have a typical short circuit current of 80mA
sourcing and 150mA sinking for the output is connected to
half way between the rails with a 10Ω resistor. If the output is
shorted indefinitely, the power dissipation could easily
increase such that the part will be destroyed. Maximum
reliability is maintained if the output current never exceeds
±40mA. This limit is set by the design of the internal metal
interconnections.
Power Dissipation
With the high output drive capability of the EL8302, It is
possible to exceed the 125°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T
–
PD
MAX
JMAXTAMAX
=
-------------------------------------------- -
θ
JA
Where:
T
= Maximum junction temperature
JMAX
T
= Maximum ambient temperature
AMAX
θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
For sourcing:
PD
MAXVSISMAX
3
VSV
+×=
–()
∑
i1=
OUTi
V
-----------------
×
OUTi
R
Li
For sinking:
3
PD
MAXVSISMAX
V
+×=
∑
i1=
OUTiVS
-–()I
×
LOADi
Where:
V
= Total supply voltage
S
I
= Maximum quiescent supply current
SMAX
V
= Maximum output voltage of the application for
OUTi
each channel
R
= Load resistance tied to ground for each
LOADi
channel
I
= Load current for eachh channel
LOADi
By setting the two PD
can solve the output current and R
equations equal to each other, we
MAX
to avoid the device
LOAD
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the V
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V
- pin becomes the negative
S
supply rail.
- pin is
S
S
+
10
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
EL8302
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier’s inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
Typical Applications
VIDEO SYNC PULSE REMOVER
Many CMOS analog to digital converters have a parasitic
latch up problem when subjected to negative input voltage
levels. Since the sync tip contains no useful video
information and it is a negative going pulse, we can chop it
off. Figure 31 shows a gain of 2 connections for EL8302.
Figure 32 shows the complete input video signal applied at
the input, as well as the output signal with the negative going
sync pulse removed.
5V
V
IN
75Ω
V
+
-
V
75Ω
S+
S-
75Ω
V
OUT
V
is passed through to the output when the ENABLE
IN1
signal is low and turns off in about 25ns when the ENABLE
signal is high. About 200ns later, Amp B turns on and V
IN2
is
passed through to the output. The break-before-make
operation ensures that more than one amplifier isn’t trying to
drive the bus at the same time.
+2.5V
B
A
2MHz
1V
2MHz
2V
P-P
75Ω
1K
P-P
75Ω
1K
ENABLE
FIGURE 33. TWO TO ONE MULTIPLEXER
+
-
+
-
-2.5V
1K
+2.5V
-2.5V
1K
75Ω
V
OUT
75Ω
1K
1K
FIGURE 31. SYNC PULSE REMOVER
1V
V
IN
V
OUT
M = 10µs/DIV
0.5V
0V
1V
0.5V
0V
FIGURE 32. VIDEO SIGNAL
MULTIPLEXER
Besides the normal power down usage, the ENABLE
pin of
the EL8302 can be used for multiplexing applications. Figure
33 shows two channels with the outputs tied together, driving
a back terminated 75Ω video load. A 2V
is applied to Amp A and a 1V
2MHz sine wave is applied
P-P
to Amp B. Figure 34 shows the ENABLE
resulting output waveform at V
. Observe the break-
OUT
2MHz sine wave
P-P
signal and the
before-make operation of the multiplexing. Amp A is on and
0V
-0.5V
ENABLE
A
M = 50ns/DIV
-1.5V
-2.5V
1V
0V
B
-1V
FIGURE 34.
SINGLE SUPPLY VIDEO LINE DRIVER
The EL8302 is wideband rail-to-rail output op amplifiers with
large output current, excellent dG, dP, and low distortion that
allow them to drive video signals in low supply applications.
Figure 35 is the single supply non-inverting video line driver
configuration and Figure 36 is the inverting video ling driver
configuration. The signal is AC coupled by C
. R1 and R2
1
are used to level shift the input and output to provide the
largest output swing. R
the virtual ground potential. R
resistors for the line. C
and RG set the AC gain. C2 isolates
F
1
and R3 are the termination
T
, C2 and C3 are selected big enough
to minimize the droop of the luminance signal.
11
EL8302
5V
C
R
1
V
R
75Ω
R
10K
2
R
1kΩ
G
10K
1
+
-
R
1kΩ
C
2
220µF
F
47µF
IN
T
C
3
470µF
R
75Ω
3
FIGURE 35. 5V SINGLE SUPPLY NON INVERTING
VIDEO LINE DRIVER
4
3
2
1
0
-1
-2
-3
-4
NORMALIZED GAIN (dB)
-5
-6
100K 1M 10M 100M 500M
FIGURE 37. VIDEO LINE DRIVER FREQUENCY RESPONSE
V
OUT
75Ω
FREQUENCY (Hz)
R
F
1kΩ
C
R
1
V
R
75Ω
R
10K
R
10K
500Ω
1
2
G
5V
47µF
IN
T
5V
-
+
C
2
220µF
C
3
470µF
R
75Ω
3
V
OUT
75Ω
FIGURE 36. SINGLE SUPPLY INVERTING VIDEO LINE DRIVER
AV = 2
AV = -2
12
SO Package Outline Drawing
EL8302
13
QSOP Package Outline Drawing
EL8302
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
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