intersil EL7585 DATA SHEET

®

EL7585

Data Sheet March 9, 2006

TFT-LCD Power Supply

The EL7585 represents a multiple output regulators for use in all large panel, TFT-LCD applications. It features a single boost converter with integrated 3.5A FET, two positive LDOs for V for V

and V

ON

generation. The boost converter can be

OFF

generation, and a single negative LDO

LOGIC

programmed to operate in either P-mode or PI-mode for improved load regulation.

The EL7585 also integrates fault protection for all four channels. Once a fault is detected, the device is latched off until the input supply or EN is cycled. This device also features an integrated start-up sequence for V then V

ON

or for V

OFF

, V

, and VON sequencing. The

BOOST

BOOST, VOFF

latter requires a single external transistor. The timing of the start-up sequence is set using an external capacitor.

The EL7585 is specified for operation over the -40°C to +85°C temperature range.

Ordering Information

PAR T

NUMBER

EL7585ILZ (Note)

EL7585ILZ-T7 (Note)

EL7585ILZ-T13 (Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING PACKAGE

7585ILZ 20 Ld 4x4 QFN

(Pb-free)

7585ILZ 20 Ld 4x4 QFN

(Pb-free)

7585ILZ 20 Ld 4x4 QFN

(Pb-free)

TA PE &

REEL

7” MDP0046

13” MDP0046

PKG.

DWG. #

- MDP0046

FN7345.2

Features

• 3.5A current limit FET options

• 3V to 5V input

• Up to 20V boost out

• 1% regulation on all outputs

•V

BOOST/VLOGIC-VOFF-VON

or V

LOGIC-VOFF-VBOOST

-

VON sequence control

• Programmable sequence delay

• Fully fault protected

,

• Thermal shutdown

• Internal soft-start

• 20 Ld QFN packages

• Pb-Free plus anneal available (RoHS Compliant)

Applications

• LCD monitors (15”+)

• LCD-TV (up to 40”+)

• Notebook displays (up to 16”)

• Industrial/medical LCD displays

Pinout

EL7585

(20 LD QFN)

TOP VIEW

PG

VDD

EN

SGND

20

19

18

17

16 FBB

CDLY

DELB

LX1

LX2

1

2

3

4

THERMAL

PAD

15

14

13

12

CINT

VREF

PGND

5

DRVP

6

7

8

DRVL

FBL

FBP

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

11 FBN

9

10DRVN

SGND

EL7585

Absolute Maximum Ratings (T

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V

DELB

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V

DRVP

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V

DRVN

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V

DD

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V

LX

= 25°C) Thermal Information

A

Thermal Resistance (Typical, Notes 1, 2) θ

QFN Package. . . . . . . . . . . . . . . . . . . . 39 2.5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V

V

DRVL

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C

(°C/W) θJC (°C/W)

JA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Maximum continuous junction temperature . . . . . . . . . . . . . . 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

JA

Tech Brief TB379.

2. For θ

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

= TC = T

J

= 5V, V

DD

-40°C to 85°C, unless otherwise specified.

BOOST

= 11V, I

A

LOAD

= 200mA, V

ON

= 15V, V

OFF

= -5V, V

= 2.5V, over temperature from

LOGIC

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

SUPPLY

V

S

Quiescent Current Enabled, LX not switching 1.7 2.5 mA

I

S

Supply Voltage 35.5V

Disabled 5 20 µA

CLOCK

F

OSC

Oscillator Frequency 900 1000 1100 kHz

BOOST

V

Boost Output Range 5.5 20 V

BOOST

FBB

Boost Feedback Voltage TA= 25°C 1.192 1.205 1.218 V

1.188 1.205 1.222 V

V

F_FBB

V

REF

FBB Fault Trip Point 0.9 V

Reference Voltage TA= 25°C 1.19 1.215 1.235 V

1.187 1.215 1.238 V

V

C

REF

D

MAX

I

LXMAX

I

LEAK

r

DS(ON)

Capacitor 22 100 nF

REF

Maximum Duty Cycle 85 %

Switch Current Limit 3.5 A

Switch Leakage Current VLX = 16V 10 µA

Switch On-Resistance 160 mΩ

Eff Boost Efficiency See curves 92 %

) Feedback Input Bias Current Pl mode, V

I(V

FBB

/

∆V

BOOST

∆V

IN

∆V

BOOST

∆I

BOOST

∆V

BOOST

∆I

BOOST

V

CINT_T

Line Regulation C

/

Load Regulation - “P” mode C

/

Load Regulation - “PI” mode C

CINT Pl Mode Select Threshold 4.7 4.8 V

= 4.7nF, I

INT

pin strapped to VDD,

INT

50mA < I

= 4.7nF, 50mA < IO < 250mA 0.1 %

INT

= 1.35V 50 500 nA

FBB

= 100mA, VIN = 3V to 5.5V 0.05 %/V

OUT

3%

< 250mA

LOAD

2

FN7345.2

March 9, 2006

EL7585

Electrical Specifications V

DD

= 5V, V

BOOST

= 11V, I

LOAD

= 200mA, V

ON

= 15V, V

OFF

= -5V, V

= 2.5V, over temperature from

LOGIC

-40°C to 85°C, unless otherwise specified. (Continued)

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

VON LDO

V

FBP

V

F_FBP

I

FBP

FBP Regulation Voltage I

FBP Fault Trip Point V

FBP Input Bias Current V

GMP FBP Effective Transconductance V

/∆I(VON)VON Load Regulation I(VON) = 0mA to 20mA -0.5 %

∆V

ON

I

DRVP

I

L_DRVP

V

OFF

V

FBN

V

F_FBN

I

FBN

LDO

DRVP Sink Current Max V

DRVP Leakage Current V

FBN Regulation Voltage I

FNN Fault Trip Point V

FBN Input Bias Current V

GMN FBN Effective Transconductance V

∆V

OFF

∆I(V

OFF

I

DRVN

I

L_DRVN

V

LOGIC

V

FBL

V

F_FBL

I

FBL

G

ML

∆V

LOGIC

∆I(V

LOGIC

I

DRVL

I

L_DRL

/

)

LDO

/

)

Load Regulation I(V

V

OFF

DRVN Source Current Max V

DRVN Leakage Current V

FBL Regulation Voltage I

FBL Fault Trip Point V

FBL Input Bias Current V

FBL Effective Transconductance V

Load Regulation I(V

V

LOGIC

DRVL Sink Current Max V

I

L_DRVL

= 0.2mA, TA = 25°C 1.176 1.2 1.224 V

DRVP

= 0.2mA 1.172 1.2 1.228 V

I

DRVP

falling 0.82 0.87 0.92 V

FBP

= 1.35V -250 250 nA

FBP

= 25V, I

DRVP

= 1.1V, V

FBP

= 1.5V, V

FBP

= 0.2mA, TA = 25°C 0.173 0.203 0.233 V

DRVN

= 0.2mA 0.171 0.203 0.235 V

I

DRVN

rising 0.38 0.43 0.48 V

FBN

= 0.2V -250 250 nA

FBN

= -6V, I

DRVN

) = 0mA to 20mA -0.5 %

OFF

= 0.3V, V

FBN

= 0V, V

FBN

= 1mA, TA = 25°C 1.176 1.2 1.224 V

DRVL

= 1mA 1.174 1.2 1.226 V

I

DRVL

falling 0.82 0.87 0.92 V

FBL

= 1.35V -500 500 nA

FBL

= 2.5V, I

DRVL

) = 100mA to 500mA 0.5 %

LOGIC

= 1.1V, V

FBL

V

= 1.5V, V

FBL

= 0.2 to 2mA 50 ms

DRVP

= 25V 2 4 mA

DRVP

= 35V 0.1 5 µA

DRVP

= 0.2mA to 2mA 50 ms

DRVN

= -6V 2 4 mA

DRVN

= -20V 0.1 5 µA

DRVN

= 1mA to 8mA 200 ms

DRVL

= 2.5V 8 16 mA

DRVL

= 5.5V 0.1 5 µA

DRVL

SEQUENCING

t

ON

t

SS

t

DEL1

t

DEL2

t

DEL3

I

DELB

C

DEL

Turn On D elay C

Soft-start Time C

Delay Between A

Delay Between VON and V

Delay Between V V

BOOST

and V

VDD

and Delayed

OFF

DELB Pull-down Current V

Delay Capacitor 10 220 nF

= 0.22µF 30 ms

DLY

= 0.22µF 2 ms

DLY

C

= 0.22µF 10 ms

DLY

C

= 0.22µF 17 ms

DLY

C

= 0.22µF 10 ms

DLY

> 0.6V 50 µA

DELB

V

< 0.6V 1.4 mA

DELB

FAULT DETECTION

t

FAULT

Fault Time Out C

= 0.22µF 50 ms

DLY

3

FN7345.2

March 9, 2006

EL7585

Electrical Specifications V

DD

= 5V, V

BOOST

= 11V, I

LOAD

= 200mA, V

ON

= 15V, V

OFF

= -5V, V

= 2.5V, over temperature from

LOGIC

-40°C to 85°C, unless otherwise specified. (Continued)

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

OT Over-temperature Threshold 140 °C

I

PG

PG Pull-down Current VPG > 0.6V 15 µA

VPG < 0.6V 1.7 mA

LOGIC ENABLE

V

HI

V

LO

I

LOW

I

HIGH

Logic High Threshold 2.2 V

Logic Low Threshold 0.8 V

Logic Low bias Current 0.2 1 µA

Logic High bias Current at VEN = 5V 12 18 24 µA

Pin Descriptions

PIN NAME PIN NUMBER DESCRIPTION

1 CDLY A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault

2 DELB Open drain output for gate drive of optional V

3, 4 LX1, LX2 Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected

5 DRVP Positive LDO base drive; open drain of an internal N channel FET

6 FBP Positive LDO voltage feedback input pin; regulates to 1.2V nominal

7 DRVL Logic LDO base drive; open drain of an internal N channel FET

8 FBL Logic LDO voltage feedback input pin; regulates to 1.2V nominal

9, 17 SGND Low noise signal ground

10 DRVN Negative LDO base drive; open drain of an internal P channel FET

11 FBN Negative LDO voltage feedback input pin; regulates to 0.2V nominal

12, 13 PGND Power ground, connected to source of internal N channel boost FET

14 VREF Bandgap voltage bypass, connect a 0.1µF to SGND

15 CINT V

16 FBB Boost regulator voltage feedback input pin; regulates to 1.2V nominal

18 EN Enable pin, High=Enable; Low or floating=Disable

19 VDD Positive supply

20 PG Push-pull gate drive of optional fault protection FET, when chip is disabled or when a fault has been

timeout time

integrator output, connect capacitor to SGND for PI mode or connect to VDD for P mode

BOOST

operation

detected, this is high

BOOST

delay FET

4

FN7345.2

March 9, 2006

Typical Performance Curves

EL7585

100

90

80

70

60

50

40

30

EFFICIENCY (%)

20

10

0

0 0.1 0.2 0.3 0.4 0.5 0.6

FIGURE 1. V

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0 0.2 0.4 0.6 0.7

FIGURE 3. V

VO=9V

VO=12V

VO=15V

(A)

I

OUT

EFFICIENCY AT VIN=3V (PI MODE) FIGURE 2. V

BOOST

VO=9V

VO=15V

0.1 0.3 0.5

(A)

I

OUT

EFFICIENCY AT VIN=3V (P MODE) FIGURE 4. V

BOOST

VO=12V

100

90

80

70

60

50

40

30

EFFICIENCY (%)

20

10

0

00.511.5

BOOST

100

90

80

70

60

50

40

30

EFFICIENCY (%)

20

10

0

0 0.5 1 1.5

BOOST

VO=15V

(A)

I

OUT

EFFICIENCY AT VIN=5V (PI MODE)

VO=15V

I

(A)

OUT

EFFICIENCY AT VIN=5V (P MODE)

VO=9V

VO=12V

VO=9V

VO=12V

-0.1

-0.2

-0.3

-0.4

LOAD REGULATION (%)

-0.5

FIGURE 5. V

0

VO=9V

VO=15V

VO=12V

0 0.1 0.2 0.3 0.4 0.5 0.6

LOAD REGULATION AT VIN=3V (PI MODE) FIGURE 6. V

BOOST

I

OUT

(A)

5

0

-0.1

-0.2

-0.3

-0.4

-0.5

LOAD REGULATION (%)

VO=15V

-0.6 0 0.2 0.4 0.6 0.8 1 1.2 1.4

LOAD REGULATION AT VIN=5V (PI MODE)

BOOST

I

OUT

VO=12V

(A)

VO=9V

FN7345.2

March 9, 2006

Typical Performance Curves (Continued)

EL7585

0

-1

-2

-3

-4

-5

-6

LOAD REGULATION (%)

-7

-8

FIGURE 7. V

-0.1

-0.2

-0.3

-0.4

LOAD REGULATION (%)

-0.5

-0.6

VO=9V

VO=15V

VO=12V

0 0.2 0.4 0.6 0.8

(A)

I

OUT

LOAD REGULATION AT VIN=3V (P MODE) FIGURE 8. V

BOOST

0

0 20406080

I

(mA)

OUT

FIGURE 9. V

LOAD REGULATION FIGURE 10. V

ON

0

-2

-4

-6

-8

LOAD REGULATION (%)

-10

00.511.5

BOOST

0

-0.2

-0.4

-0.6

-0.8

-1

LOAD REGULATION (%)

-1.2

-1.4 020 6080100

VO=15V

I

(A)

OUT

LOAD REGULATION AT VIN=5V (P MODE)

40

I

(mA)

OUT

LOAD REGULATION

OFF

VO=9V

VO=12V

0

-0.2

-0.4

-0.6

-0.8

LOAD REGULATION (%)

-1

-1.2 0 100 200 500 700

FIGURE 11. V

LOGIC

400

300

I

(mA)

OUT

LOAD REGULATION

6

600

V

CDLY

EN

V

BOOST

V

LOGIC

TIME (10ms/DIV)

FIGURE 12. START-UP SEQUENCE

=220nF

C

DLY

FN7345.2

March 9, 2006