intersil EL7585 DATA SHEET

®

EL7585

Data Sheet March 9, 2006

TFT-LCD Power Supply

The EL7585 represents a multiple output regulators for use
in all large panel, TFT-LCD applications. It features a single
boost converter with integrated 3.5A FET, two positive LDOs
for V
for V

and V

ON

generation. The boost converter can be

OFF

generation, and a single negative LDO

LOGIC

programmed to operate in either P-mode or PI-mode for
improved load regulation.

The EL7585 also integrates fault protection for all four
channels. Once a fault is detected, the device is latched off
until the input supply or EN is cycled. This device also
features an integrated start-up sequence for V
then V

ON

or for V

OFF

, V

, and VON sequencing. The

BOOST

BOOST, VOFF

latter requires a single external transistor. The timing of the
start-up sequence is set using an external capacitor.

The EL7585 is specified for operation over the -40°C to
+85°C temperature range.

Ordering Information

PAR T

NUMBER

EL7585ILZ
(Note)

EL7585ILZ-T7
(Note)

EL7585ILZ-T13
(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PART

MARKING PACKAGE

7585ILZ 20 Ld 4x4 QFN

(Pb-free)

7585ILZ 20 Ld 4x4 QFN

(Pb-free)

7585ILZ 20 Ld 4x4 QFN

(Pb-free)

TA PE &

REEL

7” MDP0046

13” MDP0046

PKG.

DWG. #

- MDP0046

FN7345.2

Features

• 3.5A current limit FET options

• 3V to 5V input

• Up to 20V boost out

• 1% regulation on all outputs

•V

BOOST/VLOGIC-VOFF-VON

or V

LOGIC-VOFF-VBOOST

-

VON sequence control

• Programmable sequence delay

• Fully fault protected

,

• Thermal shutdown

• Internal soft-start

• 20 Ld QFN packages

• Pb-Free plus anneal available (RoHS Compliant)

Applications

• LCD monitors (15”+)

• LCD-TV (up to 40”+)

• Notebook displays (up to 16”)

• Industrial/medical LCD displays

Pinout

EL7585

(20 LD QFN)

TOP VIEW

PG

VDD

EN

SGND

20

19

18

17

16 FBB

CDLY

DELB

LX1

LX2

1

2

3

4

THERMAL

PAD

15

14

13

12

CINT

VREF

PGND

PGND

5

DRVP

6

7

8

DRVL

FBL

FBP

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

11 FBN

9

10DRVN

SGND

EL7585

Absolute Maximum Ratings (T

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V

DELB

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V

DRVP

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V

DRVN

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V

DD

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V

LX

= 25°C) Thermal Information

A

Thermal Resistance (Typical, Notes 1, 2) θ

QFN Package. . . . . . . . . . . . . . . . . . . . 39 2.5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V

V

DRVL

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C

(°C/W) θJC (°C/W)

JA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Maximum continuous junction temperature . . . . . . . . . . . . . . 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

JA

Tech Brief TB379.

2. For θ

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

= TC = T

J

= 5V, V

DD

-40°C to 85°C, unless otherwise specified.

BOOST

= 11V, I

A

LOAD

= 200mA, V

ON

= 15V, V

OFF

= -5V, V

= 2.5V, over temperature from

LOGIC

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

SUPPLY

V

S

Quiescent Current Enabled, LX not switching 1.7 2.5 mA

I

S

Supply Voltage 35.5V

Disabled 5 20 µA

CLOCK

F

OSC

Oscillator Frequency 900 1000 1100 kHz

BOOST

V

V

Boost Output Range 5.5 20 V

BOOST

FBB

Boost Feedback Voltage TA= 25°C 1.192 1.205 1.218 V

1.188 1.205 1.222 V

V

F_FBB

V

REF

FBB Fault Trip Point 0.9 V

Reference Voltage TA= 25°C 1.19 1.215 1.235 V

1.187 1.215 1.238 V

V

C

REF

D

MAX

I

LXMAX

I

LEAK

r

DS(ON)

Capacitor 22 100 nF

REF

Maximum Duty Cycle 85 %

Switch Current Limit 3.5 A

Switch Leakage Current VLX = 16V 10 µA

Switch On-Resistance 160 mΩ

Eff Boost Efficiency See curves 92 %

) Feedback Input Bias Current Pl mode, V

I(V

FBB

/

∆V

BOOST

∆V

IN

∆V

BOOST

∆I

BOOST

∆V

BOOST

∆I

BOOST

V

CINT_T

Line Regulation C

/

Load Regulation - “P” mode C

/

Load Regulation - “PI” mode C

CINT Pl Mode Select Threshold 4.7 4.8 V

= 4.7nF, I

INT

pin strapped to VDD,

INT

50mA < I

= 4.7nF, 50mA < IO < 250mA 0.1 %

INT

= 1.35V 50 500 nA

FBB

= 100mA, VIN = 3V to 5.5V 0.05 %/V

OUT

3%

< 250mA

LOAD

2

FN7345.2

March 9, 2006

EL7585

Electrical Specifications V

DD

= 5V, V

BOOST

= 11V, I

LOAD

= 200mA, V

ON

= 15V, V

OFF

= -5V, V

= 2.5V, over temperature from

LOGIC

-40°C to 85°C, unless otherwise specified. (Continued)

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

VON LDO

V

FBP

V

F_FBP

I

FBP

FBP Regulation Voltage I

FBP Fault Trip Point V

FBP Input Bias Current V

GMP FBP Effective Transconductance V

/∆I(VON)VON Load Regulation I(VON) = 0mA to 20mA -0.5 %

∆V

ON

I

DRVP

I

L_DRVP

V

OFF

V

FBN

V

F_FBN

I

FBN

LDO

DRVP Sink Current Max V

DRVP Leakage Current V

FBN Regulation Voltage I

FNN Fault Trip Point V

FBN Input Bias Current V

GMN FBN Effective Transconductance V

∆V

OFF

∆I(V

OFF

I

DRVN

I

L_DRVN

V

LOGIC

V

FBL

V

F_FBL

I

FBL

G

ML

∆V

LOGIC

∆I(V

LOGIC

I

DRVL

I

L_DRL

/

)

LDO

/

)

Load Regulation I(V

V

OFF

DRVN Source Current Max V

DRVN Leakage Current V

FBL Regulation Voltage I

FBL Fault Trip Point V

FBL Input Bias Current V

FBL Effective Transconductance V

Load Regulation I(V

V

LOGIC

DRVL Sink Current Max V

I

L_DRVL

= 0.2mA, TA = 25°C 1.176 1.2 1.224 V

DRVP

= 0.2mA 1.172 1.2 1.228 V

I

DRVP

falling 0.82 0.87 0.92 V

FBP

= 1.35V -250 250 nA

FBP

= 25V, I

DRVP

= 1.1V, V

FBP

= 1.5V, V

FBP

= 0.2mA, TA = 25°C 0.173 0.203 0.233 V

DRVN

= 0.2mA 0.171 0.203 0.235 V

I

DRVN

rising 0.38 0.43 0.48 V

FBN

= 0.2V -250 250 nA

FBN

= -6V, I

DRVN

) = 0mA to 20mA -0.5 %

OFF

= 0.3V, V

FBN

= 0V, V

FBN

= 1mA, TA = 25°C 1.176 1.2 1.224 V

DRVL

= 1mA 1.174 1.2 1.226 V

I

DRVL

falling 0.82 0.87 0.92 V

FBL

= 1.35V -500 500 nA

FBL

= 2.5V, I

DRVL

) = 100mA to 500mA 0.5 %

LOGIC

= 1.1V, V

FBL

V

= 1.5V, V

FBL

= 0.2 to 2mA 50 ms

DRVP

= 25V 2 4 mA

DRVP

= 35V 0.1 5 µA

DRVP

= 0.2mA to 2mA 50 ms

DRVN

= -6V 2 4 mA

DRVN

= -20V 0.1 5 µA

DRVN

= 1mA to 8mA 200 ms

DRVL

= 2.5V 8 16 mA

DRVL

= 5.5V 0.1 5 µA

DRVL

SEQUENCING

t

ON

t

SS

t

DEL1

t

DEL2

t

DEL3

I

DELB

C

DEL

Turn On D elay C

Soft-start Time C

Delay Between A

Delay Between VON and V

Delay Between V
V

BOOST

and V

VDD

and Delayed

OFF

OFF

OFF

DELB Pull-down Current V

Delay Capacitor 10 220 nF

= 0.22µF 30 ms

DLY

= 0.22µF 2 ms

DLY

C

= 0.22µF 10 ms

DLY

C

= 0.22µF 17 ms

DLY

C

= 0.22µF 10 ms

DLY

> 0.6V 50 µA

DELB

V

< 0.6V 1.4 mA

DELB

FAULT DETECTION

t

FAULT

Fault Time Out C

= 0.22µF 50 ms

DLY

3

FN7345.2

March 9, 2006

EL7585

Electrical Specifications V

DD

= 5V, V

BOOST

= 11V, I

LOAD

= 200mA, V

ON

= 15V, V

OFF

= -5V, V

= 2.5V, over temperature from

LOGIC

-40°C to 85°C, unless otherwise specified. (Continued)

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

OT Over-temperature Threshold 140 °C

I

PG

PG Pull-down Current VPG > 0.6V 15 µA

VPG < 0.6V 1.7 mA

LOGIC ENABLE

V

HI

V

LO

I

LOW

I

HIGH

Logic High Threshold 2.2 V

Logic Low Threshold 0.8 V

Logic Low bias Current 0.2 1 µA

Logic High bias Current at VEN = 5V 12 18 24 µA

Pin Descriptions

PIN NAME PIN NUMBER DESCRIPTION

1 CDLY A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault

2 DELB Open drain output for gate drive of optional V

3, 4 LX1, LX2 Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected

5 DRVP Positive LDO base drive; open drain of an internal N channel FET

6 FBP Positive LDO voltage feedback input pin; regulates to 1.2V nominal

7 DRVL Logic LDO base drive; open drain of an internal N channel FET

8 FBL Logic LDO voltage feedback input pin; regulates to 1.2V nominal

9, 17 SGND Low noise signal ground

10 DRVN Negative LDO base drive; open drain of an internal P channel FET

11 FBN Negative LDO voltage feedback input pin; regulates to 0.2V nominal

12, 13 PGND Power ground, connected to source of internal N channel boost FET

14 VREF Bandgap voltage bypass, connect a 0.1µF to SGND

15 CINT V

16 FBB Boost regulator voltage feedback input pin; regulates to 1.2V nominal

18 EN Enable pin, High=Enable; Low or floating=Disable

19 VDD Positive supply

20 PG Push-pull gate drive of optional fault protection FET, when chip is disabled or when a fault has been

timeout time

integrator output, connect capacitor to SGND for PI mode or connect to VDD for P mode

BOOST

operation

detected, this is high

BOOST

delay FET

4

FN7345.2

March 9, 2006

Typical Performance Curves

EL7585

100

90

80

70

60

50

40

30

EFFICIENCY (%)

20

10

0

0 0.1 0.2 0.3 0.4 0.5 0.6

FIGURE 1. V

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0 0.2 0.4 0.6 0.7

FIGURE 3. V

VO=9V

VO=12V

VO=15V

(A)

I

OUT

EFFICIENCY AT VIN=3V (PI MODE) FIGURE 2. V

BOOST

VO=9V

VO=15V

0.1 0.3 0.5

(A)

I

OUT

EFFICIENCY AT VIN=3V (P MODE) FIGURE 4. V

BOOST

VO=12V

100

90

80

70

60

50

40

30

EFFICIENCY (%)

20

10

0

00.511.5

BOOST

100

90

80

70

60

50

40

30

EFFICIENCY (%)

20

10

0

0 0.5 1 1.5

BOOST

VO=15V

(A)

I

OUT

EFFICIENCY AT VIN=5V (PI MODE)

VO=15V

I

(A)

OUT

EFFICIENCY AT VIN=5V (P MODE)

VO=9V

VO=12V

VO=9V

VO=12V

-0.1

-0.2

-0.3

-0.4

LOAD REGULATION (%)

-0.5

FIGURE 5. V

0

VO=9V

VO=15V

VO=12V

0 0.1 0.2 0.3 0.4 0.5 0.6

LOAD REGULATION AT VIN=3V (PI MODE) FIGURE 6. V

BOOST

I

OUT

(A)

5

0

-0.1

-0.2

-0.3

-0.4

-0.5

LOAD REGULATION (%)

VO=15V

-0.6
0 0.2 0.4 0.6 0.8 1 1.2 1.4

LOAD REGULATION AT VIN=5V (PI MODE)

BOOST

I

OUT

VO=12V

(A)

VO=9V

FN7345.2

March 9, 2006

Typical Performance Curves (Continued)

EL7585

0

-1

-2

-3

-4

-5

-6

LOAD REGULATION (%)

-7

-8

FIGURE 7. V

-0.1

-0.2

-0.3

-0.4

LOAD REGULATION (%)

-0.5

-0.6

VO=9V

VO=15V

VO=12V

0 0.2 0.4 0.6 0.8

(A)

I

OUT

LOAD REGULATION AT VIN=3V (P MODE) FIGURE 8. V

BOOST

0

0 20406080

I

(mA)

OUT

FIGURE 9. V

LOAD REGULATION FIGURE 10. V

ON

0

-2

-4

-6

-8

LOAD REGULATION (%)

-10

00.511.5

BOOST

0

-0.2

-0.4

-0.6

-0.8

-1

LOAD REGULATION (%)

-1.2

-1.4
020 6080100

VO=15V

I

(A)

OUT

LOAD REGULATION AT VIN=5V (P MODE)

40

I

(mA)

OUT

LOAD REGULATION

OFF

VO=9V

VO=12V

0

-0.2

-0.4

-0.6

-0.8

LOAD REGULATION (%)

-1

-1.2
0 100 200 500 700

FIGURE 11. V

LOGIC

400

300

I

(mA)

OUT

LOAD REGULATION

6

600

V

CDLY

EN

V

BOOST

V

LOGIC

TIME (10ms/DIV)

FIGURE 12. START-UP SEQUENCE

=220nF

C

DLY

FN7345.2

March 9, 2006

Typical Performance Curves (Continued)

V

CDLY

EL7585

V

BOOST

V

BOOST

V

LOGIC

V

BOOST-DELAY

V

LOGIC

V

V

REF

TIME (10ms/DIV)

C

=220nF

DLY

V

LOGIC

V

OFF

V

ON

TIME (10ms/DIV)

C

=220nF

DLY

FIGURE 13. START-UP SEQUENCE FIGURE 14. START-UP SEQUENCE

OFF

V

ON

TIME (10ms/DIV)

C

=220nF

DLY

VIN=5V
V

OUT

=30mA

I

OUT

=13V

TIME (400ns/DIV)

FIGURE 15. START-UP SEQUENCE FIGURE 16. LX WAVEFORM - DISCONTINUOUS MODE

VIN=5V

=13V

V

OUT

=200mA

I

OUT

TIME (400ns/DIV)

FIGURE 17. LX WAVEFORM - CONTINUOUS MODE

7

FN7345.2

March 9, 2006

EL7585

V

REF

SGND

FBB

C

INT

V

DD

PG

CDLY

DRVN

BUFFER

REFERENCE

GENERATOR

GM

AMPLIFIER

UVLO

COMPARATOR

THERMAL

SHUTDOWN

COMPENSATION

SS

+

-

SLOPE

VOLTAGE

AMPLIFIER

EN

SHUTDOWN

& START-UP

CONTROL

0.2V V

OSCILLATOR

OSC

COMP

Σ

COMPARATOR

REF

PWM

LOGIC

CONTROLLER

CURRENT

AMPLIFIER

CURRENT

LIMIT COMPARATOR

UVLO

SS

V

REF

+

-

BUFFER

CURRENT REF

+

-

EN

LX

PGND

DRVP

BUFFER

FBP

DELB

DRVL

BUFFER

FBN

0.4V

UVLO

COMPARATOR

UVLO

COMPARATOR

FIGURE 18. BLOCK DIAGRAM

Applications Information

The EL7585 is a highly integrated multiple output power
solution for TFT-LCD applications. The system consists of
one high efficiency boost converter and three linear­regulator controllers (V
protection functions. A block diagram is shown in Figure 18.
Table 1 lists the recommended components.

The EL7585 integrates an N-channel MOSFET boost
converter to minimize external component count and cost.
The A

VDD

, VON, V
independently set using external resistors. V
voltages require external charge pumps which are post
regulated using the integrated LDO controllers.

TABLE 1. RECOMMENDED COMPONENTS

DESIGNATION DESCRIPTION

C

, C2, C310µF, 16V X5R ceramic capacitor (1206)

1

C

, C

20

TDK C3216X5R0J106K

4.7µF, 25V X5R ceramic capacitor (1206)

31

TDK C3216X5R1A475K

OFF

, V

ON

, and V

OFF

LOGIC

, and V

) with multiple

LOGIC

output voltages are

ON

, V

OFF

FBL

TABLE 1. RECOMMENDED COMPONENTS (Continued)

DESIGNATION DESCRIPTION

D

1

D

, D12, D21200mA 30V Schottky barrier diode (SOT-23)

11

1A 20V low leakage Schottky rectifier (CASE 457-

04) ON SEMI MBRM120ET3

Fairchild BAT54S

L

1

Q

1

6.8µH 1.3A Inductor
TDK SLF6025T-6R8M1R3-PF

-2.4 -20V P-channel 1.8V specified PowerTrench
MOSFET (SuperSOT-3) Fairchild FDN304P

Q

4

Q

3

Q

2

-2A -30V single P-channel logic level PowerTrench
MOSFET (SuperSOT-3) Fairchild FDN360P

200mA 40V PNP amplifier (SOT-23)
Fairchild MMBT3906

200mA 40V NPN amplifier (SOT-23)
Fairchild MMBT3904

Q

5

1A 30V PNP low saturation amplifier (SOT-23)
Fairchild FMMT549

8

FN7345.2

March 9, 2006

EL7585

Boost Converter

The main boost converter is a current mode PWM converter at
a fixed frequency of 1MHz which enables the use of low profile
inductors and multilayer ceramic capacitors. This results in a
compact, low cost power system for LCD panel design.

The EL7585 is designed for continuous current mode, but
they can also operate in discontinuous current mode at light
load. In continuous current mode, current flows continuously
in the inductor during the entire switching cycle in steady
state operation. The voltage conversion ratio in continuous
current mode is given by:

A

VDD

--------------- -

V

IN

Where D is the duty cycle of the switching MOSFET.

Figure 19 shows the block diagram of the boost regulator. It
uses a summing amplifier architecture consisting of GM
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.

-------------=

1D–

1

An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by the
following equation:

A

VDD

---------------------

×=

V

R

REF

1

R1R2+

The current through the MOSFET is limited to 3.5A peak.
This restricts the maximum output current based on the
following equation:

I

OMAXILMT




∆I

--------–

IN

L

---------

×=

V

2

O

V

Where ∆IL is peak to peak inductor ripple current, and is set by:

V

D

IN

---- -

---------

∆I

L

where f

×=

L

f

S

is the switching frequency.

S

FBB

COMPENSATION

Ifb

Iref

SLOPE

CURRENT

AMPLIFIER

GM

AMPLIFIER

REFERENCE

GENERATOR

CLOCK

LOGIC

VOLTAGE

AMPLIFIER

PWM

SHUTDOWN
& START-UP

CONTROL

BUFFER

Ifb

Iref

LX

CINT

FIGURE 19. BLOCK DIAGRAM OF THE BOOST REGULATOR

9

PGND

FN7345.2

March 9, 2006

EL7585

The following table gives typical values (margins are
considered 10%, 3%, 20%, 10%, and 15% on V
and I

V

:

OMAX

TAB LE 2 .

f

(V) VO (V) L (µH)

IN

3.3 9 6.8 1 1.040686

3.3 12 6.8 1 0.719853

3.3 15 6.8 1 0.527353

5 9 6.8 1 1.576797

5 12 6.8 1 1.090686

5 15 6.8 1 0.79902

S

(MHz) I

, VO, L, fS,

IN

OMAX

Input Capacitor

An input capacitor is used to supply the peak charging
current to the converter. It is recommended that C

IN

be
larger than 10µF. The reflected ripple voltage will be smaller
with larger C

. The voltage rating of input capacitor should

IN

be larger than maximum input voltage.

Boost Inductor

The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH are to match the internal slope
compensation. The inductor must be able to handle the
following average and peak current:

I

I

LAVG

I

LPKILAVG

-------------=

1D–

O

∆I

L

--------+=

2

Rectifier Diode

A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The rectifier
diode must meet the output current and peak inductor
current requirements.

Output Capacitor

The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging and discharging of the output
capacitor.

V

–

OVIN

V

RIPPLEILPK

ESR

----------------------- -

V

O

For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output

I

O

----------------

C

OUT

1

---- -

××+×=

f

S

capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.

NOTE: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
C

in the equation above assumes the effective value of the

OUT

capacitor at a particular voltage and not the manufacturer’s stated
value, measured at zero volts.

Compensation

The EL7585 can operate in either P mode or PI mode.
Connecting the C

pin directly to VIN will enable P mode;

INT

For better load regulation, use PI mode with a 4.7nF
capacitor in series with a 10K resistor between C

INT

and
ground. This value may be reduced to improve transient
performance, however, very low values will reduce loop
stability.

Boost feedback resistors

As the boost output voltage, A
effective voltage feedback in the IC increases the ratio of
voltage to current feedback at the summing comparator
because R

decreases relative to R1. To maintain stable

2

operation over the complete current range of the IC, the
voltage feedback to the FBB pin should be reduced
proportionally, as A

is reduced, by means of a series

VDD

resistor-capacitor network (R
with a pole frequency (f

) set to approximately 10kHz for C2

p

effective = 10µF and 4kHz for C

R7 = ((1/0.1 x R2) - 1/R1)^-1

C7 = 1/(2 x 3.142 x fp x R7)

PI mode C

(C23) and R

INT

The IC is designed to operate with a minimum C23 capacitor
of 4.7nF and a minimum C

Note that, for high voltage A
ceramic capacitors (C

) reduces their effective capacitance

2

greatly; a 16V 10µF ceramic can drop to around 3µF at 15V.

To improve the transient load response of A
a resistor may be added in series with the C
larger the resistor the lower the overshoot but at the expense
of stability of the converter loop - especially at high currents.

With L = 10µH, A

= 15V, C23 = 4.7nF, C2 (effective)

VDD

should have a capacitance of greater than 10µF. R
can have values up to 5kΩ for C
up to 10K for C

Larger values of R
A

load currents less than the current limit are used. To

VDD

ensure A

VDD

(effective) up to 30µF.

2

(R7) may be possible if maximum

INT

stability, the IC should be operated at the
maximum desired current and then the transient load
response of A
maximum value of R

should be used to determine the

VDD

INT

.

, is reduced below 12V the

VDD

and C7) in parallel with R1,

7

(effective) = 30µF.

2

(R10)

INT

(effective) = 10µF.

2

, the voltage coefficient of

VDD

in PI mode,

VDD

capacitor. The

23

(effective) up to 20µF and

2

INT

(R7)

10

FN7345.2

March 9, 2006

EL7585

Operation of the DELB Output Function

An open drain DELB output is provided to allow the boost
output voltage, developed at C

(see application diagram),

2

to be delayed via an external switch (Q4) to a time after the
V

supply and negative V

BOOST

charge pump supply

OFF

have achieved regulation during the start-up sequence
shown in Figure 28. This then allows the A

VDD

and VON
supplies to start-up from 0V instead of the normal offset
voltage of V

IN-VDIODE (D1

) if Q4 were not present.

When DELB is activated by the start-up sequencer, it sinks
50µA allowing a controlled turn-on of Q4 and charge-up of
C

. C16 can be used to control the turn-on time of Q4 to

9

reduce inrush current into C
by R

and R8 can be used to limit the VGS voltage of Q4 if

9

. The potential divider formed

9

required by the voltage rating of this device. When the
voltage at DELB falls to less than 0.6V, the sink current is
increased to ~1.2mA to firmly pull DELB to 0V.

The voltage at DELB is monitored by the fault protection
circuit so that if the initial 50µA sink current fails to pull DELB
below ~0.6V after the start-up sequencing has completed,
then a fault condition will be detected and a fault time-out
ramp will be initiated on the C

capacitor (C7).

DEL

Operation of the PG Output Function

The PG output consists of an internal pull-up PMOS device
to V

, to turn-off the external Q1 protection switch and a

IN

current limited pull-down NMOS device which sinks ~15µA
allowing a controlled turn-on of Q1 gate capacitance. C

is

O

used to control how fast Q1 turns-on - limiting inrush current
into C

. When the voltage at the PG pin falls to less than

1

0.6V, the PG sink current is increased to ~1.2mA to firmly
pull the pin to 0V.

The voltage at PG is monitored by the fault protection circuit
so that if the initial 15µA sink current fails to pull PG below
~0.6V after the start-up sequencing has completed, then a
fault condition will be detected and a fault time-out ramp will
be initiated on the C

capacitor (C7).

DEL

Cascaded MOSFET Application

A 20V N-channel MOSFET is integrated in the boost
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed

as shown in Figure 20. The voltage rating of the external
MOSFET should be greater than V

V

IN

LX

EL7585

FIGURE 20. CASCADED MOSFET TOPOLOGY FOR HIGH

OUTPUT VOLTAGE APPLICATIONS

Linear-Regulator Controllers (VON, V
V

)

OFF

BOOST

FB

.

LOGIC

V

BOOST

, and

The EL7585 includes three independent linear-regulator
controllers, in which two are positive output voltage (V
and V
V

LOGIC

), and one is negative. The VON, V

LOGIC

OFF

linear-regulator controller functional diagrams,

ON

, and

applications circuits are shown in Figures 21, 22, and 23
respectively.

Calculation of the Linear Regulator Base-Emitter
Resistors (R

For the pass transistor of the linear regulator, low frequency
gain (Hfe) and unity gain freq. (f
datasheet. The pass transistor adds a pole to the loop
transfer function at f
phase margin at low frequency, the best choice for a pass
device is often a high frequency low gain switching
transistor. Further improvement can be obtained by adding a
base-emitter resistor R
Block Diagram), which increase the pole frequency to:
f

*(1+ Hfe *re/RBE)/Hfe, where re=KT/qIc. So choose the

p=fT

lowest value R
enough base current (I
current (I

We will take as an example the V
Fairchild FMMT549 PNP transistor is used as the external
pass transistor, Q5 in the application diagram, then for a
maximum V
sheet indicates Hfe_min = 100.

C

, RBP and RBN)

BL

) are usually specified in the

T

/Hfe. Therefore, in order to maintain

p=fT

(RBP, RBL, RBN in the Functional

BE

in the design as long as there is still

BE

) to support the maximum output

B

).

LOGIC

operating requirement of 500mA the data

LOGIC

linear regulator. If a

11

FN7345.2

March 9, 2006

EL7585

The base-emitter saturation voltage is: Vbe_max = 1.25V
(note this is normally a Vbe ~ 0.7V, however, for the Q5
transistor an internal Darlington arrangement is used to
increase it's current gain, giving a 'base-emitter' voltage of
2xV

BE

).

(Note that using a high current Darlington PNP transistor for
Q5 requires that V

IN

> V

+ 2V. Should a lower input

LOGIC

voltage be required, then an ordinary high gain PNP
transistor should be selected for Q5 so as to allow a lower
collector-emitter saturation voltage).

For the EL7585, the minimum drive current is:
I_DRVL_min = 8mA

The minimum base-emitter resistor, R

, can now be

BL

calculated as:

R

_min = VBE_max/(I_DRVL_min - Ic/Hfe_min) =

BL

1.25V/(8mA - 500mA/100) = 417Ω

This is the minimum value that can be used - so, we now
choose a convenient value greater than this minimum value;
say 500Ω. Larger values may be used to reduce quiescent
current, however, regulation may be adversely affected, by
supply noise if R

0.9V

PG_LDOP

+

-

GMP

FIGURE 21. VON FUNCTIONAL BLOCK DIAGRAM

is made too high in value.

BL

LDO_ON

1: Np

36V

ESD

CLAMP

DRVP

FBP

+

­R

BP

7kΩ

V

R

R

20kΩ

BOOST

Q3

P1

P2

LX

0.1µF

CP (TO 36V)

0.1µF

VON (TO 35V)

C

ON

LX

0.1µF

CP (TO -26V)

PG_LDON

0.4V

FIGURE 22. V

0.9V

PG_LDOL

FIGURE 23. V

-

+

GMN

-

+
GML

-

+

ESD

CLAMP

+

-

1: Nn

36V

LDO_OFF

FBN

DRVN

R

BN

3kΩ

FUNCTIONAL BLOCK DIAGRAM

OFF

LDO_LOG

DRVL

FBL

1: N1

FUNCTIONAL BLOCK DIAGRAM

LOGIC

R

BL

500Ω

R

N2

20kΩ

R

V

REF

N1

Q2

OR V

V

IN

(3V TO 6V)

R

L1

R

L2

20kΩ

V

(TO -20V)

OFF

PROT

Q5

V

LOGIC

(1.3V TO 3.6V)

0.1µF

C

OFF

C

LOG

10µF

The VON power supply is used to power the positive supply
of the row driver in the LCD panel. The DC/DC consists of an
external diode-capacitor charge pump powered from the
inductor (LX) of the boost converter, followed by a low
dropout linear regulator (LDO_ON). The LDO_ON regulator
uses an external PNP transistor as the pass element. The
onboard LDO controller is a wide band (>10MHz)
transconductance amplifier capable of 4mA drive current,
which is sufficient for up to 40mA or more output current
under the low dropout condition (forced beta of 10). Typical
V

voltage supported by EL7585 ranges from +15V to

ON

+36V. A fault comparator is also included for monitoring the
output voltage. The under-voltage threshold is set at 25%
below the 1.2V reference.

12

The V

power supply is used to power the negative

OFF

supply of the row driver in the LCD panel. The DC/DC

March 9, 2006

FN7345.2

EL7585

consists of an external diode-capacitor charge pump
powered from the inductor (LX) of the boost converter,
followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an external NPN transistor as the
pass element. The onboard LDO controller is a wide band
(>10MHz) transconductance amplifier capable of 4mA drive
current, which is sufficient for up to 40mA or more output
current under the low dropout condition (forced beta of 10).
Typical V

voltage supported by EL7585 ranges from -5V

OFF

to -20V. A fault comparator is also included for monitoring
the output voltage. The undervoltage threshold is set at
200mV above the 0.2V reference level.

The V

power supply is used to power the logic circuitry

LOGIC

within the LCD panel. The DC/DC may be powered directly
from the low voltage input, 3.3V or 5.0V, or it may be
powered through the fault protection switch. The
LDO_LOGIC regulator uses an external PNP transistor as
the pass element. The onboard LDO controller is a wide
band (>10MHz) transconductance amplifier capable of
16mA drive current, which is sufficient for up to 160mA or
more output current under the low dropout condition (forced
beta of 10). Typical V
ranges from +1.3V to V

voltage supported by EL7585

LOGIC

-0.2V. A fault comparator is also

DD

included for monitoring the output voltage. The undervoltage
threshold is set at 25% below the 1.2V reference.

Set-Up Output Voltage

Refer to the Typical Application Diagram, the output voltages
of V

, V

ON

equations:

OFF

, and V

are determined by the following

LOGIC

the transistor. VF is the forward-voltage of the charge pump
rectifier diode.

The number of negative charge pump stages is given by:

N

NEGATIVE

V

OUTPUTVCE

-------------------------------------------------

≥

V

INPUT

+

2VF×–

To achieve high efficiency and low material cost, the lowest
number of charge pump stages which can meet the above
requirements, is always preferred.

High Charge Pump Output Voltage (>36V)
Applications

In the applications where the charge pump output voltage is
over 36V, an external npn transistor need to be inserted into
between DRVP pin and base of pass transistor Q3 as shown
in Figure 24; or the linear regulator can control only one
stage charge pump and regulate the final charge pump
output as shown in Figure 25.

CHARGE PUMP

V

IN

VDD

NPN

OUTPUT

7kΩ

Q3

V

ON

EL7585

OR A

DRVP

CASCODE

TRANSISTOR

FBP

R



V

ONVREF

V

OFFVREFN

V

LOGICVREF

Where V

REF

×=

12

1

--------- -+



R



11

R

22

----------

V

R

×=

= 1.2V, V

REFNVREF

21

R



42

1

----------+



R



41

REFN

–()×+=

= 0.2V.

Resistor networks in the order of 250kΩ, 120kΩ and 10kΩ
are recommended for V

ON

, V

OFF

and V

LOGIC

, respectively.

Charge Pump

To generate an output voltage higher than V
multiple stages of charge pumps are needed. The number of
stage is determined by the input and output voltage. For
positive charge pump stages:

N

POSITIVE

where V

V

OUTVCEVINPUT

--------------------------------------------------------------

≥

V

INPUT

is the dropout voltage of the pass component of

CE

–+

2V

×–

F

the linear regulator. It ranges from 0.3V to 1V depending on

BOOST

, single or

FIGURE 24. CASCODE NPN TRANSISTOR CONFIGURATION

FOR HIGH CHARGE PUMP OUTPUT VOLTAGE
(>36V)

LX

0.1µF

A

0.1µF

7kΩ

DRVP

EL7585

FIGURE 25. THE LINEAR REGULATOR CONTROLS ONE

FBP

STAGE OF CHARGE PUMP

0.47µF

Q3

0.1µF 0.1µF

0.1µF

VDD

V

(>36V)

0.22µF

ON

13

FN7345.2

March 9, 2006

EL7585

Discontinuous/Continuous Boost Operation and
its Effect on the Charge Pumps

The EL7585 VON and V
edges to drive diode charge pumps from which LDO
regulators generate the V
appreciated that should a regular supply of LX switching
edges be interrupted, for example during discontinuous
operation at light A

VDD

affect the performance of V
depending on their exact loading conditions at the time.

To optimize V

ON/VOFF

discontinuous/continuous operation of the boost converter
can be adjusted, by suitable choice of inductor given V
V

, switching frequency and the A

OUT

be in continuous operation.

The following equation gives the boundary between
discontinuous and continuous boost operation. For
continuous operation (LX switching every clock cycle) we
require that:

I(A

_load) > D*(1-D)*VIN/(2*L*F

VDD

where the duty cycle, D = (A

For example, with V

IN

12V we find continuous operation of the boost converter can
be guaranteed for:

L = 10µH and I(A

L = 6.8µH and I(A

L = 3.3µH and I(A

VDD

VDD

VDD

architecture uses LX switching

OFF

ON

and V

supplies. It can be

OFF

boost load currents, then this may

ON

and V

regulation -

OFF

regulation, the boundary of

current loading, to

VDD

)

OSC

- VIN)/A

= 5V, F

VDD

OSC

VDD

= 1.0MHz and A

VDD

) > 61mA

) > 89mA

) > 184mA

IN

,

=

Charge Pump Output Capacitors

Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:

I

OUT

C

where f

------------------------------------------------------

≥

OUT

2V

OSC

××

RIPPLEfOSC

is the switching frequency.

Start-Up Sequence

Figure 26 shows a detailed start-up sequence waveform. For
a successful power-up, there should be six peaks at V
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.

If EN is L, the device is powered down. If EN is H, and the
input voltage (V
starts to charge C

) exceeds 2.5V, an internal current source

DD

to an upper threshold using a fast

DLY

ramp followed by a slow ramp. If EN is low at this point, the
C

ramp will be delayed until EN goes high.

DLY

The first four ramps on C

(two up, two down) are used to

DLY

initialize the fault protection switch and to check whether
there is a fault condition on C

DLY

or V

. If a fault is

REF

CDLY

detected, the outputs and the input protection will turn off
and the chip will power down.

If no fault is found, C

continues ramping up and down

CDLY

until the sequence is completed.

During the second ramp, the device checks the status of
V

and over temperature. At the peak of the second ramp,

REF

PG output goes low and enables the input protection PMOS
Q1. Q1 is a controlled FET used to prevent in-rush current into
V
on is controlled by C
off and disconnect the inductor from V

BOOST

before V

is enabled internally. Its rate of turn

BOOST

. When a fault is detected, M1 will turn

o

.

IN

With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~V
enabled so V

BOOST

rises to VIN-V

diode. Hence, there is a step at V

. Initially the boost is not

IN

through the output

DIODE

during this part of the

BOOST

start-up sequence. If this step is not desirable, an external
PMOS FET can be used to delay the output until the boost is
enabled internally. The delayed output appears at A

For EL7585, V

BOOST

and V

soft-start at the beginning

LOGIC

VDD

.

of the third ramp. The soft-start ramp depends on the value
of the C

capacitor. For C

DLY

of 220nF, the soft-start time

DLY

is ~2ms.

V

turns on at the start of the fourth peak. At the fifth

OFF

peak, the open drain o/p DELB goes low to turn on the
external PMOS Q4 to generate a delayed V

VON is enabled at the beginning of the sixth ramp. A
PG, V

, DELB and VON are checked at end of this ramp.

OFF

BOOST

output.

VDD

,

Fault Protection

During the startup sequence, prior to BOOST soft-start,
V

is checked to be within ±20% of its final value and the

REF

device temperature is checked. If either of these are not
within the expected range, the part is disabled until the
power is recycled or EN is toggled.

If C
while if C
occur and the sequence will not complete.

Once the start-up sequence is completed, the chip
continuously monitors C
FBB and PG and checks for faults. During this time, the

.

voltage on the C
fault is detected, or the EN pin is pulled low.

A fault on C
chip immediately. If a fault on any other output is detected,
C

DELAY

the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the C

is shorted low, then the sequence will not start,

DELAY

is shorted H, the first down ramp will not

DELAY

, DELB, FBP, FBL, FBN, V

DLY

capacitor remains at 1.15V until either a

DLY

, V

DELAY

or temperature will shut down the

REF

will ramp up linearly with a 5µA (typical) current to

capacitor returns to 1.15V.

DLY

REF

,

14

FN7345.2

March 9, 2006

EL7585

Typical fault thresholds for FBP, FBL, FBN and FBB are
included in the tables. PG and DELB fault thresholds are
typically 0.6V.

C

has an internal current-limited clamp to keep the

INT

voltage within its normal range. If C
boost regulator will attempt to regulate to 0V. If C

is shorted low, the

INT

INT

is

shorted H, the regulator switches to P mode.

If any of the regulated outputs (V
V

) are driven above their target levels the drive

LOGIC

BOOST

, VON, V

OFF

or

circuitry will switch off until the output returns to its expected
value.

If V

is excessively loaded, the current limit will

BOOST

prevent damage to the chip. While in current limit, the part
acts like a current source and the regulated output will drop.
If the output drops below the fault threshold, a ramp will be
initiated on C

and, provided that the fault is sustained,

DELAY

the chip will be disabled on completion of the ramp.

In some circumstances, (depending on ambient temperature
and thermal design of the board), continuous operation at
current limit may result in the over-temperature threshold
being exceeded, which will cause the part to disable
immediately.

All I/O also have ESD protection, which in many cases will
also provide overvoltage protection, relative to either ground
or V

. However, these will not generally operate unless

DD

abs max ratings are exceeded.

Component Selection for Start-Up Sequencing and
Fault Protection

The C
to stabilize the V
22nF to 1µF and should not be more than five times the
capacitor on C

The C
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching µA levels.

C

DEL

above). Note with 220nF on C
typically 50ms and the use of a larger/smaller value will vary
this time proportionally (e.g. 1µF will give a fault time-out
period of typically 230ms).

capacitor is typically set at 220nF and is required

REF

capacitor is typically 220nF and has a usable

DEL

should be at least 1/5 of the value of C

output. The range of C

REF

to ensure correct start-up operation.

DEL

the fault time-out will be

DEL

REF

REF

is from

(See

Fault Sequencing

The EL7585 has an advanced fault detection system which
protects the IC from both adjacent pin shorts during
operation and shorts on the output supplies.

A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.

15

FN7345.2

March 9, 2006

V

V

BOOST

CDLY

EN

V

REF

EL7585

ON

REF

PG ON

V

LOGIC

, V

VDD

A

SOFT-START

ON

OFF

V

SOFT-START

ON

DELB ON

V

FAULT DETECTED

CHIP DISABLED

V

LOGIC

V

OFF

DELAYED

V

BOOST

V

ON

t

ON

t

OS

t

DEL1

START-UP SEQUENCE

TIMED BY C

DLY

t

DEL2

NORMAL

OPERATION

FAULT

PRESENT

16

FIGURE 26. START-UP SEQUENCE

FN7345.2

March 9, 2006

EL7585

Over-Temperature Protection

An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of 140°C, the device will shut
down.

Layout Recommendation

The device's performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.

There are some general guidelines for layout:

1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.

2. Place V

3. Minimize the length of traces carrying fast signals and
high current.

4. All feedback networks should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.

and VDD bypass capacitors close to the pins.

REF

5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point near the main
decoupling capacitors.

6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.

7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.

8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return

DELAY

, R11,

1

capacitor

connections for feedback resistor networks (R

) and the V

R

41

capacitor, C22, the C

REF

C7 and the integrator capacitor C23.

9. Minimize feedback input track lengths to avoid switching
noise pick-up.

A two-layer demo board is available to illustrate the proper
layout implementation. A four-layer demo board can be used
to further optimize the layout recommendations.

Demo Board Layout

FIGURE 27. TOP LAYER FIGURE 28. BOTTOM LAYER

17

FN7345.2

March 9, 2006

Typical Application Diagram

EL7585

V

C

10

4.7µF

NODE 1

V

LOGIC

(2.5V)

IN

4.7µF

LX

A

L

Q

1

1nF

NODE 1

C

C

0

1

10µF

x2

PG

C

7

CDELAY

1

6.8µH

LX

FBB

D

1

46.5kΩ

R

5kΩ

Q

4

C

R

C

2

9

R

2

10µF

1MΩ

X2

1

R7 OPEN

OPEN

C

7

16

22nF

R

8

10kΩ

C

9

0.1µF

VDD

(12V)

0.22µF

10Ω

R

6

VDD

C64.7µF

R

10kΩ

7

V

REF

0.1µF

C

41

C

R

43

500Ω

Q

5

C

31

5.4kΩ

22

0.1µF

R

42

R

41

5kΩ

EN

VREF

DRVL

FBL

SGND

DELB

CINT

DRVP

FBP

DRVN

FBN

PGND

R

10

10kΩ

V

R

REF

C

C

R

12

R
20kΩ

22

R

20K

23

P

R

7kΩ

11

R

3kΩ

21

4.7nF

1nF

13

230kΩ

23

104K

Q

Q

3

C

15

0.47µF

2

C

20

4.7µF

C

14

0.1µF

C

25

0.1µF D

12

21

C

13

0.1µF

C

12

0.1µFD

C

24

0.1µF

LX

D

LX

C

0.1µF

11

11

V

ON

(15V)

V

OFF

(-5V)

NOTE: The SGND should be connected to the exposed die plate and connected to the PGND at one point only.

18

FN7345.2

March 9, 2006

QFN Package Outline Drawing

EL7585

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

19

FN7345.2

March 9, 2006