intersil EL7554 DATA SHEET

EL7554

Data Sheet November 5, 2007

Monolithic 4A DC/DC Step-Down Regulator

The EL7554 is a full-feature synchronous 4A step-down regulator capable of up to 96% efficiency. This device operates from 3V to 6V V

input supply. With internal CMOS

power FETs, the device can operate at up to 100% duty ratio, allowing for output voltage range from 0.8V up to nearly V

.The adjustable high switching frequency of up to 1MHz

enables the use of small components, making the whole converter occupy less than 0.58 square inch with components on one side of the PCB. The EL7554 operates at constant frequency PWM mode, making external synchronization possible. The EL7554 features soft-start and full start-up control, which eliminates the in-rush current and enables users to control the start-up of multiple converters to any configuration with ease. The EL7554 also offers a ±5% voltage margining capability that allows ra ising and lowering of the supplies derived from the EL7554 to validate the performance and reliability of system cards quickly and easily during manufacturing testing. A junction temperature indicator conveniently monitors the silicon die temperature, saving designers time in the tedious thermal characterization.

An easy-to-use simulation tool is available for download and can be used to modify design parameters such as switching frequency, voltage ripple, ambient temperature, as well as view schematics waveforms, efficiency graphs, and complete BOM with Gerber layout.

The EL7554 is available in a 28 Ld HTSSOP package and is specified for operation over the -40°C to +85°C temperature range.

Ordering Information

TEMP.

PART

NUMBER

EL7554IRE* 7554IRE -40 to +85 28 Ld HTSSOP MDP0048 EL7554IREZ*

(See Note) *Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347 for

details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ

special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

7554IREZ -40 to +85 28 Ld HTSSOP

RANGE

(°C) PACKAGE

(Pb-free)

PKG.

DWG. #

MDP0048

FN7360.5

Features

• Integrated MOSFETs

• 4A continuous output current

• Up to 96% efficiency

• All ceramic capacitors

• Multiple supply start-up tracking

• Built-in ±5% voltage margining

• 3V to 6V input voltage

• 0.58 in

footprint with components on one side of PCB

• Adjustable switching frequency to 1MHz

• Oscillator synchronization possible

• 100% duty ratio

• Junction temperature indicator

• Over-temperature protection

• Internal soft-start

• Variable output voltage down to 0.8V

• Power-good indicator

• 28 Ld HTSSOP package

• Pb-free available (RoHS compliant)

Applications

• Point-of-regulation power sup pli es

• FPGA Core and I/O supplies

• DSP, CPU Core, and IO supplies

• Logic/Bus supplies

• Portable equipment

Related Documentation

• Technical Brief 418 - Using the EL7554 Demo Board

• Easy to use applications software simulation tool available at www.intersil.com/dc-dc

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Typical Application Diagram

10.2K

12.7K

0.018µF

2.32K

EL7554

COMP

VREF

VTJ

SGND

COSC

STN

STP

220pF

OSC

0.22µF

OUT

(1.8V, 4A)

47µF

2.2µH

OUT

SEL

8 21

14 15

VDD

VIN

PGND

(3V TO

6V)

2x10µF

FN7360.5

November 5, 2007

EL7554

Absolute Maximum Ratings (T

, VDD to SGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

VX to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

SGND to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

COMP, V SEL, PG, EN, STP, STN, C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. T yp values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T

, FB, VO, VTJ, TM,

REF

to SGND . . . . . -0.3V to VDD +0.3V

OSC

DC Electrical Specifications V

= +25°C)

= V

+0.3V

= TC = T

= 3.3V, TA = TJ = +25°C, C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

= 390pF, Unless Otherwise Specified

OSC

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

REF

REFTC

REFLOAD

RAMP

OSC_CHG

OSC_DIS

VDD

VDD_OFF

DD_OFF

DD_ON

HYS

LEAK

LMAX

DSON1

DSONTC2

DSONTC

STP

STN

PGP

PGN

PG_HI

PG_LO

OVP

FB_LINE

FB_TC

Input Voltage Range 3 6 V Reference Accuracy 1.24 1.26 1.28 V Reference Temperature Coefficient 50 ppm/°C Reference Load Regulation 0 < I

< 50µA -1 %

REF

Oscillator Ramp Amplitude 1.15 V Oscillator Charge Current 0.1V < V Oscillator Discharge Current 0.1V < V

< 1.25V 200 µA

OSC

< 1.25V 8 mA

OSC

VDD Supply Current VEN = 1 (L disconnected) 2 2.7 5 mA V

Standby Current EN = 0 1 1.5 mA

VDD for Shutdown 2.4 2.65 V VDD for Startup 2.6 2.95 V Over-temperature Threshold 135 °C Over-temperature Hysteresis 20 °C Internal FET Leakage Current EN = 0, LX = 6V (low FET), LX = 0V (high FET) 10 µA Peak Current Limit 6A PFET On Resistance 35 70 mΩ NFET On Resistance 30 60 mΩ R

Tempco 0.2 mΩ/°C

DSON

STP Pin Input Pull-down Current V STN Pin Input Pull-up Current V

= VIN/2 -4 2.5 µA

STP

= VIN/2 2.5 4 µA

STN

Positive Power Good Threshold With respect to target output voltage 6 14 % Negative Power Good Threshold With respect to target output voltage -14 -6 % Power Good Drive High I

= 1mA 2.6 V

Power Good Drive Low IPG = -1mA 0.5 V Output Over-voltage Protection 10 % Output Initial Accuracy I Output Line Regulation V

= 0A 0.79 0.8 0.81 V

LOAD

= 3.3V, ΔVIN = 10%, I

= 0A 0.2 0.5 %

LOAD

Error Amplifier Transconductance VCC = 0.65V 85 125 165 µs Output Temperature Stability 0°C < TA < +85°C, I

= 3A ±1 %

LOAD

Switching Frequency 300 370 440 kHz Feedback Input Pull-up Current V

= 0V 100 200 nA

FN7360.5

November 5, 2007

EL7554

DC Electrical Specifications V

= V

= 3.3V, TA = TJ = +25°C, C

= 390pF, Unless Otherwise Specified

OSC

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

EN_HI

EN_LO

TM, S TM, S

EL_HI EL_LO

EN Input High Level 2.6 V EN Input Low Level 1V Enable Pull-up Current VEN = 0 -4 -2.5 µA Input High Level 2.6 V Input Low Level 1V

Pin Descriptions

PIN NUMBER PIN NAME PIN FUNCTION

1 COMP Error amplifier output; place loop compensation components here 2 VREF B andgap reference bypass capacitor; typically 0.01µF to 0.047µF to SGND 3 FB Voltage feedback input; connected to external resistor divider between V

output; also used for speed-up capacitor connection 4 VO Output sense for fixed output; also used for speed-up capacitor connection 5 VTJ Junction temperature monitor output, connected to a 0.01µF - 0.047µF to SGND 6 TM Stress test enable; allows ±5% output movement; needs a pull-down resistor (1k - 100k); connect to

SGND if function is not used 7 SEL Positive or negative voltage margining set pin; needs a pull-down resistor (1k - 100k); connect to SGND

if function is not used

8, 9, 10, 11, 12, 13 LX Inductor drive pin; high current output whose average voltage equals the regulator output voltage

14, 15 NC Not used 16, 17, 18 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS Power FET 19, 20, 21 VIN Power supply input of the regulator; connected to the drain of the high-side PMOS Power FET

22 VDD Control circuit positive supply; connected to V

through an internal 20Ω resistor

23 PG Power-good window comparator output; logic 1 when regulator output is within ±10% of target output

voltage

24 EN Chip enable, active high; a 2µA internal pull-up current enables the device if the pin is left open; a

capacitor can be added at this pin to delay the start of a converter

25 STP Auxilliary supply tracking positive input; tied to regulator output to synchronize start-up with a second

supply; leave open for standalone operation; 2µA internal pull-up current

26 STN Auxiliary supply tracking negative input; connect to output of a second supply to synchronize start-up;

leave open for standalone operation; 2µA internal pull-up current 27 COSC Oscillator timing capacitor (see performance curves) 28 SGND Control circuit negative supply or signal ground

and SGND for adjustable

OUT

FN7360.5

November 5, 2007

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