intersil EL7158 DATA SHEET

®

www.BDTIC.com/Intersil

EL7158

Data Sheet May 14, 2007

Ultra-High Current Pin Driver

The EL7158 high performance pin
driver with three-state is suited to

many ATE and level-shifting
applications. The 12A peak drive capability makes this part
an excellent choice when driving high capacitance loads.

The output pin OUT is connected to input pins VH or VL
respectively, depending on the status of the IN pin. When the
OE pin is active low, the output is placed in the three-state
mode. The isolation of the output FETs from the power
supplies enables VH and VL to be set independently,
enabling level-shifting to be implemented. Related to the
EL7155, the EL7158 adds a lower supply pin VS- and makes
VL an isolated and independent input. This feature adds
applications flexibility and improves switching response due
to the increased enhancement of the output FETs.

This pin driver has improved performance over existing pin
drivers. It is specifically designed to operate at voltages
down to 0V across the switch elements while maintaining
good speed and ON-resistance characteristics.

Available in the 8 Ld SOIC package, the EL7158 is specified
for operation over the full -40°C to +85°C temperature range.

Pinout

EL7158

(8 LD SOIC)

TOP VIEW

VS+

OE

GND

1

L

2

O
G

IN

I

3

C

4

8

VH

OUT

7

VL

6

VS-

5

FN7349.2

Features

• Clocking speeds up to 40MHz

• 12ns t

at 2000pF C

R/tF

LOAD

• 0.2ns rise and fall times mismatch

• 0.5ns t

ON-tOFF

prop delay mismatch

• 3.5pF typical input capacitance

• 12A peak drive

• Low ON-resistance of 0.5Ω

• High capacitive drive capability

• Operates from 4.5V to 12V

• Pb-free plus anneal available (RoHS compliant)

Applications

• ATE/burn-in testers

• Level shifting

•IGBT drivers

• CCD drivers

Ordering Information

PART

NUMBER

EL7158IS 7158IS 8 Ld SOIC - MDP0027
EL7158IS-T7 7158IS 8 Ld SOIC 7” MDP0027
EL7158IS-T13 7158IS 8 Ld SOIC 13” MDP0027
EL7158ISZ

(Note)
EL7158ISZ-T7

(Note)
EL7158ISZ-T13

(Note)

NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.

PART

MARKING PACKAGE

7158ISZ 8 Ld SOIC

(Pb-free)

7158ISZ 8 Ld SOIC

(Pb-free)

7158ISZ 8 Ld SOIC

(Pb-free)

TAPE &

REEL

7” MDP0027

13” MDP0027

PKG.

DWG. #

- MDP0027

1

Copyright © Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

EL7158

www.BDTIC.com/Intersil

Absolute Maximum Ratings (T

Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = T

Electrical Specifications V

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

V

IH

I

IH

V

IL

I

IL

C

IN

R

IN

OUTPUT

R

OVH

R

OVL

I

OUT

I

PK

I

DC

POWER SUPPLY

I

S

I

VH

SWITCHING CHARACTERISTICS

t

R

t

F

t

RFΔ

t

d-1

t

d-2

t

dΔ

t

d-3

t

d-4

SR+ V
SR- V

Logic ‘1’ Input Voltage 2.4 V
Logic ‘1’ Input Current VIH = VS+0.110µA
Logic ‘0’ Input Voltage 0.8 V
Logic ‘0’ Input Current VIL = 0V 0.1 10 µA
Input Capacitance 3.5 pF
Input Resistance 50 MΩ

ON-Resistance VH to OUT I
ON-Resistance VL to OUT I
Output Leakage Current OE = 0V, OUT = VH/V
Peak Output Current

(linear resistive operation)

Continuous Output Current Source/Sink 500 mA

Power Supply Current Inputs = VS+1.33mA
Off Leakage at VH and V

Rise Time CL = 2000pF 12.0 ns
Fall Time CL = 2000pF 12.2 ns
tR, tF Mismatch CL = 2000pF 0.2 ns
Turn-Off Delay Time CL = 2000pF 22.5 ns
Turn-On Delay Time CL = 2000pF 22.0 ns
t

Mismatch CL = 2000pF 0.5 ns

d-1-td-2

Three-State Delay Enable 22 ns
Three-State Delay Disable 22 ns

+ Slew Rate R

OUT

- Slew Rate R

OUT

= +25°C) Thermal Information

A

- -0.3V, VS +0.3V

S

A

+ = +12V, VH = +12V, VL = 0V, VS- = 0V, TA = +25°C, unless otherwise specified.

S

= -500mA 0.5 1 Ω

OUT

= +500mA 0.5 1 Ω

OUT

Source 12 A
Sink 12 A

L

VH, VL = 0V 4 10 µA

= 6Ω 800 V/µs

LOAD

= 6Ω 800 V/µs

LOAD

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +15 0°C

Ambient operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

L

0.1 10 µA

2

FN7349.2

May 14, 2007

EL7158

www.BDTIC.com/Intersil

Electrical Specifications V

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

V

IH

I

IH

V

IL

I

IL

C

IN

R

IN

OUTPUT

R

OVH

R

OVL

I

OUT

I

PK

I

DC

POWER SUPPLY

I

S

V

H

SWITCHING CHARACTERISTICS

t

R

t

F

t

RFΔ

t

d-1

t

d-2

t

dΔ

t

d-3

t

d-4

SR+ V
SR- V

Logic ‘1’ Input Voltage 2.0 V
Logic ‘1’ Input Current VIH = VS+0.110µA
Logic ‘0’ Input Voltage 0.8 V
Logic ‘0’ Input Current VIL = 0V 0.1 10 µA
Input Capacitance 3.5 pF
Input Resistance 50 MΩ

ON-Resistance VH to OUT I
ON-Resistance VL to OUT I
Output Leakage Current OE = 0V, OUT = VH/V
Peak Output Current

(linear resistive operation)

Continuous Output Current Source/Sink 500 mA

Power Supply Current Inputs = VS+12.5mA
Off Leakage at VH and V

Rise Time CL = 2000pF 11 ns
Fall Time CL = 2000pF 11 ns
tR, tF Mismatch CL = 2000pF 0 ns
Turn-Off Delay Time CL = 2000pF 20.5 ns
Turn-On Delay Time CL = 2000pF 20.0 ns
t

Mismatch CL = 2000pF 0.5 ns

d-1-td-2

Three-State Delay Enable 20 ns
Three-State Delay Disable 20 ns

+ Slew Rate R

OUT

- Slew Rate R

OUT

+ = +12V, VH = +1.2V, VL = 0V, VS- = 0V, TA = +25°C, unless otherwise specified. (Continued)

S

= -500mA 0.5 1 Ω

OUT

= +500mA 0.5 1 Ω

OUT

L

Source 1.2 A
Sink 1.2 A

L

VH, VL = 0V 4 10 µA

= 6Ω 80 V/µs

LOAD

= 6Ω 80 V/µs

LOAD

0.1 10 µA

3

FN7349.2

May 14, 2007